QMP 7.5 R/C-1 Rev.
1
Channabasaveshwara Institute of Technology
(Affiliated to VTU, Belgaum & Approved by AICTE, New Delhi)
(NAAC Accredited & ISO 9001:2015 Certified Institution)
NH 206 (B.H. Road), Gubbi, Tumkur – 572 216. Karnataka
Digital VLSI Design QUESTION BANK
Module-01
1. With a neat diagram and equations explain the Metal Oxide Semiconductor (MOS)
Structure
2.
Calculate the threshold voltage VTO at VSB = 0, for a polysilicon gate n-channel MOS
transistor, with the following parameters: substrate doping density N A = 1016 cm-3 ,
polysilicon gate doping density ND = 2 x 1020 cm-3 , gate oxide thickness tox = 500 A, and
oxide-interface fixed charge density Nox = 4 x 1010 cm-2.
3. Describe the behaviour of MOS system under external bias with energy band diagram and
relevant equations.
4. Derive the expression for threshold voltage VT in terms of body effect and surface potential
5. Draw the neat circuit diagram of NMOS inverter circuit and explain the circuit operation
with its VTC curve.
6. For a resistive-load inverter circuit with VDD= 5V, k’n= 20 uA/V2, V T0= 0.8V, RL = 200
KΩ, and W/L = 2. Calculate the critical voltages (V OL,'VOH VIL, VIH) on the VTC and find
the noise margins of the circuit.
7. Derive expressions for VOH,VOL,VIL and VIH in terms of threshold voltage for of Resistive-
Load Inverter
8. With a neat diagram explain the operation of Enhancement-Load nMOS Inverter
9. With a neat diagram explain the structure and operation of an n-channel MOSFET.
Module-2
1. With a neat circuit diagram and necessary equations explain the operation of cmos inverter
and also indicate different operating regions of cmos inveter
2. Explain the effect of capacitance on Cascaded CMOS inverter stages and First-stage
CMOS inverter
3. Derive the equation for the propagation delay time for high-to-low output transition
4. For the CMOS inverter shown in Fig with a power supply voltage of VDD = 5 V,
determine the fall time tfall which is defined as the time elapsed between the time point at
which Vout = V90% = 4.5 V and the time point at which VOut = V10% = 0.5 V. Use both
the average-current method and the differential equation method for calculating t fall. output
load capacitance is 1 pF. The nMOS transistor parameters are given as
un C.ox = 20uA/V2
(W/L) = 10
VT = 1.0 V
5. Write short notes on CMOS Ring Oscillator Circuit
6. Write short notes on Estimation of Interconnect Parasitics
7. Explain Interconnect Capacitance Estimation
8. Explain Interconnect Resistance Estimation
9. Briefly explain RC Delay Models
10. Explain how to calculate The Elmore Delay for Rc tree network
11. Explain Switching Power Dissipation of CMOS Inverters
Module 3
1. Explain the operation of Full CMOS SRAM Cell
2. With a neat circuit diagram explain the operation of SRAM Read Circuitry.
3. Explain the operation of 4-bit x 4-bit NOR-based ROM array.
4. With a neat circuit diagram explain Basic structure of the resistive-load SRAM cell
5. With a neat circuit diagram explain CMOS static RAM column with data write and data
Read circuitry.
6. With a neat circuit diagram explain the operation of One-Transistor DRAM Cell
7. With a neat circuit diagram explain the operation of SRAM write Circuitry.
8. With a neat circuit diagram explain the operation of Three-Transistor DRAM Cell.
Mod-4
1. Explain how to overcome threshold voltage drop in integrated circuits using voltage
bootstrapping technique.
2. Explain Dynamic bootstrapping arrangement technique.
3. With a neat circuit diagram Explain the Charge Leakage in nMOS pass transistor
4. With a neat circuit diagram explain the Basic Principles of Pass Transistor Circuits.
5. Explain Charge Storage and Charge Leakage in nMOS pass transistor.
6. With a neat generalized circuit diagram explain domino CMOS logic gate.
7. With a neat diagram explain the operation of Dynamic Pass Transistor Circuits.
8. With a neat circuit diagram explain the operation of CMOS Transmission Gate Logic
9. With a neat generalized circuit diagram explain Cascaded domino CMOS logic gates.
10. With a neat circuit diagram explain the operation of Dynamic CMOS Logic (Precharge-
Evaluate Logic).
Mod-5
1. Explain the operation of BiCMOS inverter circuit, with four MOSFETs and two BJTs.
2. Explain the Structure and Operation of Bipolar Junction Transistor (BJT)
3. Explain Static Characteristics of BJT Inverter Circuit
4. Explain how to analyze Dynamic Behavior of BJTs using Charge-Control Model
5. Explain BiCMOS inverter circuit with resistive base pull-down
6. Briefly explain Switching Delay In BICMOS Logic Circuits
7. Write a short notes on BICMOS APLLICATIONS
8. Explain the operation of BiCMOS NOR2 gate.
9. Explain the operation of BiCMOS complex logic gate.
10. Explain the operation of BiCMOS NAND2 gate.
