Fundamentals of Digital Electronics (BE03003031)

A Laboratory Manual for

Fundamentals of Digital Electronics (BE03003031)

B.E. Semester 3
(Biomedical Engineering)

Directorate of Technical Education, Gandhinagar,

Gujarat
Fundamentals of Digital Electronics (BE03003031)

Government Engineering College,

Sector-28, Gandhinagar

Certificate

This is to certify that Mr./Ms. ___________________________________ Enrolment No.

_______________ Of B.E. Semester _____ Biomedical Engineering of this Institute (GTU

Code: ) has satisfactorily completed the Practical / Tutorial work for the subject

Fundamentals of Digital Electronics (BE03003031) for the academic year ____________.

Place: __________

Date: __________

Name and Sign of Faculty member

Head of the Department

Fundamentals of Digital Electronics (BE03003031)

Preface
Main motto of any laboratory/practical/field work is for enhancing required skills as well as
creating ability amongst students to solve real time problem by developing relevant
competencies in psychomotor domain. By keeping in view, GTU has designed competency
focused outcome-based curriculum for engineering degree programs where sufficient
weightage is given to practical work. It shows importance of enhancement of skills amongst
the students and it pays attention to utilize every second of time allotted for practical amongst
students, instructors and faculty members to achieve relevant outcomes by performing the
experiments rather than having merely study type experiments. It is must for effective
implementation of competency focused outcome-based curriculum that every practical is
keenly designed to serve as a tool to develop and enhance relevant competency required by
the various industry among every student. These psychomotor skills are very difficult to
develop through traditional chalk and board content delivery method in the classroom.
Accordingly, this lab manual is designed to focus on the industry defined relevant outcomes,
rather than old practice of conducting practical to prove concept and theory.
By using this lab manual students can go through the relevant theory and procedure in
advance before the actual performance which creates an interest and students can have basic
idea prior to performance. This in turn enhances pre-determined outcomes amongst students.
Each experiment in this manual begins with competency, industry relevant skills, course
outcomes as well as practical outcomes (objectives). The students will also achieve safety
and necessary precautions to be taken while performing practical.
This manual also provides guidelines to faculty members to facilitate student centric lab
activities through each experiment by arranging and managing necessary resources in order
that the students follow the procedures with required safety and necessary precautions to
achieve the outcomes. It also gives an idea that how students will be assessed by providing
rubrics.
Fundamental of Digital Electronics course will enable the students to learn about
fundamentals and design concepts of digital circuits such as Logic operation of Gates and its
realizations for different logic families, Representations form of Boolean algebra and its
different method of minimization. It is also included design concepts of various
combinational circuits using Programmable logic devices and sequential circuits with its
state representation.
Utmost care has been taken while preparing this lab manual however always there is chances
of improvement. Therefore, we welcome constructive suggestions for improvement and
removal of errors if any.
Fundamentals of Digital Electronics (BE03003031)

Disclaimer: This lab manual includes information and content sourced from various books
and websites. The authors of these books/websites are acknowledged and credited within
the relevant sections of the manual. While every effort has been made to accurately
represent their ideas and theories, any errors are unintentional. The inclusion of these
sources does not imply endorsement or affiliation with the authors or their publishers. This
Laboratory manual is only for free education purpose without any commercial use.

Practical – Course Outcome matrix

Course Outcomes (COs):

1. Understand and evaluate various Number System and binary codes with their
arithmetic operations in digital design.
2. Understand the fundamental logic operations of gates and their various
implementations, the principles of Boolean Algebra, and various techniques
for minimizing switching functions.
3. Design and understand the construction and operation of various
combinational circuits and their applications, as well as utilizing
programmable logic devices such as PAL, PLA, and PROM.
4. Understand and design various sequential logic circuits, including their
operations, types of flip-flops, and applications.
5. Understand and design various types of registers and counters, including their
functions.

Sr. CO CO CO CO CO
Objective(s) of Experiment
No. 1 2 3 4 5

To study & implement the logic operation of

AND, OR & NOT gates and their TTL and
CMOS realization.
1. To understand the logic operation of Basic
Gates.
1. √ √
2. To design AND, OR and NOT gate logic
operations using TTL and CMOS
realizations.
3. To implement logic operations of Basic
gates using Gate ICs.

To study & implement the logic operation of

Universal gates and their realization using AOI
2. logic. √ √
1. To understand the logic operation of
Universal Gates.
Fundamentals of Digital Electronics (BE03003031)

2. To implement logic operations of

Universal gates using AOI Gate ICs.
3. To verify the truth tables of Universal
gates using breadboard and/or Digital Lab
kits.
To study & implement the EX-OR & EX-NOR
gates.
1. To understand the logic operation of EX-
3. OR & EX-NOR Gates. √ √
2. To verify the truth tables of EX-OR &
EX-NOR using breadboard and/or Digital
Lab kits.

To Implement of Boolean Logic Functions using

AOI and Universal logic.
4. √ √
1. To design Boolean Logic functions using
AOI and Universal logic.

To study & implement Half Adder and Full

Adder using AOI and Universal logic.
1. To design Half Adder and Full Adder
using AOI and Universal logic.

5. 2. To implement Half and Full Adder using √

Basic Gate ICs.
3. To implement and verify the truth tables
of Half and Full Adder using breadboard
and/or Digital Lab kits.

To study & implement Half Subtractor and Full

Subtractor using AOI and Universal logic.
1. To design Half Subtractor and Full
Subtractor using AOI and Universal logic.
6. 2. To implement Half and Full Subtractor √
using Basic Gate ICs.
3. To implement and verify the truth tables
of Half and Full Subtractor using
breadboard and/or Digital Lab kits.
Fundamentals of Digital Electronics (BE03003031)

To study & implement Gray to Binary &

Binary to Gray code conversion using Gate
ICs.
1. To design Gray to Binary & Binary to
Gray code conversion using AOI and
Universal logic.
7. √ √
2. To implement Gray to Binary & Binary to
Gray code conversion using Basic Gate
ICs.
3. To verify the truth tables Gray to Binary
& Binary to Gray code conversion using
breadboard and/or Digital Lab kits.

To study & implement 1-bit & 2-bit

Magnitude Comparator using Gate ICs.
1. To design 1-bit & 2-bit Magnitude
Comparator AOI and Universal logic.
8. 2. To implement 1-bit & 2-bit Magnitude √
Comparator using Basic Gate ICs.
3. To verify the truth tables of 1-bit & 2-bit
Magnitude Comparator using breadboard
and/or Digital Lab kits.

To study & implement Encoder and Decoder

using Gate ICs.
1. To design Encoder and Decoder using
9. √
AOI and Universal logic.
2. To implement Encoder and Decoder using
Basic Gate ICs.

To study & implement Multiplexer and

Demultiplexer using Gate ICs.
1. To design Multiplexer and
Demultiplexer using AOI and
10. Universal logic. √
2. To implement Multiplexer and
Demultiplexer using Basic Gate ICs.
3. To study working of the Multiplexer
and Demultiplexer using breadboard.
Fundamentals of Digital Electronics (BE03003031)

To study about different Flip-Flops, their

Excitation tables, and implementation using
Gate ICs.
1. To study about different types of
11. Flip-Flops and their excitation tables. √
2. To implement flipflops or latches
using NAND & NOR gate.
3. To study working of the Flipflops
using breadboard and/or Digital Lab
kits.

To study about design of Counters and shift

register.
1. To study about working of Counters
12. and shift register. √
2. To design types of Counters and Shift
registers.
3. To study about Counters and shift
register using Digital Lab kits.
Fundamentals of Digital Electronics (BE03003031)

Industry Relevant Skills

The following industry relevant competency are expected to be developed in the student
by undertaking the practical work of this laboratory.
1. Mathematics
2. logic development
3. Programming skills
4. Software basic skills
Guidelines for Faculty members
1. Teacher should provide the guideline with demonstration of practical to the
students with all features.
2. Teacher shall explain basic concepts/theory related to the experiment to the students
before starting of each practical.
3. Involve all the students in performance of each experiment.
4. Teacher is expected to share the skills and competencies to be developed in the
students and ensure that the respective skills and competencies are developed in
the students after the completion of the experimentation.
5. Teachers should give opportunity to students for hands-on experience after the
demonstration.
6. Teacher may provide additional knowledge and skills to the students even though
not covered in the manual but are expected from the students by concerned
industry.
7. Give practical assignment and assess the performance of students based on task
assigned to check whether it is as per the instructions or not.
8. Teacher is expected to refer complete curriculum of the course and follow the
guidelines for implementation.
Instructions for Students
1. Students are expected to carefully listen to all the theory classes delivered by the faculty
members and understand the COs, content of the course, teaching and examination
scheme, skill set to be developed etc.
2. Students shall organize the work in the group and make record of all observations.
3. Students shall develop maintenance skill as expected by industries.
4. Student shall attempt to develop related hand-on skills and build confidence.
5. Student shall develop the habits of evolving more ideas, innovations, skills etc. apart
from those included in scope of manual.
6. Student shall refer technical magazines and data books.
7. Student should develop a habit of submitting the experimentation work as per the
schedule and s/he should be well prepare.
Fundamentals of Digital Electronics (BE03003031)

Here are some general rubrics that can be applied to practical:

1. Knowledge and Understanding: This rubric assesses the student's ability to understand
and apply theoretical concepts related to the practical.

2. Programming skills: This rubric evaluates the student's ability to write a code and perform
practical tasks accurately and effectively.

3. Communication skills: This rubric evaluates the student's ability to effectively

communicate the results of the practical, including written reports, presentations, and
discussions.

4. Problem solving: This rubric evaluates the student's ability to solve/answer given quiz
correctly.

5. Time Management: This rubric evaluates the student's ability to manage their time
effectively during the practical, including setting priorities and meeting deadlines.
 Fundamentals of Digital Electronics (BE03003031)

Index
(Progressive Assessment Sheet)

Sr. Objective(s) of Experiment Page Date Date of Assessme Sign. of Rema

No. No. of submis nt Teacher rks
perfor sion Marks with
mance date
To study & implement the logic
1. operation of AND, OR & NOT gates
and their TTL and CMOS realization.
To study & implement the logic
2. operation of Universal gates and
their realization using AOI logic.
To study & implement the EX-OR &
3.
EX-NOR gates.
To Implement of Boolean Logic
4. Functions using AOI and Universal
logic.
To study & implement Half Adder
5. and Full Adder using AOI and
Universal logic.
To study & implement Half Subtractor
6. and Full Subtractor using AOI and
Universal logic.
To study & implement Gray to
7. Binary & Binary to Gray code
conversion using Gate ICs.
To study & implement 1-bit & 2-bit
8. Magnitude Comparator using Gate
ICs.
To study & implement Encoder and
9.
Decoder using Gate ICs.
To study & implement Multiplexer
10.
and Demultiplexer using Gate ICs.
To study about different Flip-
11. Flops, their Excitation tables, and
implementation using Gate ICs.
To study about design of Counters
12.
and shift register.
Total
Fundamentals of Digital Electronics (BE03003031)

Practical No: 0

Commissionerate of Technical Education

➢ To provide globally competitive technical education;

➢ Remove geographical imbalances and inconsistencies;
➢ Develop student friendly resources with a special focus on girls’ education and support
to weaker sections;
➢ Develop programs relevant to industry and create a vibrant pool of technical
professionals

Government Engineering College, Sector-28, Gandhinagar

Institute Vision

➢ To be a premier engineering institution, imparting quality education for innovative

solutions relevant to society and environment
Institute Mission
1. To develop human potential to its fullest extent so that intellectual and innovative
engineers can emerge in a wide range of professions.
2. To advance knowledge and educate students in engineering and other areas of scholarship
that will best serve the nation and the world in future.
3. To produce quality engineers, entrepreneurs and leaders to meet the present and future
needs of society as well as environment.
Biomedical Engineering Department

Vision
➢ To play a pivotal role in promoting human health through the best of current
and future technologies from the field of engineering and medical science to bridge the
gap between medicine and engineering.

Mission
1. To serve the fundamental principles of engineering to human health care and well-
being for medical industries, health care providers, governmental agencies, and
academic entities.
2. To create a linkage between content generation, research in critical areas and imparting
education for integrating our knowledge with the advancements in Hospitals and
Industries.
Fundamentals of Digital Electronics (BE03003031)

3. To obtain and maintain the competitive edge in the hospitals and industries, for
identification and nurturing of talent and learning in academic entities

2. Program Outcomes as defined by NBA (PO)

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and

design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research

methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.

7. Environment and sustainability: Understand the impact of the professional engineering

solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.

9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
Fundamentals of Digital Electronics (BE03003031)

11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.

3. PSOs and PEOs of the department

Program Specific Outcomes (PSOs)

PSO-1: Operate and maintain Biomedical Instruments.
PSO-2: Design and Develop Biomedical Instruments.
PSO-3: Acquire and develop the ability for life-long learning needed for a successful
professional career such as professional and ethical attitude, effective communication skills
and teamwork skills.
Program Educational Objectives (PEOs)
PEO-1: To have mathematics, science, and engineering fundamentals expertise at the interface
of engineering and the life sciences, enabling them to take leadership roles in the field of
biomedical engineering.
PEO-2: To have ability to use their problem solving skills and multidisciplinary perspectives
to understand and advance scientific discoveries and technological innovations across
professional and disciplinary boundaries with the highest professional and ethical standards.
PEO-3: To possess technical and practical skills to identify, formulate, and solve open-ended
problems with medical relevance, including the design of devices, systems, and processes to
improve human health.
PEO-4: To develop successful careers related to Biomedical Engineering like biomedical
electronics, medical instrumentation, medical imaging, biomedical signal processing,
rehabilitation engineering, and neuro engineering or another area of the student’s choosing,
through employment in industry or government, or through pursuit of graduate or professional
degrees; and Successfully practice biomedical engineering to serve state and regional
industries, hospitals, government agencies, or national and international industries.
PEO-5: Work professionally in one or more of the following areas: biomedical electronics,
medical instrumentation, biomedical signal processing, rehabilitation engineering, and neuro
engineering.
PEO-6: To enhance career skills through life-long learning.
Fundamentals of Digital Electronics (BE03003031)

Course Outcomes (COs):

1. Understand and evaluate various Number System and binary codes with their
arithmetic operations in digital design.
2. Understand the fundamental logic operations of gates and their various
implementations, the principles of Boolean Algebra, and various techniques
for minimizing switching functions.
3. Design and understand the construction and operation of various
combinational circuits and their applications, as well as utilizing
programmable logic devices such as PAL, PLA, and PROM.
4. Understand and design various sequential logic circuits, including their
operations, types of flip-flops, and applications.
5. Understand and design various types of registers and counters, including their
functions.
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 1
Date:

AIM: To study & implement the logic operation of AND, OR & NOT gates
and their TTL and CMOS realization.

Objectives: -
1. To understand the logic operation of Basic Gates.
2. To design AND, OR and NOT gate logic operations using TTL and CMOS
realizations.
3. To implement logic operations of Basic gates using Gate ICs.

Theory: -

Logic gates are the basic building blocks of any digital system. It is an electronic circuit having
one or more than one input and only one output. The relationship between the input and the
output is based on a certain logic. Based on this, logic gates are named as AND gate, OR gate,
NOT gate etc.

NOT Gate

The NOT gate is a digital logic gate with one input and one output that operates an inverter
operation of the input.The output of the NOT gate is the reverse of the input. When the input
of the NOT gate is true then the output will be false and vice versa. The symbol and truth table
of a NOT gate with one input is shown below in Fig.1.

Fig:1. NOT gate symbol and Truth Table

In transistor NOT gate as shown in Fig.2. the input to the gate may be 0V or +5V. When A =
0V, the transistor T is OFF. As no current flows through R, no voltage drop occurs across R.
Hence, the output voltage A' =+5V. When the input X=+5V, T is ON and the output voltage
A' = Vce(sat) = 0V. The truth table for the NOT gate circuit is as shown below.

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Fundamentals of Digital Electronics (BE03003031)

Table: 3 Truth table

Inputs Outputs
A A'
0V 5V
5V 0V

Fig: 2. Transistor NOT gate Fig: 3. CMOS Transistor NOT gate

CMOS Transistor as Inverter

CMOS means – Complementary Metal oxide semi- conductor. MOS inverters are
widely used and MOSFET inverters find their use in chip design. Another advantage of CMOS
inverters is that they have large noise margin in both high and low logic states and have good
logic buffer characteristics also.
A CMOS inverter has an NMOS and a PMOS transistors, connected at Drain and Gate.
The supply voltage VDD is given at the source terminal of PMOS and the source terminal of
NMOS transistor is grounded. The input voltage Vin is given at the gate terminals and the
output Vout is collected at drain terminals.
The key point to remember about the CMOS inverter is that it doesn’t contain any
resistors so there is no voltage drop. This makes the CMOS inverter more power efficient.
Whenever the input voltage of the CMOS inverter varies between 0 volts and 5 volts the state
of PMOS and NMOS also varies.
The switch conditions will depend on the Drain, Source and Gate voltages, which are
explained as,

NMOS
NMOS is built on a p-type substrate with n-type source and drain diffused on it. In NMOS, the
majority carriers are electrons. When a high voltage is applied to the gate, the NMOS will
conduct. Similarly, when a low voltage is applied to the gate, NMOS will not conduct. NMOS

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Fundamentals of Digital Electronics (BE03003031)

are considered to be faster than PMOS, since the carriers in NMOS, which are electrons, travel
twice as fast as the holes.

Fig.4. NMOS
PMOS
P- channel MOSFET consists P-type Source and Drain diffused on an N-type substrate.
Majority carriers are holes. When a high voltage is applied to the gate, the PMOS will not
conduct. When a low voltage is applied to the gate, the PMOS will conduct. The PMOS devices
are more immune to noise than NMOS devices.

Fig.5. PMOS
In CMOS technology, both N-type and P-type transistors are used to design logic functions.
The same signal which turns ON a transistor of one type is used to turn OFF a transistor of the
other type. This characteristic allows the design of logic devices using only simple switches,
without the need for a pull-up resistor.
In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down
network between the output and the low voltage power supply rail (Vss or quite often ground).
Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of p-
type MOSFETs in a pull-up network between the output and the higher-voltage rail (often
named Vdd).
Thus, if both a p-type and n-type transistor have their gates connected to the same input,
the p-type MOSFET will be ON when the n-type MOSFET is OFF, and vice-versa. The
networks are arranged such that one is ON and the other OFF for any input pattern as shown
in the figure below.

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Fundamentals of Digital Electronics (BE03003031)

Fig. 6. CMOS
The inverter circuit as shown in the Fig. 7 below. It consists of PMOS and NMOS FET. The
input A serves as the gate voltage for both transistors.

Fig. 7. CMOS Transistor NOT Gate

The NMOS transistor has an input from Vss (ground) and PMOS transistor has an input from
Vdd. The terminal Y is output. When a high voltage (~ Vdd) is given at input terminal (A) of
the inverter, the PMOS becomes open circuit and NMOS switched OFF so the output will be
pulled down to Vss. When a low-level voltage (<Vdd, 0V) applied to the inverter, the NMOS
switched OFF and PMOS switched ON. So the output becomes Vdd or the circuit is pulled
up to Vdd.

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Fundamentals of Digital Electronics (BE03003031)

AND Gate
The AND gate is a digital logic gate with ‘n’ i/ps one o/p, which perform logical conjunction
based on the combinations of its inputs.The output of this gate is true only when all the inputs
are true. When one or more inputs of the AND gate’s i/ps are false, then only the output of the
AND gate is false. The symbol and truth table of an AND gate with two inputs is as shown
below in Fig.8..

Fig.8. AND gate symbol and Truth Table

In the transistor AND gate as shown in Fig.9, when X=0V and Y=0V or when X=0V
and Y=+5V or when X=+5V and Y=+0V, both the transistors T1 and T2 are OFF. Transistor
T3 gets enough base drive from the supply through R3 and so, T3 will be ON. Hence, the
Table: 2 Truth table output voltage Z= Vce(sat) =0V. When both X
Inputs Outputs and Y are equal to +5V, both the transistors T1
X Y Z and T2 will be ON and, therefore, the voltage at
0V 0V 0V the collector of transistors T1 will drop. So, T3
0V 5V 0V does not get enough base drive and, therefore,
5V 0V 0V remains OFF. Hence no current flows through the
5V 5V 5V collector resistor of T3 and, therefore, no voltage
drop occurs across it. Hence output voltage,
X=5V. The truth table for the above gate circuits is as shown below.

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Fundamentals of Digital Electronics (BE03003031)

Fig:9 Two-input transistor AND gate

Fig:10. CMOS realization of two input AND gate

CMOS realization of two input AND gate as show in Fig.10. If either input A or B is logic 0,
at least one of the NMOS transistors will be OFF, breaking the path from C to Ground. But at
least one of the pMOS transistors will be ON, creating a path from C to VDD. Hence, the
output C will be high.When a high voltage (~ Vdd) is given at input terminal (C) of the inverter,
the PMOS becomes open circuit and NMOS switched On so the output will be pulled down to
Vss (Low logic 0= 0V).
If both inputs are high, both of the NMOS transistors will be ON and both of the pMOS
transistors will be OFF. Hence, the output will be logic low. When a low-level voltage (<Vdd,
0V) applied to the inverter input terminal (C), the NMOS switched OFF and PMOS switched
ON. So the output becomes Vdd or the circuit is pulled up to Vdd (High logic 1=5V).

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Fundamentals of Digital Electronics (BE03003031)

OR Gate
The OR gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs a logical conjunction
based on the combinations of its inputs.The output of the OR gate is true only when one or
more inputs are true. If all the i/ps of the gate are false, then only the output of the OR gate is
false. The symbol and truth table of an OR gate with two inputs is shown belowin Fig.11.

Fig.11. OR gate symbol and Truth Table

In transistor OR gate as shown in Fig.12, when X=0V and Y=0V, both the transistors
T1 and T2 are OFF. Transistors T3 gets enough base drive from +5V through R3 and, therefore,
it will be ON. The output voltage, Z =Vce(sat)=0V. When either X=+5V or Y=+5V or when
both X and Y are equal to +5V, the corresponding transistor T1 or T2 is ON or both T1 and
T2 will be ON and, therefore, the voltage at the collector of T1 is = Vce(sat)=0V. This cannot
forward bias the base emitter junction of T3 and, therefore, it will remain OFF. Hence, the
output voltage will be Z=5V. The truth table for the above gate circuits is as shown below.

Table: 3 Truth table

Inputs Outputs
X Y Z
0V 0V 0V
0V 5V 5V
5V 0V 5V
5V 5V 5V

Fig:5 Two-input transistor OR gate

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Fundamentals of Digital Electronics (BE03003031)

Fig:13. CMOS realization of two input OR gate

CMOS realization of two input OR gate as show in Fig.13. If either input A or B is
logic 1, at least one of the NMOS transistors will be OFF, Open the path from output of inverter
to Ground. But at least one of the pMOS transistors will be ON, creating a path from output of
inverter to Ground. Hence, the output of inverter will be low.When a low voltage (~ Vdd) is
given at input terminal of the inverter, the PMOS becomes on circuit and NMOS switched OFF
so the output will be pulled up to Vdd (high logic 1= 5V).
If both inputs are low, both of the NMOS transistors will be OFF and both of the pMOS
transistors will be ON. Hence, the output of NOR gate will be logic high. When a high-level
voltage (Vdd, 5V) applied to the inverter input terminal (C), the NMOS switched ON and
PMOS switched OFF. So the output becomesVdd or the circuit is pulled down to Vss (Low
logic 0=0V).

PIN DIAGRAM OF BASIC GATES ICs:

7404 NOT Gate: 7408 AND Gate:

7432 OR Gate:

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 Fundamentals of Digital Electronics (BE03003031)

❖ Implement logic operations of Basic gates using Gate ICs.

CIRCUIT DIAGRAM:

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Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

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Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

Using Transistor Logic

AND GATE
Input A Input B I/P A I/P B Output O/P
(Logic) (Logic) Volt(V) Volt(V) A.B(Logic) Volt(V)
R=
0(L) 0(L) 0(L)
0(L) 1(H) 0(L)
1(H) 0(L) 0(L)
1(H) 1(H) 1(H)

OR GATE
Input A Input B I/P A I/P B Output O/P
(Logic) (Logic) Volt(V) Volt(V) A+B(Logic) Volt(V)
R=
0(L) 0(L) 0(L)
0(L) 1(H) 1(H)
1(H) 0(L) 1(H)
1(H) 1(H) 1(H)

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Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:
Using Gate Ics.

NOT GATE
INPUT I/P VOLT(V) OUTPUT A' O/P
(logic) (logic) VOLT(V)
A
0(L) 1(H)
1(H) 0(L)

AND GATE
Input A Input B I/P A I/P B Output O/P Volt(V)
(Logic) (Logic) Volt(V) Volt(V) A.B(Logic)
0(L) 0(L) 0(L)
0(L) 1(H) 0(L)
1(H) 0(L) 0(L)
1(H) 1(H) 1(H)

OR GATE
Input A Input B I/P A I/P B Output O/P Volt(V)
(Logic) (Logic) Volt(V) Volt(V) A.B(Logic)
0(L) 0(L) 0(L)
0(L) 1(H) 1(H)
1(H) 0(L) 1(H)
1(H) 1(H) 1(H)

12
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
1. A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
2. M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
3. R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
4. Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
5. Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
6. https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
7. https://www.electronics-tutorials.ws/logic/logic_4.html
8. https://www.javatpoint.com/logic-gates
9. http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

13
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 2
Date:

AIM: To study & implement the logic operation of Universal gates and
their realization using AOI logic.
Objectives: -
1. To understand the logic operation of Universal Gates.
2. To implement logic operations of Universal gates using AOI Gate ICs.
3. To verify the truth tables of Universal gates using breadboard and/or
Digital Lab kits.

Theory
A universal gate is a gate which can implement any Boolean function without need to use
any other gate type. The NAND and NOR gates are universal gates. In practice, this is
advantageous since NAND and NOR gates are economical and easier to fabricate and are
the basic gates used in all IC digital logic families.
NAND Gate
The NAND gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs the operation
of the AND gate followed by the operation of the NOT gate.NAND gate is designed by
combining the AND and NOT gates. If the input of the NAND gate high, then the output of
the gate will be low. The symbol and truth table of the NAND gate with two inputs is shown
below Fig.1.

Fig:1. Truth table and symbol of NAND Gate

In the transistor NAND gate as shown in Fig.2, when A=0V and B=0V or when A=0V and
B=+5V or when A=+5V and B=+0V, both or either the transistors T1 and T2 are OFF. Hence,
the output voltage OUT= Vce(sat) =5V. When both A and B are equal to +5V, both the
transistors T1 and T2 will be ON. Hence no voltage drop occurs across it. Hence output
voltage, OUT=0V. The truth table for the above gate circuits is as shown below.
Table: 1 Truth table NAND
Inputs Outputs
A B OUT
0V 0V 5V
0V 5V 5V
5V 0V 5V
5V 5V 0V

14
Fundamentals of Digital Electronics (BE03003031)

Fig:2. Two input transistor NAND Gate

NOR Gate
The NOR gate is a digital logic gate with n inputs and one output, that performs the operation
of the OR gate followed by the NOT gate. NOR gate is designed by combining the OR and
NOT gate. When any one of the i/ps of the NOR gate is true, then the output of the NOR gate
will be false. The symbol and truth table of the NOR gate with truth table is shown below Fig.4.

Fig 3:. Truth table and symbol of NOR Gate

In the transistor NOR gate as shown in Fig.5, when A=+5V and B=+5V or when A=0V and
B=+5V or when A=+5V and B=+0V, both or either the transistors T1 and T2 are ON. Hence,
the output voltage OUT= Vce =0V. When both A and B are equal to 0V, both the transistors
T1 and T2 will be OFF. Hence output voltage, OUT= Vce(sat) =5V. The truth table for the
above gate circuits is as shown below.

Table: 2 Truth table NOR

Inputs Outputs
A B OUT
0V 0V 5V
0V 5V 0V
5V 0V 0V
5V 5V 0V

15
Fundamentals of Digital Electronics (BE03003031)

Fig:4. Two input transistor NOR Gate

PIN DIAGRAM OF NAND & NOR GATES ICs:

NOR Gate IC Pin Diagram NAND Gate IC Pin Diagram

16
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

17
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

18
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

NAND GATE
Input A Input B I/P A I/P B Output O/P
(Logic) (Logic) Volt(V) Volt(V) A.B(Logic) Volt(V)
0(L) 0(L) 1(H)
0(L) 1(H) 1(H)
1(H) 0(L) 1(H)
1(H) 1(H) 0(L)

NOR GATE
Input A Input B I/P A I/P B Output O/P
(Logic) (Logic) Volt(V) Volt(V) A.B(Logic) Volt(V)
0(L) 0(L) 1(H)
0(L) 1(H) 0(L)
1(H) 0(L) 0(L)
1(H) 1(H) 0(L)

19
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

20
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 3
Date:

AIM: To study & implement the EX-OR & EX-NOR gates.

Objectives: -
1. To understand the logic operation of EX-OR & EX-NOR Gates.
2. To verify the truth tables of EX-OR & EX-NOR using breadboard and/or Digital
Lab kits.
Theory

EX-OR Gate
An XOR gate (sometimes referred to by its extended name, Exclusive OR gate) is a digital
logic gate with two or more inputs and one output that performs exclusive disjunction. The
output of an XOR gate is true only when exactly one of its inputs is true. If both of an XOR
gate's inputs are false, or if both of its inputs are true, then the output of the XOR gate is false.
If an XOR gate has more than two inputs, then its behavior depends on its implementation.
In the vast majority of cases, an XOR gate will output true if an odd number of its inputs
is true. However, it's important to note that this behavior differs from the strict definition of
exclusive or, which insists that exactly one input must be true for the output to be true.
Symbol: Each of the symbols below can be used to represent an XOR gate. There are multiple
international standards defined, and one may preferred over the other in your region of the
world.

There is a way to represent the Exclusive-OR function in terms of OR and AND, AB’ + A’B.

21
Fundamentals of Digital Electronics (BE03003031)

Fig:1 EX-OR Gate using AOI logic.

Fig:2. EX-OR Gate using NAND logic. Fig:3. EX-OR Gate using NOR logic.

Fig.4. Truth table and symbol of EX-OR Gate

Here X, Y are the inputs and Z is the output of two input Ex-OR gate. The truth table of Ex-
OR gate is same as that of OR gate for first three rows. The only modification is in the fourth
row. That means, the output (Z) is zero instead of one, when both the inputs are one, since
the inputs having even number of ones. So, when both the inputs are same, then output of Ex-
OR gate is zero. When both the inputs are different, then output of Ex-OR gate is one.
EX-NOR Gate

XNOR gate is a special type of gate. It can be used in the half adder, full adder and subtractor.
The exclusive-NOR gate is abbreviated as EX-NOR gate or sometime as X-NOR gate. It has
n input (n >= 2) and one output. So, when both the inputs are same, then output of Ex-NOR
gate is one. When both the inputs are same, then output of Ex-NOR gate is zero.

22
Fundamentals of Digital Electronics (BE03003031)

Fig.4. Truth table and symbol of EX-NOR Gate.

Fig:5. EX-NOR Gate using NOR logic. Fig:6. EX-NOR Gate using NAND logic.

23
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

24
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

25
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

EX-OR GATE
Input A Input B I/P A I/P B Output O/P
(Logic) (Logic) Volt(V) Volt(V) A.B(Logic) Volt(V)
0(L) 0(L) 0(L)
0(L) 1(H) 1(H)
1(H) 0(L) 1(H)
1(H) 1(H) 0(L)

EX-NOR GATE
Input A Input B I/P A I/P B Output O/P
(Logic) (Logic) Volt(V) Volt(V) A.B(Logic) Volt(V)
0(L) 0(L) 1(H)
0(L) 1(H) 0(L)
1(H) 0(L) 0(L)
1(H) 1(H) 1(H)

26
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

27
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 4
Date:

AIM: To Implement of Boolean Logic Functions using AOI and

Universal logic.
Objectives: -
• To design Boolean Logic functions using AOI and Universal logic.
Theory:

De Morgan has suggested two theorems which are extremely useful in Boolean Algebra.
The two theorems are discussed below.
Theorem 1

• The left-hand side (LHS) of this theorem represents a NAND gate with inputs A and B,
whereas the right-hand side (RHS) of the theorem represents an OR gate with inverted
inputs.
• This OR gate is called as Bubbled OR.

Fig.1. Truth table and circuit diagram of De Morgan's theorem

28
Fundamentals of Digital Electronics (BE03003031)

Theorem 2

• The LHS of this theorem represents a NOR gate with inputs A and B, whereas the RHS
represents an AND gate with inverted inputs.
• This AND gate is called as Bubbled AND.

Fig.2. Truth table and circuit diagram of De Morgan's theorem

Boolean Function implementation using AOI Logic:
Boolean algebra deals with binary variables and logic operation. A Boolean Function is
described by an algebraic expression called Boolean expression which consists of binary
variables, the constants 0 and 1, and the logic operation symbols. Consider the following
example.

Here the left side of the equation represents the output Y. So we can state equation

29
Fundamentals of Digital Electronics (BE03003031)

no. 1

Truth Table Formation

A truth table represents a table having all combinations of inputs and their corresponding
result.
It is possible to convert the switching equation into a truth table. For example, consider the
following switching equation.

The output will be high (1) if A = 1 or BC = 1 or both are 1. The truth table for this equation
is shown by Table (a). The number of rows in the truth table is 2n where n is the number of
input variables (n=3 for the given equation). Hence there are 23 = 8 possible input
combination of inputs.

Implementation of Boolean Logic function

F=(A.B.C) +A(B'+C')

Fig.3. Boolean logic diagram using AOI Logic

30
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

31
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

32
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

33
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

34
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 5
Date:

AIM: To study & implement Half Adder and Full Adder using AOI and
Universal logic.
Objectives: -
1. To design Half Adder and Full Adder using AOI and Universal logic.
2. To implement Half and Full Adder using Basic Gate ICs.
3. To implement and verify the truth tables of Half and Full Adder using
breadboard and/or Digital Lab kits.
Theory:
Combinational circuit is a circuit in which we combine the different gates in the circuit, for
example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of
combinational circuits are following −
• The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
• The combinational circuit do not use any memory. The previous state of input does not
have any effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs.

Block diagram

Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder
circuit is designed to add two single bit binary number A and B. It is the basic building block
for addition of two single bit numbers. This circuit has two outputs carry and sum.

Fig.1. Half Adder using AOI Logic & Truth Table.

35
Fundamentals of Digital Electronics (BE03003031)

NAND LOGIC:

S=AB'+A'B=AB'+AA'+BB'+A'B
=A(A'+B')+B(A'+B')
=A.(AB)'+B.(AB)'
= ((A.(AB)')'.(B.(AB)')')'

C=AB=((AB)')'

Fig.2. Half Adder using NAND and NOR Logic.

NOR LOGIC:
S=AB'+A'B=AB'+AA'+BB'+A'B
=A(A'+B')+B(A'+B')
=(A+B)(A'+B')
= ((A+B)'+(A'+B')')'
C=AB=(A'+B')'

Full Adder:
A full adder is an arithmatic circuit that adds two bits and a carry and outputs a sum bit and
a carry bit. When we want to add two binary numbers, each having two or more bits, the
LSBs, can be added by using a half adder. The carry resulted from the addition of the LSBs
is carried over to the next significant column and added to the two bits in that column. So,
in the second and higher columns, the two data bits of that column and the carry bit generated
from the addition in the previous column need to be added. The full adder adds the bits A
and B and carry from the previous column called the carry-in Cin and outputs the sum bit S
and the carry bit called carry -out Cout. The block diagram and truth table of a full adder are
shown below.

36
Fundamentals of Digital Electronics (BE03003031)

Block diagram Truth Table Circuit Diagram

Fig.3. Full Adder Block diagram, truth table and AOI Logic.
The Boolean expression for a full adder is as follows.
Logical Expression for SUM:
= A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN
= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B)
= (1,2,4,7)
Logical Expression for C-OUT:
= A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN
= A B + B C-IN + A C-IN
= (3,5,6,7)
Another form in which C-OUT can be implemented:
= A B + A C-IN + B C-IN (A + A’)
= A B C-IN + A B + A C-IN + A’ B C-IN
= A B (1 +C-IN) + A C-IN + A’ B C-IN
= A B + A C-IN + A’ B C-IN
= A B + A C-IN (B + B’) + A’ B C-IN
= A B C-IN + A B + A B’ C-IN + A’ B C-IN
= A B (C-IN + 1) + A B’ C-IN + A’ B C-IN
= A B + A B’ C-IN + A’ B C-IN
= AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)

Fig.4. Full Adder using NAND Gate.

37
Fundamentals of Digital Electronics (BE03003031)

Fig.6. Full Adder using NOR Gate.

38
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

39
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

40
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:
HALF ADDER:

FULL ADDER:

41
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

42
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 6
Date:

AIM: To study & implement Half Subtractor and Full Subtractor using
AOI and Universal logic.
Objectives:-
1. To design Half Subtractor and Full Subtractor using AOI and Universal
logic.
2. To implement Half and Full Subtractor using Basic Gate ICs.
3. To implement and verify the truth tables of Half and Full Subtractor
using breadboard and/or Digital Lab kits.
Theory:
Half Subtractor
Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It
produces the difference between the two binary bits at the input and also produces an output (Borrow)
to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called
as Subtrahend bit.

Fig.1. Half Subtrctor truth table and logic diagram using AOI logic.

Fig.2. Half Subtractor using NAND Logic.

43
Fundamentals of Digital Electronics (BE03003031)

Fig.3. Half Subtractor using NOR Logic.

Full Subtractor
A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, taking into account borrow of the previous adjacent lower
minuend bit. This circuit has three inputs and two outputs. The three inputs A, B and Bin,
denote the minuend, subtrahend, and previous borrow, respectively. The two outputs, D and
Bout represent the difference and output borrow, respectively.

Fig:4. Full Subtractor using AOI Logic.

44
Fundamentals of Digital Electronics (BE03003031)

Table:1. Truth table of Full Subtractor

Fig:5. Logical expression of Full Subtractor.

Logical expression for difference –

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin
Logical expression for borrow –
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
= A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
= A’Bin + A’B + BBin
OR
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= Bin(AB + A’B’) + A’B(Bin + Bin’)
= Bin( A XNOR B) + A’B
= Bin (A XOR B)’ + A’B

45
Fundamentals of Digital Electronics (BE03003031)

Fig:6. Full Subtractor using NAND Logic.

Fig:7. Full Subtractor using NOR Logic.

46
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

47
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

48
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:
HALF SUBTRACTOR:

FULL SUBTRACTOR:

49
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

50
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 7
Date:

AIM: To study & implement Gray to Binary & Binary to Gray code
conversion using Gate ICs.

Objectives: -
1. To design Gray to Binary & Binary to Gray code conversion using AOI
and Universal logic.
2. To implement Gray to Binary & Binary to Gray code conversion using
Basic Gate ICs.
3. To verify the truth tables Gray to Binary & Binary to Gray code
conversion using breadboard and/or Digital Lab kits.
Theory:
This conversion can be done by applying following rules:

Binary to Gray conversion :

1 The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given
binary code.
2 Other bits of the output gray code can be obtained by XORing binary code bit at that index
and previous index.
Example of Binary to Gray Code Converter
Let assume the Binary code digits be bo, b1, b2, b3 whereas the particular Gray Code can be
attained based on the following concept.

From the above operation, finally we can get the gray values like g3 = b3, g2 = b3
XOR b2, g1= b2 XOR b1, g0 = b1 XOR b0.

For example, take the binary value b3, b2, b1, b0 = 1101 and find the gray code g3, g2, g1, g0
based on the above concept.

51
Fundamentals of Digital Electronics (BE03003031)

g3=b3=1
g2 = b3 XOR b2 = 1 XOR 1 =0
g1= b2 XOR b1= 1 XOR 0 = 1
g0= b1 XOR b0= 0 XOR 1 = 1

Table:1 Truth Table of Binary To Gray Code

Fig:1. Binary to Gray Code Conversion Logic diagram.

52
Fundamentals of Digital Electronics (BE03003031)

Gray to binary conversion :

1 The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the
given binary number.
2 Other bits of the output binary code can be obtained by checking gray code bit at that
index. If current gray code bit is 0, then copy previous binary code bit, else copy invert
of previous binary code bit.

Example of Gray to Binary Code Converter

Let assume the Gray Code digits g3, g2, g1, g0 whereas the particular Binary code digits are
bo, b1, b2, b3 can be attained based on the following concept.

From the above operation, finally we can get the binary values like b3 = g3, b2 =
b3 XOR g2, b1= b2 XOR g1, b0 = b1 XOR g0.

For example, take the gray value g3, g2, g1, g0 = 0011 and find the binary code b3, b2, b1, b0
based on the above concept

b3=g3=0
b2 = b3 XOR g2 = 0 XOR 0 =0
b1= b2 XOR g1= 0 XOR 1 = 1
b0= b1 XOR g0= 1 XOR 1 = 0
The final binary code for the value of gray 0011 is 0010

53
Fundamentals of Digital Electronics (BE03003031)

Table:2 Truth Table of Gray to Binary Code.

Fig:2. Gray to Binary Code Conversion Logic diagram.

54
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

55
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

56
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

57
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

58
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 8
Date:
AIM: To study & implement 1-bit & 2-bit Magnitude Comparator
using Gate ICs.
Objectives: -
1. To design 1-bit & 2-bit Magnitude Comparator AOI and Universal
logic.
2. To implement 1-bit & 2-bit Magnitude Comparator using Basic Gate
ICs.
3. To verify the truth tables of 1-bit & 2-bit Magnitude Comparator using
breadboard and/or Digital Lab kits.
Theory:

A magnitude digital Comparator is a combinational circuit that compares two digital or

binary numbers in order to find out whether one binary number is equal, less than or greater
than the other binary number. We logically design a circuit for which we will have two inputs
one for A and other for B and have three output terminals, one for A > B condition, one for A
= B condition and one for A < B condition.

1-Bit Magnitude Comparator:

A comparator used to compare two bits is called a single bit comparator. It consists of two
inputs each for two single bit numbers and three outputs to generate less than, equal to and
greater than between two binary numbers.
The truth table for a 1-bit comparator is given below:

Fig:1. 1-Bit Magnitude Comparator.

From the above truth table logical expressions for each output can be expressed as follows:
A>B: AB'
A<B: A'B
A=B: A'B' + AB

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Fundamentals of Digital Electronics (BE03003031)

From the above expressions we can derive the following formula:

By using these Boolean expressions, we can implement a logic circuit for this comparator
as given below:

Fig:2 Logic diagram of 1-Bit Magnitude Comparator.

• Firstly, the circuit does not distinguish between either two “0” or two “1”‘s as an
output A = B is produced when they are both equal, either A = B = “0” or A = B = “1”.
Secondly, the output condition for A = B resembles that of a commonly available logic
gate, the Exclusive-NOR or Ex-NOR function (equivalence) on each of the n-
bits giving: Q = A ⊕ B
• Digital comparators actually use Exclusive-NOR gates within their design for
comparing their respective pairs of bits. When we are comparing two binary or BCD
values or variables against each other, we are comparing the “magnitude” of these
values, a logic “0” against a logic “1” which is where the term Magnitude
Comparator comes from.
• As well as comparing individual bits, we can design larger bit comparators by cascading
together n of these and produce a n-bit comparator just as we did for the n-bit adder in
the previous tutorial. Multi-bit comparators can be constructed to compare whole binary
or BCD words to produce an output if one word is larger, equal to or less than the other.

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Fundamentals of Digital Electronics (BE03003031)

2-Bit Magnitude Comparator:

A comparator used to compare two binary numbers each of two bits is called a 2-bit
Magnitude comparator. It consists of four inputs and three outputs to generate less than, equal
to and greater than between two binary numbers.

The truth table for a 2-bit comparator is given below:

From the above truth table K-map for each output can be drawn as follows:

Fig:3 K-Map for 2-bit comparator.

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Fundamentals of Digital Electronics (BE03003031)

From the above K-maps logical expressions for each output can be expressed as follows:
A>B:A1B1’ + A0A1B1’B0’ + A1'B1'A0B0’
A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A=B = .
A<B:A1’B1 + A1A0’B1B0 + A1’A0’B0B1'
By using these Boolean expressions, we can implement a logic circuit for this comparator
as given below:

Fig:4. Logic diagram of 2-Bit Magnitude Comparator.

62
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

63
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

64
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

65
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

66
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 9
Date:

AIM: To study & implement Encoder and Decoder using Gate ICs.

Objectives: -
1. To design Encoder and Decoder using AOI and Universal logic.
2. To implement Encoder and Decoder using Basic Gate ICs.
Theory:

An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to
the input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It
is optional to represent the enable signal in encoders.

4 to 2 Line Encoder

Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the following figure.

Fig.1. 4 to 2 line Encoder.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code
at the output. The Truth table of 4 to 2 encoder is shown below.

FA1 = y2+y3
FA0 = y1+y3
We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 line encoder is shown in the following figure.

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Fundamentals of Digital Electronics (BE03003031)

Fig:2 4 to 2 line encoder

The above circuit diagram contains two OR gates. These OR gates encode the four inputs
with two bits.

Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to
binary encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder
is shown in the following figure.

Fig.3. Octal to Binary Encoder.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary
code. The Truth table of octal to binary encoder is shown below.

From Truth table, we can write the Boolean functions for each output as,
FA2 = Y4+Y5+Y6+Y7
FA1 = Y2+Y3+Y6+Y7
FA0 = Y1+Y3+Y5+Y7

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Fundamentals of Digital Electronics (BE03003031)

We can implement the above Boolean functions by using four input OR gates. The circuit
diagram of octal to binary encoder is shown in the following figure.

Fig.4. Octal to Binary Encoder.

The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight
inputs with three bits.

Drawbacks of Encoder
Following are the drawbacks of normal encoder.
• There is an ambiguity, when all outputs of encoder are equal to zero. Because, it could
be the code corresponding to the inputs, when only least significant input is one or
when all inputs are zero.
• If more than one input is active High, then the encoder produces an output, which may
not be the correct code. For example, if both Y3 and Y6 are ‘1’, then the encoder
produces 111 at the output. This is neither equivalent code corresponding to Y3, when
it is ‘1’ nor the equivalent code corresponding to Y6, when it is ‘1’.
So, to overcome these difficulties, we should assign priorities to each input of encoder. Then,
the output of encoder will be the (binary) code corresponding to the active High input(s),
which has higher priority. This encoder is called as priority encoder.

Priority Encoder
A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. Here, the
input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case,
even if more than one input is ‘1’ at the same time, the output will be the (binary) code
corresponding to the input, which is having higher priority.
We considered one more output, V in order to know, whether the code available at outputs is
valid or not.
• If at least one input of the encoder is ‘1’, then the code available at outputs is a valid
one. In this case, the output, V will be equal to 1.
• If all the inputs of encoder are ‘0’, then the code available at outputs is not a valid one.
In this case, the output, V will be equal to 0.

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Fundamentals of Digital Electronics (BE03003031)

The Truth table of 4 to 2 priority encoder is shown below.

Use 4 variable K-maps for getting simplified expressions for each output.

The simplified Boolean functions are,

FA1= Y3+Y2
FA0=Y3+Y1Y2'
Similarly, we will get the Boolean function of output, V as,
FV=Y3+Y2+Y1+Y0
We can implement the above Boolean functions using logic gates. The circuit diagram of 4
to 2 priority encoder is shown in the following figure.

Fig.5. 4 to 2 priority encoder.

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Fundamentals of Digital Electronics (BE03003031)

The above circuit diagram contains two 2-input OR gates, one 4-input OR gate, one 2input
AND gate & an inverter. Here AND gate & inverter combination are used for producing a
valid code at the outputs, even when multiple inputs are equal to ‘1’ at the same time. Hence,
this circuit encodes the four inputs with two bits based on the priority assigned to each input.

Digital Encoder Applications

Keyboard Encoder
Priority encoders can be used to reduce the number of wires needed in a particular circuits or
application that have multiple inputs. For example, assume that a microcomputer needs to read
the 104 keys of a standard QWERTY keyboard where only one key would be pressed either
“HIGH” or “LOW” at any one time.
One way would be to connect all 104 wires from the individual keys on the keyboard directly
to the computers input but this would be impractical for a small home PC. Another alternative
and better way would be to interface the keyboard to the PC using a priority encoder.
The 104 individual buttons or keys could be encoded into a standard ASCII code of only 7-bits
(0 to 127 decimal) to represent each key or character of the keyboard and then input as a much
smaller 7-bit B.C.D code directly to the computer. Keypad encoders such as the 74C923 20-
key encoder are available to do just that.

Positional Encoders
Another more common application is in magnetic positional control as used on ships navigation
or for robotic arm positioning etc. Here for example, the angular or rotary position of a compass
is converted into a digital code by a 74LS148 8-to-3 line priority encoder and input to the
systems computer to provide navigational data and an example of a simple 8 position to 3-bit
output compass encoder is shown below. Magnets and reed switches could be used at each
compass point to indicate the needles angular position.

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Fundamentals of Digital Electronics (BE03003031)

Decoders:

The name “Decoder” means to translate or decode coded information from one format into
another, so a binary decoder transforms “n” binary input signals into an equivalent code using
2n outputs.
Binary Decoders are another type of digital logic device that has inputs of 2-bit, 3-bit or 4-bit
codes depending upon the number of data input lines, so a decoder that has a set of two or more
bits will be defined as having an n-bit code, and therefore it will be possible to represent
2n possible values. Thus, a decoder generally decodes a binary value into a non-binary one by
setting exactly one of its n outputs to logic “1”.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean number)
it activates one and only one of its 2n outputs based on that input with all other outputs
deactivated.

So for example, an inverter ( NOT-gate ) can be classed as a 1-to-2 binary decoder as 1-input
and 2-outputs (21) is possible because with an input A it can produce two outputs A and A (not-
A) as shown.
Then we can say that a standard combinational logic decoder is an n-to-m decoder,
where m ≤ 2n, and whose output, Q is dependent only on its present input states. In other words,
a binary decoder looks at its current inputs, determines which binary code or binary number is
present at its inputs and selects the appropriate output that corresponds to that binary input.
A Binary Decoder converts coded inputs into coded outputs, where the input and output codes
are different and decoders are available to “decode” either a Binary or BCD (8421 code) input
pattern to typically a Decimal output code. Commonly available BCD-to-Decimal decoders
include the TTL 7442 or the CMOS 4028. Generally a decoders output code normally has more
bits than its input code and practical “binary decoder” circuits include, 2-to-4, 3-to-8 and 4-to-
16 line configurations.
An example of a 2-to-4 line decoder along with its truth table is given as:

A 2-to-4 Binary Decoders

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Fundamentals of Digital Electronics (BE03003031)

This simple example above of a 2-to-4 line binary decoder consists of an array of
four AND gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs, hence
the description of 2-to-4 binary decoder. Each output represents one of the miniterms of the 2
input variables, (each output = a miniterm).
The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic
level “1” while the remaining outputs are held “LOW” at logic “0” so only one output can be
active (HIGH) at any one time. Therefore, whichever output line is “HIGH” identifies the
binary code present at the input, in other words it “de-codes” the binary input.
Some binary decoders have an additional input pin labelled “Enable” that controls the outputs
from the device. This extra input allows the decoders outputs to be turned “ON” or “OFF” as
required. These types of binary decoders are commonly used as “memory address decoders”
in microprocessor memory applications.

74LS138 Binary Decoder

We can say that a binary decoder is a demultiplexer with an additional data line that is used to
enable the decoder. An alternative way of looking at the decoder circuit is to regard
inputs A, B and C as address signals. Each combination of A, B or C defines a unique memory
address.
We have seen that a 2-to-4 line binary decoder (TTL 74155) can be used for decoding any 2-
bit binary code to provide four outputs, one for each possible input combination. However,
sometimes it is required to have a Binary Decoder with a number of outputs greater than is
available, so by adding more inputs, the decoder can potentially provide 2n more outputs.
So for example, a decoder with 3 binary inputs ( n = 3 ), would produce a 3-to-8 line decoder
(TTL 74138) and 4 inputs ( n = 4 ) would produce a 4-to-16 line decoder (TTL 74154) and so
on. But a decoder can also have less than 2n outputs such as the BCD to seven-segment decoder
(TTL 7447) which has 4 inputs and only 7 active outputs to drive a display rather than the full
16 (24) outputs as you would expect.
Here a much larger 4 (3 data plus 1 enable) to 16 line binary decoder has been implemented
using two smaller 3-to-8 decoders.

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Fundamentals of Digital Electronics (BE03003031)

A 4-to-16 Binary Decoder Configuration

Inputs A, B, C are used to select which output on either decoder will be at logic “1” (HIGH)
and input D is used with the enable input to select which encoder either the first or second will
output the “1”.
However, there is a limit to the number of inputs that can be used for one particular decoder,
because as n increases, the number of AND gates required to produce an output also becomes
larger resulting in the fan-out of the gates used to drive them becoming large.
This type of active-“HIGH” decoder can be implemented using just Inverters, ( NOT Gates )
and AND gates. It is convenient to use an AND gate as the basic decoding element for the
output because it produces a “HIGH” or logic “1” output only when all of its inputs are logic
“1”.
But some binary decoders are constructed using NAND gates instead of AND gates for their
decoded output, since NAND gates are cheaper to produce than AND’s as they require fewer
transistors to implement within their design.
The use of NAND gates as the decoding element, results in an active-“LOW” output while the
rest will be “HIGH”. As a NAND gate produces the AND operation with an inverted output,
the NAND decoder looks like this with its inverted truth table.

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Fundamentals of Digital Electronics (BE03003031)

Memory Address Decoding

The binary decoder requires only 3 address lines, (A0 to A2) to select each one of the 8 chips
(the lower part of the address), while the remaining 8 address lines (A3 to A10) select the correct
memory location on that chip (the upper part of the address).
Having selected a memory location using the address bus, the information at the particular
internal memory location is sent to a common “Data Bus” for use by the microprocessor. This
is of course a simple example but the principals remain the same for all types of memory chips
or modules.
Binary Decoders are very useful devices for converting one digital format to another, such as
binary or BCD type data into decimal or octal etc and commonly available decoder IC’s are
the TTL 74LS138 3-to-8 line binary decoder or the 74ALS154 4-to-16 line decoder. They are
also very useful for interfacing to 7-segment displays such as the TTL 74LS47.

75
Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

76
Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

77
Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

78
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

79
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 10
Date:

AIM: To study & implement Multiplexer and Demultiplexer using Gate

ICs.
Objectives: -
1. To design Multiplexer and Demultiplexer using AOI and Universal
logic.
2. To implement Multiplexer and Demultiplexer using Basic Gate ICs.
3. To study working of the Multiplexer and Demultiplexer using breadboard.

Theory:
Multiplexing is the generic term used to describe the operation of sending one or more analogue
or digital signals over a common transmission line at different times or speeds and as such, the
device we use to do just that is called a Multiplexer.
The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed to
switch one of several input lines through to a single common output line by the application of
a control signal. Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to the output.
Multiplexers, or MUX’s, can be either digital circuits made from high speed logic gates used
to switch digital or binary data or they can be analogue types using transistors, MOSFET’s or
relays to switch one of the voltage or current inputs through to a single output.
The most basic type of multiplexer device is that of a one-way rotary switch as shown below.

Basic Multiplexing Switch

The rotary switch, also called a wafer switch as each layer of the switch is known as a wafer,
is a mechanical device whose input is selected by rotating a shaft. In other words, the rotary
switch is a manual switch that you can use to select individual data or signal lines simply by
turning its inputs “ON” or “OFF”. So how can we select each data input automatically using a
digital device.
In digital electronics, multiplexers are also known as data selectors because they can “select”
each input line, are constructed from individual Analogue Switches encased in a single IC
package as opposed to the “mechanical” type selectors such as normal conventional switches
and relays.

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Fundamentals of Digital Electronics (BE03003031)

They are used as one method of reducing the number of logic gates required in a circuit design
or when a single data line or data bus is required to carry two or more different digital signals.
For example, a single 8-channel multiplexer.
Generally, the selection of each input line in a multiplexer is controlled by an additional set of
inputs called control lines and according to the binary condition of these control inputs, either
“HIGH” or “LOW” the appropriate data input is connected directly to the output. Normally, a
multiplexer has an even number of 2n data input lines and a number of “control” inputs that
correspond with the number of data inputs.
Note that multiplexers are different in operation to Encoders. Encoders are able to switch an n-
bit input pattern to multiple output lines that represent the binary coded (BCD) output
equivalent of the active input.
We can build a simple 2-line to 1-line (2-to-1) multiplexer from basic logic NAND gates as
shown.

2-input Multiplexer Design:

The input A of this simple 2-1 line multiplexer circuit constructed from standard NAND gates
acts to control which input ( I0 or I1 ) gets passed to the output at Q.
From the truth table above, we can see that when the data select input, A is LOW at logic 0,
input I1 passes its data through the NAND gate multiplexer circuit to the output, while input
I0 is blocked. When the data select A is HIGH at logic 1, the reverse happens and now input
I0 passes data to the output Q while input I1 is blocked.
So by the application of either a logic “0” or a logic “1” at A we can select the appropriate
input, I0 or I1 with the circuit acting a bit like a single pole double throw (SPDT) switch.
As we only have one control line, (A) then we can only switch 21 inputs and in this simple
example, the 2-input multiplexer connects one of two 1-bit sources to a common output,
producing a 2-to-1-line multiplexer. We can confirm this in the following Boolean expression.
Q = A'.I0'.I1 + A'.I0.I1 + A.I0.I1' + A.I0.I1
and for our 2-input multiplexer circuit above, this can be simplified too:
Q = A'.I1 + A.I0

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Fundamentals of Digital Electronics (BE03003031)

We can increase the number of data inputs to be selected further simply by following the same
procedure and larger multiplexer circuits can be implemented using smaller 2-to-1 multiplexers
as their basic building blocks. So for a 4-input multiplexer we would therefore require two data
select lines as 4-inputs represents 22 data control lines give a circuit with four inputs,
I0, I1, I2, I3 and two data select lines A and B as shown.

4-to-1 Channel Multiplexer:

The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and data select
lines a, b is given as:
Q = a'b'A + ab'B + a'bC + abD
In this example at any one instant in time only ONE of the four analogue switches is closed,
connecting only one of the input lines A to D to the single output at Q. As to which switch is
closed depends upon the addressing input code on lines “a” and “b“.

So for this example to select input B to the output at Q, the binary input address would need to
be “a” = logic “1” and “b” = logic “0”. Thus we can show the selection of the data through the
multiplexer as a function of the data select bits as shown.

Multiplexer Input Line Selection

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Fundamentals of Digital Electronics (BE03003031)

Adding more control address lines, (n) will allow the multiplexer to control more inputs as it
can switch 2n inputs but each control line configuration will connect only ONE input to the
output.
Then the implementation of the Boolean expression above using individual logic gates would
require the use of seven individual gates consisting of AND, OR and NOT gates as shown.

4 Channel Multiplexer using Logic Gates:

The symbol used in logic diagrams to identify a multiplexer is as follows:

Multiplexer Symbol

Multiplexers are not limited to just switching a number of different input lines or channels to
one common single output. There are also types that can switch their inputs to multiple outputs
and have arrangements or 4-to-2, 8-to-3 or even 16-to-4 etc configurations and an example of
a simple Dual channel 4 input multiplexer (4-to-2) is given below:

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Fundamentals of Digital Electronics (BE03003031)

4-to-2 Channel Multiplexer

Here in this example the 4 input channels are switched to 2 individual output lines but larger
arrangements are also possible. This simple 4-to-2 configuration could be used for example, to
switch audio signals for stereo pre-amplifiers or mixers.

Implementation of Higher-order Multiplexers

Now, let us implement the following higher-order Multiplexers using lower-order
Multiplexers.

• 8x1 Multiplexer

8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer.
We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas,
8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since,
each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and one
output Y. The Truth table of 8x1 Multiplexer is shown below.

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering
the above Truth table. The block diagram of 8x1 Multiplexer is shown in the following
figure.

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Fundamentals of Digital Electronics (BE03003031)

The same selection lines, s & s are applied to both 4x1 Multiplexers. The data inputs of upper
1 0

4x1 Multiplexer are I to I and the data inputs of lower 4x1 Multiplexer are I to I . Therefore,
7 4 3 0

each 4x1 Multiplexer produces an output based on the values of selection lines, s & s .1 0

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s is applied to 2x1 Multiplexer.
2

• If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to I0 based
on the values of selection lines s1 & s0.
• If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to I4 based
on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs
as one 8x1 Multiplexer.
Demultiplexer
The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is the
exact opposite of the Multiplexer we saw in the previous tutorial.
The demultiplexer takes one single input data line and then switches it to any one of a number
of individual output lines one at a time. The demultiplexer converts a serial data signal at the
input to a parallel data at its output lines as shown below.

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Fundamentals of Digital Electronics (BE03003031)

1-to-4 Channel De-multiplexer

The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and data
select lines a, b is given as:
F = a'b'A + a'bB + ab'C + abD
The function of the Demultiplexer is to switch one common data input line to any one of the
4 output data lines A to D in our example above. As with the multiplexer the individual solid
state switches are selected by the binary input address code on the output select pins “a” and
“b” as shown.

Demultiplexer Output Line Selection:

As with the previous multiplexer circuit, adding more address line inputs it is possible to switch
more outputs giving a 1-to-2n data line outputs.
Some standard demultiplexer IC´s also have an additional “enable output” pin which disables
or prevents the input from being passed to the selected output. Also some have latches built
into their outputs to maintain the output logic level after the address inputs have been changed.
However, in standard decoder type circuits the address input will determine which single data
output will have the same value as the data input with all other data outputs having the value
of logic “0”.
The implementation of the Boolean expression above using individual logic gates would
require the use of six individual gates consisting of AND and NOT gates as shown.

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Fundamentals of Digital Electronics (BE03003031)

4 Channel Demultiplexer using Logic Gates

The symbol used in logic diagrams to identify a demultiplexer is as follows.

The Demultiplexer Symbol

standard Demultiplexer IC packages available are the TTL 74LS138 1 to 8-output

demultiplexer, the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-
to-16 output demultiplexer.
Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line
demultiplexer/decoder. Here the individual output positions are selected using a 4-bit binary
coded input. Like multiplexers, demultiplexers can also be cascaded together to form higher
order demultiplexers.
Unlike multiplexers which convert data from a single data line to multiple lines and
demultiplexers which convert multiple lines to a single data line, there are devices available
which convert data to and from multiple lines and in the next tutorial about combinational logic
devices, we will look at Encoders which convert multiple input lines into multiple output lines,
converting the data from one form to another.
Implementation of Higher-order De-Multiplexers
Now, let us implement the following higher-order De-Multiplexers using lower-order De-
Multiplexers.

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Fundamentals of Digital Electronics (BE03003031)

• 1x8 De-Multiplexer
1x8 De-Multiplexer
In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-
Multiplexer. We know that 1x4 De-Multiplexer has single input, two selection lines and four
outputs. Whereas, 1x8 De-Multiplexer has single input, three selection lines and eight outputs.
So, we require two 1x4 De-Multiplexers in second stage in order to get the final eight outputs.
Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first
stage so that the outputs of first stage will be the inputs of second stage. Input of this 1x2 De-
Multiplexer will be the overall input of 1x8 De-Multiplexer.
Let the 1x8 De-Multiplexer has one input I, three selection lines s , s & s and outputs Y to Y .
2 1 0 7 0

The Truth table of 1x8 De-Multiplexer is shown below.

We can implement 1x8 De-Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 1x8 De-Multiplexer is shown
in the following figure.

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Fundamentals of Digital Electronics (BE03003031)

he common selection lines, s & s are applied to both 1x4 De-Multiplexers. The outputs of
1 0

upper 1x4 De-Multiplexer are Y to Y and the outputs of lower 1x4 De-Multiplexer are Y to
7 4 3

Y.0

The other selection line, s is applied to 1x2 De-Multiplexer. If s is zero, then one of the four
2 2

outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of selection
lines s & s . Similarly, if s is one, then one of the four outputs of upper 1x4 DeMultiplexer
1 0 2

will be equal to input, I based on the values of selection lines s & s .

1 0

CIRCUIT DIAGRAM:

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Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

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Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

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Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign:

92
Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 11
Date:

AIM: To study about different Flip-Flops, their Excitation tables, and

implementation using Gate ICs.
Objectives: -
1. To study about different types of Flip-Flops and their excitation tables.
2. To implement flipflops or latches using NAND & NOR gate.
3. To study working of the Flipflops using breadboard and/or Digital Lab kits.
Theory:

The sequential circuit contains a set of inputs and output(s). The output(s) of sequential circuit
depends not only on the combination of present inputs but also on the previous output(s).
Previous output is nothing but the present state. Therefore, sequential circuits contain
combinational circuits along with memory (storage) elements. Some sequential circuits may
not contain combinational circuits, but only memory elements.

Types of Sequential Circuits

Following are the two types of sequential circuits −

• Asynchronous sequential circuits

• Synchronous sequential circuits

Asynchronous sequential circuits

If some or all the outputs of a sequential circuit do not change (affect) with respect to active
transition of clock signal, then that sequential circuit is called as Asynchronous sequential
circuit. That means, all the outputs of asynchronous sequential circuits do not change (affect)
at the same time. Therefore, most of the outputs of asynchronous sequential circuits are not
in synchronous with either only positive edges or only negative edges of clock signal.

Synchronous sequential circuits

If all the outputs of a sequential circuit change (affect) with respect to active transition of clock
signal, then that sequential circuit is called as Synchronous sequential circuit. That means,
all the outputs of synchronous sequential circuits change (affect) at the same time. Therefore,
the outputs of synchronous sequential circuits are in synchronous with either only positive
edges or only negative edges of clock signal.

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Fundamentals of Digital Electronics (BE03003031)

Clock Signal and Triggering

Clock signal
Clock signal is a periodic signal and its ON time and OFF time need not be the same. We can
represent the clock signal as a square wave, when both its ON time and OFF time are same.
This clock signal is shown in the following figure.

the above figure, square wave is considered as clock signal. This signal stays at logic High
(5V) for some time and stays at logic Low (0V) for equal amount of time. This pattern repeats
with some time period. In this case, the time period will be equal to either twice of ON time
or twice of OFF time.
We can represent the clock signal as train of pulses, when ON time and OFF time are not
same. This clock signal is shown in the following figure.

Types of Triggering
Following are the two possible types of triggering that are used in sequential circuits.

• Level triggering
• Edge triggering
Level triggering
There are two levels, namely logic High and logic Low in clock signal. Following are the
two types of level triggering.

• Positive level triggering

• Negative level triggering
If the sequential circuit is operated with the clock signal when it is in Logic High, then that
type of triggering is known as Positive level triggering. It is highlighted in below figure.

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Fundamentals of Digital Electronics (BE03003031)

If the sequential circuit is operated with the clock signal when it is in Logic Low, then that
type of triggering is known as Negative level triggering. It is highlighted in the following
figure.

Edge triggering
There are two types of transitions that occur in clock signal. That means, the clock signal
transitions either from Logic Low to Logic High or Logic High to Logic Low.
Following are the two types of edge triggering based on the transitions of clock signal.

• Positive edge triggering

• Negative edge triggering
If the sequential circuit is operated with the clock signal that is transitioning from Logic Low
to Logic High, then that type of triggering is known as Positive edge triggering. It is also
called as rising edge triggering. It is shown in the following figure.

If the sequential circuit is operated with the clock signal that is transitioning from Logic High
to Logic Low, then that type of triggering is known as Negative edge triggering. It is also
called as falling edge triggering. It is shown in the following figure.

There are two types of memory elements based on the type of triggering that is suitable to
operate it.

• Latches
• Flip-flops
Latches operate with enable signal, which is level sensitive. Whereas, flip-flops are edge
sensitive
Those are the basic building blocks of flip-flops. We can implement flip-flops in two methods.
In first method, cascade two latches in such a way that the first latch is enabled for every
positive clock pulse and second latch is enabled for every negative clock pulse. So that the
combination of these two latches become a flip-flop.

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Fundamentals of Digital Electronics (BE03003031)

In second method, we can directly implement the flip-flop, which is edge sensitive. In this
chapter, let us discuss the following flip-flops using second method.

• SR Flip-Flop
• D Flip-Flop
• JK Flip-Flop
• T Flip-Flop

SR Flip-Flop
SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, SR latch operates with enable signal. The circuit diagram of SR flip-flop is shown
in the following figure.

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The operation of SR flipflop
is similar to SR Latch. But, this flip-flop affects the outputs only when positive transition of
the clock signal is applied instead of active enable.
The following table shows the state table of SR flip-flop.

Here, Q(t) & Q(t + 1) are present state & next state respectively. So, SR flip-flop can be used
for one of these three functions such as Hold, Reset & Set based on the input conditions,
when positive transition of clock signal is applied. The following table shows
the characteristic table of SR flip-flop.

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Fundamentals of Digital Electronics (BE03003031)

By using three variable K-Map, we can get the simplified expression for next state, Q(t + 1).
The three variable K-Map for next state, Q(t + 1) is shown in the following figure.

The maximum possible groupings of adjacent ones are already shown in the figure.
Therefore, the simplified expression for next state Q(t + 1) is
Q(t + 1) = S+Q(t)R'

D Flip-Flop
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal.
The circuit diagram of D flip-flop is shown in the following figure.

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Fundamentals of Digital Electronics (BE03003031)

This circuit has single input D and two outputs Q(t) & Q(t)’. The operation of D flip-flop is
similar to D Latch. But, this flip-flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.
The following table shows the state table of D flip-flop.

Therefore, D flip-flop always Hold the information, which is available on data input, D of
earlier positive transition of clock signal. From the above state table, we can directly write the
next state equation as
Q(t + 1) = D
Next state of D flip-flop is always equal to data input, D for every positive transition of the
clock signal. Hence, D flip-flops can be used in registers, shift registers and some of the
counters.

JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions. The circuit diagram of JK flip-flop is shown in the
following figure.

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Fundamentals of Digital Electronics (BE03003031)

This circuit has two inputs J & K and two outputs Q(t) & Q(t)’. The operation of JK flip-flop
is similar to SR flip-flop. Here, we considered the inputs of SR flip-flop as S = J Q(t)’ and R
= KQ(t) in order to utilize the modified SR flip-flop for 4 combinations of inputs.
The following table shows the state table of JK flip-flop.

Here, Q(t) & Q(t + 1) are present state & next state respectively. So, JK flip-flop can be used
for one of these four functions such as Hold, Reset, Set & Complement of present state based
on the input conditions, when positive transition of clock signal is applied. The following table
shows the characteristic table of JK flip-flop.

By using three variable K-Map, we can get the simplified expression for next state, Q(t +
1). Three variable K-Map for next state, Q(t + 1) is shown in the following figure.

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Fundamentals of Digital Electronics (BE03003031)

The maximum possible groupings of adjacent ones are already shown in the figure. Therefore,
the simplified expression for next state Q(t+1) is,
Q(t+1) = Q(t)'J+Q(t)K'
T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same input
‘T’ to both inputs of JK flip-flop. It operates with only positive clock transitions or negative
clock transitions. The circuit diagram of T flip-flop is shown in the following figure.

This circuit has single input T and two outputs Q(t) & Q(t)’. The operation of T flip-flop is
same as that of JK flip-flop. Here, we considered the inputs of JK flip-flop as J = T and K =
T in order to utilize the modified JK flip-flop for 2 combinations of inputs. So, we eliminated
the other two combinations of J & K, for which those two values are complement to each other
in T flip-flop.
The following table shows the state table of T flip-flop.

Here, Q(t) & Q(t + 1) are present state & next state respectively. So, T flip-flop can be used
for one of these two functions such as Hold, & Complement of present state based on the

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Fundamentals of Digital Electronics (BE03003031)

input conditions, when positive transition of clock signal is applied. The following table
shows the characteristic table of T flip-flop.

From the above characteristic table, we can directly write the next state equation as,
Q(t+1) = Q(t)'T+Q(t)T'
The output of T flip-flop always toggles for every positive transition of the clock signal, when
input T remains at logic High (1). Hence, T flip-flop can be used in counters.

EXCITATION TABLE OF FLIP-FLOPS:

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Fundamentals of Digital Electronics (BE03003031)

CIRCUIT DIAGRAM:

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Fundamentals of Digital Electronics (BE03003031)

PROCEDURE:

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Fundamentals of Digital Electronics (BE03003031)

OBSERVATION TABLE:

104
Fundamentals of Digital Electronics (BE03003031)

Conclusion:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign

105
 Fundamentals of Digital Electronics (BE03003031)

PRACTICAL NO : 12
Date:

AIM: To study about design of Counters and shift register.

Objectives:-
1. To study about working of Counters and shift register.
2. To design types of Counters and Shift registers.
3. To study about Counters and shift register using Digital Lab kits.
Theory:
This sequential device loads the data present on its inputs and then moves or “shifts” it to its
output once every clock cycle, hence the name Shift Register.
A shift register basically consists of several single bit “D-Type Data Latches”, one for each
data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement
so that the output from one data latch becomes the input of the next latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the other from either
the left or the right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is
usually determined by the number of bits to be stored with the most common being 8-bits (one
byte) wide constructed from eight individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary numbers before
they are added together, or to convert the data from either a serial to parallel or parallel to serial
format. The individual data latches that make up a single shift register are all driven by a
common clock ( Clk ) signal making them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:
▪ Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time,
with the stored data being available at the output in parallel form.
▪ Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register,
one bit at a time in either a left or right direction under clock control.
▪ Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
▪ Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented
graphically as:

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Fundamentals of Digital Electronics (BE03003031)

Also, the directional movement of the data through a shift register can be either to the left, (left
shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting
within the same register thereby making it bidirectional. In this tutorial it is assumed that all
the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel
data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the
output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other
outputs still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has
returned LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output
of FFB and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic
“1” has now moved or been “shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and
so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to
logic level “0” because the input to FFA has remained constant at logic level “0”.

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The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in
the register. This data value can now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic “1” through the register
from left to right as follows.

Basic Data Movement Through A Shift Register

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the
register and will remain there provided clocking of the register has stopped. In practice the
input data to the register may consist of various combinations of logic “1” and “0”. Commonly
available SIPO IC’s include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow
straight through the register and out of the other end. Since there is only one output,
the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-
in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock
signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift
register.

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Fundamentals of Digital Electronics (BE03003031)

4-bit Serial-in to Serial-out Shift Register

This type of shift register converts parallel data, such as an 8-bit data word into serial format,
it can be used to multiplex many different input lines into a single serial DATA stream which
can be sent directly to a computer or transmitted over a communications line. Commonly
available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift
register also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input
pins PA to PD and then transferred together directly to their respective output pins QA to QD by
the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement
for parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three
connections, the parallel input (PI) which determines what enters the flip-flop, the parallel
output (PO) and the sequencing clock signal (Clk).
Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary
storage device or as a time delay device, with the amount of time delay being varied by the
frequency of the clock pulses. Also, in this type of register there are no interconnections
between the individual flip-flops since no serial shifting of the data is required.

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Fundamentals of Digital Electronics (BE03003031)

Universal Shift Register

Today, there are many high speed bi-directional “universal” type Shift Registers available
such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-
function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-
parallel, parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence their
name “Universal”.
These universal shift registers can perform any combination of parallel and serial input to
output operations but require additional inputs to specify desired function and to pre-load and
reset the device. A commonly used universal shift register is the TTL 74LS194 as shown below.

4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond
to operations that require some form of temporary memory storage or for the delay of
information such as the SISO or PIPO configuration modes or transfer data from one
point to another in either a serial or parallel format. Universal shift registers are frequently
used in arithmetic operations to shift data to the left or right for multiplication or division.

COUNTERS:

An ‘N’ bit binary counter consists of ‘N’ T flip-flops. If the counter counts from 0 to 2𝑁 − 1,
then it is called as binary up counter. Similarly, if the counter counts down from 2𝑁 − 1 to 0,
then it is called as binary down counter.
There are two types of counters based on the flip-flops that are connected in synchronous or
not.

• Asynchronous counters
• Synchronous counters

Asynchronous or ripple counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are
being used. But we can use the JK flip-flop also with J and K connected permanently to logic
1. External clock is applied to the clock input of flip-flop A and Q output is applied to the
A

clock input of the next flip-flop i.e. FF-B.

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Logical Diagram

Operation

S.N. Condition Operation

1 Initially let both the FFs be in the reset state QBQA = 00 initially

2 After 1st negative clock edge As soon as the first negative clock
edge is applied, FF-A will toggle
and QA will be equal to 1.
QA is connected to clock input of
FF-B. Since QA has changed from 0
to 1, it is treated as the positive
clock edge by FF-B. There is no
change in QB because FF-B is a
negative edge triggered FF.
QBQA = 01 after the first clock
pulse.

3 After 2nd negative clock edge On the arrival of second negative

clock edge, FF-A toggles again and
QA = 0.
The change in QA acts as a negative
clock edge for FF-B. So it will also
toggle, and QB will be 1.
QBQA = 10 after the second clock
pulse.

4 After 3rd negative clock edge On the arrival of 3rd negative clock
edge, FF-A toggles again and
QA become 1 from 0.
Since this is a positive going
change, FF-B does not respond to it
and remains inactive. So QB does

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Fundamentals of Digital Electronics (BE03003031)

not change and continues to be

equal to 1.
QBQA = 11 after the third clock
pulse.

5 After 4th negative clock edge On the arrival of 4th negative clock
edge, FF-A toggles again and
QA becomes 1 from 0.
This negative change in QA acts as
clock pulse for FF-B. Hence it
toggles to change QB from 1 to 0.
QBQA = 00 after the fourth clock
pulse.

Truth Table

Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a
counter is called as synchronous counter.
2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The
JB and KB inputs are connected to QA.

Logical Diagram

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Fundamentals of Digital Electronics (BE03003031)

Operation

S.N. Condition Operation

1 Initially let both the FFs be in the reset state QBQA = 00 initially.

2 After 1st negative clock edge As soon as the first negative clock
edge is applied, FF-A will toggle
and QA will change from 0 to 1.
But at the instant of application of
negative clock edge, QA , JB = KB =
0. Hence FF-B will not change its
state. So QB will remain 0.
QBQA = 01 after the first clock
pulse.

3 After 2nd negative clock edge On the arrival of second negative

clock edge, FF-A toggles again and
QA changes from 1 to 0.
But at this instant QA was 1. So JB =
KB= 1 and FF-B will toggle. Hence
QB changes from 0 to 1.
QBQA = 10 after the second clock
pulse.

4 After 3rd negative clock edge On application of the third falling

clock edge, FF-A will toggle from 0
to 1 but there is no change of state
for FF-B.
QBQA = 11 after the third clock
pulse.

5 After 4th negative clock edge On application of the next clock

pulse, QA will change from 1 to 0 as
QB will also change from 1 to 0.
QBQA = 00 after the fourth clock
pulse.

Classification of counters
Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows −

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Fundamentals of Digital Electronics (BE03003031)

• Up counters
• Down counters
• Up/Down counters

UP/DOWN Counter

Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode
control (M) input is also provided to select either up or down mode. A combinational circuit
is required to be designed and used between each pair of flip-flop in order to achieve the
up/down operation.

• Type of up/down counters

• UP/DOWN ripple counters
• UP/DOWN synchronous counter

UP/DOWN Ripple Counters

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops
or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to
every other FF is obtained from (Q = Q bar) output of the previous FF.
• UP counting mode (M=0) − The Q output of the preceding FF is connected to the
clock of the next stage if up counting is to be achieved. For this mode, the mode select
input M is at logic 0 (M=0).
• DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF
is connected to the next FF. This will operate the counter in the counting mode.

Example
3-bit binary up/down ripple counter.
• 3-bit − hence three FFs are required.
• UP/DOWN − So a mode control input is essential.
• For a ripple up counter, the Q output of preceding FF is connected to the clock input
of the next one.
• For a ripple up counter, the Q output of preceding FF is connected to the clock input
of the next one.
• For a ripple down counter, the Q bar output of preceding FF is connected to the clock
input of the next one.
• Let the selection of Q and Q bar output of the preceding FF be controlled by the mode
control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1,
DOWN counting. So connect Q bar to CLK.

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Block Diagram

Truth Table

Operation

S.N. Condition Operation

1 Case 1 − With M = 0 (Up counting mode) If M = 0 and M bar = 1, then the AND
gates 1 and 3 in fig. will be enabled
whereas the AND gates 2 and 4 will
be disabled.
Hence QA gets connected to the clock
input of FF-B and QB gets connected
to the clock input of FF-C.
These connections are same as those
for the normal up counter. Thus with
M = 0 the circuit work as an up
counter.

2 Case 2: With M = 1 (Down counting mode) If M = 1, then AND gates 2 and 4 in

fig. are enabled whereas the AND
gates 1 and 3 are disabled.
Hence QA bar gets connected to the
clock input of FF-B and QB bar gets
connected to the clock input of FF-C.

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These connections will produce a

down counter. Thus with M = 1 the
circuit works as a down counter.

Modulus Counter (MOD-N Counter)

The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-
8 counter. So in general, an n-bit ripple counter is called as modulo-N counter. Where, MOD
number = 2n.
Type of modulus
• 2-bit up or down (MOD-4)
• 3-bit up or down (MOD-8)
• 4-bit up or down (MOD-16)

Application of counters
• Frequency counters
• Digital clock
• Time measurement
• A to D converter
• Frequency divider circuits
• Digital triangular wave generator.

4-bit Ring Counter

The synchronous Ring Counter example above, is preset so that exactly one data bit in the
register is set to logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal
is firstly applied to all the flip-flops together in order to “RESET” their outputs to a logic “0”
level and then a “PRESET” pulse is applied to the input of the first flip-flop ( FFA ) before the
clock pulses are applied. This then places a single logic “1” value into the circuit of the ring
counter.
So on each successive clock pulse, the counter circulates the same data bit between the four
flip-flops over and over again around the “ring” every fourth clock cycle. But in order to cycle
the data correctly around the counter we must first “load” the counter with a suitable data
pattern as all logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring
counter invalid.

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This type of data movement is called “rotation”, and like the previous shift register, the effect
of the movement of the data bit from left to right through a ring counter can be presented
graphically as follows along with its timing diagram:

Rotational Movement of a Ring Counter

Since the ring counter example shown above has four distinct states, it is also known as a
“modulo-4” or “mod-4” counter with each flip-flop output having a frequency value equal to
one-fourth or a quarter (1/4) that of the main clock frequency.
The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or
sequences through before repeating itself and a ring counter can be made to output any modulo
number. A “mod-n” ring counter will require “n” number of flip-flops connected together to
circulate a single data bit providing “n” different output states.
For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would
require sixteen flip-flops. However, as in our example above, only four of the possible sixteen
states are used, making ring counters very inefficient in terms of their output state usage.

Johnson Ring Counter

The Johnson Ring Counter or “Twisted Ring Counters”, is another shift register with
feedback exactly the same as the standard Ring Counter above, except that this time the
inverted output Q of the last flip-flop is now connected back to the input D of the first flip-flop
as shown below.
The main advantage of this type of ring counter is that it only needs half the number of flip-
flops compared to the standard ring counter then its modulo number is halved. So a “n-stage”

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Johnson counter will circulate a single data bit giving sequence of 2n different states and can
therefore be considered as a “mod-2n counter”.

4-bit Johnson Ring Counter

This inversion of Q before it is fed back to input D causes the counter to “count” in a different
way. Instead of counting through a fixed set of patterns like the normal ring counter such as for
a 4-bit counter, “0001”(1), “0010”(2), “0100”(4), “1000”(8) and repeat, the Johnson counter
counts up and then down as the initial logic “1” passes through it to the right replacing the
preceding logic “0”.
A 4-bit Johnson ring counter passes blocks of four logic “0” and then four logic “1” thereby
producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit
pattern continually repeats. For example, “1000”, “1100”, “1110”, “1111”, “0111”, “0011”,
“0001”, “0000” and this is demonstrated in the following table below.

Truth Table for a 4-bit Johnson Ring Counter

As well as counting or rotating data around a continuous loop, ring counters can also be used
to detect or recognise various patterns or number values within a set of data. By connecting

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simple logic gates such as the AND or the OR gates to the outputs of the flip-flops the circuit
can be made to detect a set number or value.
Standard 2, 3 or 4-stage Johnson Ring Counters can also be used to divide the frequency of
the clock signal by varying their feedback connections and divide-by-3 or divide-by-5 outputs
are also available.
For example, a 3-stage Johnson Ring Counter could be used as a 3-phase, 120 degree phase
shift square wave generator by connecting to the data outputs at A, B and NOT-B.
The standard 5-stage Johnson counter such as the commonly available CD4017 is generally
used as a synchronous decade counter/divider circuit.

PROCEDURE:

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Conclusion:

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Suggested References:

Reference Books:
• A. Anand Kumar, '' Fundamentals of Digital Electronics'', PHI Learning Publications.
• M. Morris Mano, " Digital Logic and Computer Design", Pearson Education India.
• R. P. Jain, "Modern Digital Electronics", Tata McGraw-Hill Education.
• Anil K. Maini, "Digital Electronics: Principles and Integrated Circuits", Wiley.
• Malvino& Leach, "Digital Principles and Applications", McGraw-Hill Education.
Reference Websites:
• https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm
• https://www.electronics-tutorials.ws/logic/logic_4.html
• https://www.javatpoint.com/logic-gates
• http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/index.html
References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total

Marks

Faculty Sign

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Fundamentals of Digital Electronics (BE03003031)

Bio-Medical Engineering

GTU course code: BE03003031

Lab Manual

prepared by

Prof. Priyank K. Shah

Assistant Professor

Biomedical Engineering,

Government Engineering College, Sector 28, Gandhinagar

Branch Coordinator

Dr. Mitul B. Patel

Associate Professor

Biomedical Engineering,

L. D. College of Engineering, Ahmedabad.

Committee Chairman

Dr. N M Bhatt

Professor of Mechanical Engineering

L. E. College, Morbi

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