APB

SOC OVERVIEW

In the mid-1990s, ASIC technology evolved from a chip-set philosophy to an embedded-

cores based system-on-a-chip (SoC) concept. In simple terms, we define an SoC as an IC,
designed by stitching together multiple stand-alone VLSI designs to provide full
functionality for an applications.

System on chip (SOC), is an integrated circuit where all the functional elements such as
dedicated hardware, processor, memory, I/O, and peripherals are embedded onto a single
platform chip to meet the product design requirements.

Figure 1. A Basic SOC Model

Introduction to Advanced Microcontroller Bus Architecture

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APB-Advanced peripheral Bus Advanced Microcontroller Bus Architecture (AMBA) is a
collection of on-chip bus protocol specifications used by Arm processors as well as a wide
range of on-chip digital components such as memory interfaces, peripherals and debug
components. The specification is developed by Arm and is an open standard available to the
chip design industry.

Unlike most other bus protocols such as PCI, AMBA bus protocols are designed for on-chip
communications. To enable easier system integration inside chip designs, almost all the
AMBA specifications have the following characteristics:

● Synchronous operations:- use only clock rising edge for flip-flops, friendly to common
synthesis flow.
● No on-chip bi-directional signals:- avoiding the need for tri-state buffers.

The most common AMBA bus protocols used in microcontrollers include:

1. AHB (Advanced High-performance Bus) :- a lightweight pipelined bus protocol used

in the majority of the Arm Cortex-M processors.
2. APB (Advanced Peripheral Bus) :- a simple bus protocol for connecting general simple
peripherals with low data bandwidth requirements.
3. AXI (Advanced eXtensible Interface) :- a high-performance bus protocol for efficient,
highperformance processors including the Cortex-M7 processor, Cortex-R
processors and the majority of the Arm Cortex-A processors. The AXI protocol:
A. Provides multiple data channels running concurrently at high clock frequency.
B. Allows new transfers to be issued and take place even with previous transfers
still outstanding.
.

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APB (Advanced Peripheral Bus)

APB is a simple bus mainly targeted for peripherals connections. It was introduced as part
of the AMBA 2 specification, and the functionalities have been extended in AMBA 3 and
AMBA 4 to allow wait states, error responses. Most APB systems are 32-bit. Although the
bus protocol does not have a bus width limitation, the common practice for Arm-based
systems is to use a 32-bit peripheral bus.

Although it is possible to directly connect a peripheral to the AHB, separating peripheral

connections using APB has various advantages:-

1. Many system-on-chip designs contain large numbers of peripherals. If they are

connected to the AHB system bus, they could reduce the maximum frequency of the
system due to high signal fan out and complex address decoding logic. Grouping
peripheral connections in the APB can reduce the performance impact on the AHB.
2. A peripheral subsystem can run at a different clock frequency, or be powered down
without affecting AHB.
3. APB interfaces use a simpler bus protocol, which simplifies the peripheral designs as
well as reducing the verification effort.
4. Most peripherals designed for traditional processors can be connected to APB easily
as APB transfers are not pipelined.

An APB system operates with a clock signal called PCLK. This signal is common to bus
master (usually an AHB to APB Bridge), bus slaves and the bus infrastructure blocks. All
registers on the APB trigger at rising edges of PCLK. There is also an active-low reset signal
called PRESETn. When this signal is low, it resets the APB system immediately
(asynchronous reset). This allows a system to be reset even if the clock is stopped. Like the
reset signal in AHB (HRESETn), the PRESETn signal itself should be synchronized to PCLK
so that race conditions can be avoided.

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Operating States

Figure 2. State Diagram

The State machines operated through the following states:

1. IDLE:- This is the default state of the APB.

2. SETUP:- When a transfer is required the bus moves into the SETUP state, where the
appropriate select signal, PSELx, is asserted. The bus only remains in the SETUP state
for one clock cycle and always moves to the ACCESS state on the next rising edge of
the clock.
3. ACCESS:- The enable signal, PENABLE, is asserted in the ACCESS state. The address,
write, select, and write data signals must remain stable during the transition from the
SETUP to ACCESS state.
Exit from the ACCESS state is controlled by the PREADY signal from the slave:

● If PREADY is held LOW by the slave then the peripheral bus remains in the
ACCESS state.

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● If PREADY is driven HIGH by the slave then the ACCESS state is exited and the
bus returns to the IDLE state if no more transfers are required. Alternatively,
the bus moves directly to the SETUP state if another transfer follows.

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Signal Descriptions

Table 1. Signal description

Signal Source Description

PCLK Clock source Clock. The rising edge of PCLK times all transfers on the
APB

PRESETn System bus Reset. The APB reset signal is active LOW. This signal is
equivalent normally connected directly to the system bus reset signal

PADDR APB Bridge Address. This is the APB address bus. It can be up to 32 bits
wide and is driven by the peripheral bus bridge unit

PSELx APB Bridge Select. The APB bridge unit generates this signal to each
peripheral bus slave. It indicates that the slave device is
selected and that a data transfer is required. There is a
PSELx signal for each slave.

PENABLE APB Bridge Enable. This signal indicates the second and subsequent
cycles of an APB transfer

PWRITE APB Bridge Direction. This signal indicates an APB write access when
HIGH and an APB read access when LOW.

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 PWDATA APB Bridge Write data. This bus is driven by the peripheral bus bridge
unit during write cycles when PWRITE is HIGH. This bus can
be up to 32 bits wide

PREADY Slave Ready. The slave uses this signal to extend an APB transfer.
Interface

PRDATA Slave Read Data. The selected slave drives this bus during read
interface cycles when PWRITE is LOW. This bus can be up to 32-bits
wide.

APB Transfers

1. Write transfers

Two types of write transfer are described in this section:

● With no wait states

● With wait states.

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Figure 3. Write transfer with no wait states

Figure 4. Write transfer with wait states

Figure 5. Block Diagram for APB Master

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