SECTION A

1. Explain 2's complement method for subtraction.

To subtract signed binary numbers using the 2's complement method:

1. Take the 2's complement of the subtrahend (the number to be subtracted).

2. Add it to the minuend (the number from which subtraction is done).

3. Discard any carry out (if it occurs).

Example 1: Positive - Positive To subtract +3 (0011) from +5 (0101) in a 4-bit system:

 Take the 2's complement of +3: 0011 → 1101

 Add it to +5: 0101 + 1101 = 10000 (ignore carry, result is 1000 = -8).
Example 2: Positive - Negative To subtract -3 (1101) from +5 (0101):

 Take the 2's complement of -3: 1101 → 0011

 Add it to +5: 0101 + 0011 = 1000 (+8).

2. Explain about signed binary number with examples.

Signed binary numbers represent both positive and negative values. There are three common
methods to represent signed numbers:
1. Representation: The most significant bit (MSB) indicates the sign (0 for positive, 1 for
negative), and the remaining bits represent the magnitude.

o Example: +5 = 0101, -5 = 1101.

2. 1's Complement: Negative numbers are obtained by inverting all bits of the positive
number.

o Example: +5 = 0101, -5 = 1010.

3. 2's Complement (Most Common): Negative numbers are represented by inverting all bits
of the positive number and adding 1.

o Example: +5 = 0101, -5 = 1011.

3. Explain about NOT, AND, OR gates with truth tables.

The NOT, AND, and OR gates are fundamental logic gates used in digital circuits:
1. NOT Gate: It outputs 1 if the input is 0, and 0 if the input is 1.

o Boolean Expression: Y = A'

o Truth Table:
  A|Y

 0|1

 1|0
2. AND Gate: It outputs 1 only if both inputs are 1.

o Boolean Expression: Y = A · B

o Truth Table:

 A| B |Y

 0|0|0

 0|1|0
 1|0|0

 1|1|1
3. OR Gate: It outputs 1 if at least one input is 1.

o Boolean Expression: Y = A + B

o Truth Table:

 A| B |Y
 0|0|0

 0|1|1

 1|0|1
 1|1|1

4. Design X OR and X-NOR gates using universal gates.

The XOR and XNOR gates can be implemented using NAND gates:
1. XOR Gate using NAND Gates:

o Boolean Expression: Y = A ⊕ B = A'B + AB'

o Implementation:
 Use four NAND gates:

1. First NAND gate: A and B → (A · B)'

 2. Second NAND gate: A and (A · B)' → A' + (A · B)'

3. Third NAND gate: B and (A · B)' → B' + (A · B)'

4. Fourth NAND gate: Outputs of second and third → A'B + AB' (XOR)
2. XNOR Gate using NAND Gates:

o Boolean Expression: Y = (A ⊕ B)' = AB + A'B'

o Implementation:

 Use five NAND gates:

1. Implement XOR using four NAND gates.

2. Add a fifth NAND gate to invert the XOR output, yielding XNOR.

5. Draw the block diagram of full-subtractor with truth table.

Full Subtractor:
A full subtractor is a combinational circuit that performs subtraction of three bits: the minuend (A),
subtrahend (B), and borrow-in (Bin). It produces a difference (D) and borrow-out (Bout).
Block Diagram:

Boolean Expressions:

 D = A ⊕ B ⊕ Bin

 Bout = A'B + A'Bin + BBin

6. Explain the difference between combinational and sequential circuits.

Combinational Circuits:

 Depend only on current inputs.

 No memory elements; output is a direct function of the input.

 Examples: Adders, subtractors, multiplexers, decoders.

Sequential Circuits:

 Depend on both current inputs and previous states (memory).

 Use memory elements like flip-flops or latches to store past states.

 Examples: Counters, registers, finite state machines.

Key Difference:

 Combinational circuits produce outputs based solely on present inputs, while sequential
circuits consider both present inputs and past states, allowing memory and state-dependent
behavior.

7. Explain the distinguish between Multiplexer and Demultiplexer.

Here is the distinguish between Multiplexer and Demultiplexer.

Feature Multiplexer (MUX) Demultiplexer (DEMUX)

Selects one input from many and sends it to Takes one input and sends it to one of
Definition
a single output many outputs

4-to-1 MUX: 4 inputs, 2 select lines, 1 1-to-4 DEMUX: 1 input, 2 select lines, 4
Example
output outputs

Select
Decide which input is passed to the output Decide which output receives the input
Lines

Combines multiple inputs into a single Distributes single input to multiple

Function
output outputs

Usage Data selection Data distribution

Structure Multiple inputs, one output One input, multiple outputs

8. Write a short note on classification of sequential circuits.

Classification of Sequential Circuits:

1. Synchronous Sequential Circuits:

o Use clock signals to synchronize state changes.

 o State depends on both current state and inputs but changes occur at clock pulses.

o Types include flip-flop-based circuits, counters, registers, and finite state machines
(FSMs).
 Mealy Machine: Output depends on state and input.

 Moore Machine: Output depends only on state.

2. Asynchronous Sequential Circuits:

o No clock; state changes immediately with input changes.

o Faster but prone to hazards and race conditions.

o Examples include latches and asynchronous counters.

9. Explain the operation of RS flip flop.

RS Flip-Flop:

An RS flip-flop (SR latch) is a basic digital circuit that stores binary data. It has two inputs, Set (S)
and Reset (R), and two outputs, Q and Q' (the complement of Q).
Truth Table:

S R Q (Next State) Q' (Next State)

0 0 Q (Current) Q' (Current)

10 1 0

01 0 1

1 1 Undefined Undefined

Explanation:

 Hold (S=0, R=0): Retains current state.

 Set (S=1, R=0): Q becomes 1, Q' becomes 0.

 Reset (S=0, R=1): Q becomes 0, Q' becomes 1.
 Undefined (S=1, R=1): Invalid state.

Excitation Table:

Q (Current) Q (Next) S R

0 0 0X

0 1 10

1 0 01

1 1 X0
10. Explain the POS and SOP logic functions.

Sum of Products (SOP):

 SOP is a Boolean expression written as a sum (OR) of minterms (AND terms).

 Minterms are the AND of all variables in either true or complemented form, corresponding
to rows in the truth table where the output is 1.

 Example: If F(X, Y, Z) = 1 for minterms m1, m3, m5, then: F = m1 + m3 + m5 = X'Y'Z + X'YZ
+ XY'Z.
Product of Sums (POS):

 POS is a Boolean expression written as a product (AND) of maxterms (OR terms).

 Maxterms are the OR of all variables in either true or complemented form, corresponding to
rows in the truth table where the output is 0.

 Example: If F(X, Y, Z) = 0 for maxterms M0, M2, M4, then: F = M0 · M2 · M4 = (X + Y + Z)(X

+ Y' + Z')(X' + Y + Z').

SECTION B

11. Discuss in detail about Binary, Decimal, Hexadecimal and Octal number systems with
examples.

Number System:
A Number System is a method of representing numbers using a set of digits or symbols
according to specific rules. It is fundamental in both mathematics and digital computing for
expressing and processing numerical values.
Types of Number Systems:

1. Decimal Number System (Base 10):

o Uses digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.

o Most commonly used in everyday life.

o Example: 345₁₁ represents 3 × 10² + 4 × 10¹ + 5 × 10⁰ = 300 + 40 + 5 = 345.

2. Binary Number System (Base 2):

o Uses digits: 0, 1.

o Essential in digital systems and computing.

o Example: 1011₁ represents 1 × 2³ + 0 × 2² + 1 × 2¹ + 1 × 2⁰ = 8 + 0 + 2 + 1 = 11.

3. Octal Number System (Base 8):

o Uses digits: 0, 1, 2, 3, 4, 5, 6, 7.
 o Often used in computing as a shorthand for binary.
o Example: 57₁ represents 5 × 8¹ + 7 × 8⁰ = 40 + 7 = 47.

4. Hexadecimal Number System (Base 16):

o Uses digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F (where A = 10, B = 11, etc.).

o Commonly used in programming and computer memory addressing.

o Example: 2F₁₁ represents 2 × 16¹ + 15 × 16⁰ = 32 + 15 = 47.

13. What is K-map? Explain how it help in simplifying a given Boolean expression. Draw k-
map for four variables.

What is a K-Map

A K-Map is a visual method used to simplify Boolean expressions. It helps in minimizing the
number of logic gates in digital circuits by grouping minterms or maxterms and reducing redundant
variables.
How K-Map Helps in Simplifying Boolean Expressions:

 Representation:

o Each cell represents a minterm (for SOP) or maxterm (for POS).

o Adjacent cells differ by only one variable (Gray code ordering).

 Grouping:

o Group 1s (for SOP) or 0s (for POS) in powers of 2 (1, 2, 4, 8 cells).

o Each group represents a simplified term in the expression.

 Simplification:

o Combine variables that remain constant within a group, eliminating those that
change.

o The result is a minimized Boolean expression in SOP or POS form.

K-Map for Four Variables:

 Rows = A and B, Columns = C and D, all in Gray code.

14. NAND and NOR gates called as universal gates. Explain.

Answer (from Pages 12-13, under "NAND Gate" and "NOR Gate"):

NAND and NOR Gates as Universal Gates:

NAND and NOR gates are called universal gates because any Boolean logic function or basic
gate (AND, OR, NOT) can be implemented using only NAND or only NOR gates.
NAND Gate:

 Definition: A NAND gate is a combination of AND and NOT gates.

 Boolean Expression: Y = (A · B)'

NAND as Universal Gate:

 NOT gate: (A · A)' = A'

 AND gate: [(A · B)']' = A · B (using two NANDs)

 OR gate: A + B = (A' · B')' using De Morgan’s Law

NOR Gate:

 Definition: A NOR gate is a combination of OR and NOT gates.

 Boolean Expression: Y = (A + B)'

 Truth Table:
 NOR as Universal Gate:

 NOT gate: (A + A)' = A'

 OR gate: [(A + B)']' = A + B (using two NORs)

 AND gate: A · B = (A' + B')' using De Morgan’s Law

15. Design full adder and half subtractor by using universal gates.

Full Adder using NAND Gates:

A full adder adds three bits (A, B, and carry-in Cin) to produce a sum (S) and carry-out (Cout).

Boolean Expressions:

 Sum (S) = A ⊕ B ⊕ Cin

 Cout = AB + BCin + ACin

Implementation:

 Sum (S):

o XOR of A and B using 4 NAND gates.

o XOR the result with Cin using another 4 NAND gates.

 Carry (Cout):

o Each term (AB, BCin, ACin) is done using double NANDs.

o Use NAND-based OR logic to combine the terms.

 Total NAND Gates: ~9 to 12 depending on optimization.

Half Subtractor using NAND Gates:

A half subtractor subtracts two bits (A, B) to produce a difference (D) and borrow-out (Bout).
Boolean Expressions:

 D=A⊕ B

 Bout = A'B

Implementation:

 Difference (D):

o XOR of A and B using 4 NAND gates.

 Borrow (Bout):

o A' = (A · A)' using 1 NAND.

o A'B = [(A' · B)']' using 2 more NAND gates.

 Total NAND Gates: ~5 to 7

16. Explain half adder with truth table. Implement the full adder using two half adders.

Half Adder:
A half adder adds two single-bit inputs (A, B) to produce a sum (S) and carry-out (Cout).

 Boolean Expressions:

o S=A⊕ B

o Cout = A · B
 Truth Table:
Implementing Full Adder using Two Half Adders:
A full adder adds three bits (A, B, Cin) to produce a sum (S) and carry-out (Cout).
 Boolean Expressions:

o S = A ⊕ B ⊕ Cin

o Cout = AB + BCin + ACin

 Implementation:

o First Half Adder: Takes A and B, produces:

 S1 = A ⊕ B

 C1 = A · B
o Second Half Adder: Takes S1 and Cin, produces:

 S = S1 ⊕ Cin = (A ⊕ B) ⊕ Cin

 C2 = S1 · Cin = (A ⊕ B) · Cin
o Carry-Out: Combine carries from both half adders:

 Cout = C1 + C2 = AB + (A ⊕ B) · Cin

o Use an OR gate to combine C1 and C2.

 Circuit:

o First half adder: A, B → S1, C1

o Second half adder: S1, Cin → S, C2

o OR gate: C1, C2 → Cout

17. Explain the working of Demultiplexer and Decoder circuit diagram.

Demultiplexer:

A demultiplexer is a combinational circuit that takes one input and channels it to one of many
outputs based on select lines.
  Working Principle:
o Routes input D to one output line based on binary value of select lines (e.g., S1, S0
for 1-to-4 DEMUX).
o Uses AND and NOT gates to direct the input.

 Circuit Diagram:

D -----[AND]---- Y0 (S1' · S0' · D)

[AND]---- Y1 (S1' · S0 · D)
[AND]---- Y2 (S1 · S0' · D)

[AND]---- Y3 (S1 · S0 · D)

S1, S0 ----[Select Logic]

Decoder:

A decoder is a circuit that takes binary inputs and activates one output line corresponding to
the input combination.
Working Principle:

 Has n inputs and up to 2ⁿ outputs.

 Each output is activated based on a unique input combination.

 Circuit Diagram:

o Uses AND gates with inputs and their complements to generate each output.

A1, A0 ----[AND]---- Y0 (A1' · A0')

[AND]---- Y1 (A1' · A0)

[AND]---- Y2 (A1 · A0')

[AND]---- Y3 (A1 · A0)

19. What is difference between latch and flip-flop? Explain about clocked RS flip flop using
NAND gate.
Difference Between Latch and Flip-Flop:

Feature Flip-Flop Latch

Level-triggered (changes with input

Trigger Type Edge-triggered (needs clock pulse)
level)

Operation Synchronous (clock-based) Asynchronous (no clock needed)

Feature Flip-Flop Latch

Clock
Requires clock signal Does not require clock signal
Dependency

Low as it only responds to input

Power Usage Lower due to clock regulation
changes

Works with current/past input & output + Works with current/past input &
Data Handling
clock output

Circuit Analysis Easier More complex

Construction Built using latches + clock Built using logic gates

Clocked RS Flip-Flop using NAND Gates:

Definition:

A clocked RS flip-flop adds a clock input to an RS latch made with NAND gates, making it
synchronous.

Working:

S R Q (Next) Q' (Next) State

0 0 No Change No Change Hold

01 0 1 Reset

10 1 0 Set

1 1 Invalid Invalid Unpredictable State

Explanation:

 S=0, R=0: No change in output.

 S=0, R=1: Reset state (Q=0, Q'=1).

 S=1, R=0: Set state (Q=1, Q'=0).

 S=1, R=1: Invalid state (both outputs 0, unreliable)

Clocked Operation:

 Uses extra NAND gates to combine S and R with the clock signal.
 The flip-flop responds only when clock is high, ensuring controlled timing.

20. Convert D flip flop into RS flip flop and JK flip flop.
Objective:

Convert a D flip-flop (1 input) into an RS flip-flop (2 inputs: Set (S), Reset (R)).

RS Flip-Flop Characteristic Table:

S R Q(t+1)

0 0 Q(t)

10 1

01 0

1 1 Undefined

Key Boolean Expression:

 D = S + R'Q(t)
(Logic to generate D from S, R, and current Q)
Circuit Elements:

 NOT gate: For R'

 AND gate: For R'Q(t)

 OR gate: Combines S and R'Q(t)

 Output of OR gate connects to D flip-flop.

2. D Flip-Flop to JK Flip-Flop Conversion

Objective:

Convert a D flip-flop into a JK flip-flop (2 inputs: J, K).

JK Flip-Flop Characteristic Table:

J K Q(t+1)

0 0 Q(t)

10 1

01 0

1 1 ~Q(t)

Key Boolean Expression:

 D = JQ' + K'Q
Circuit Elements:

 NOT gates: For Q' and K'

 AND gates: For JQ' and K'Q

 OR gate: Combines outputs to form D

 Result feeds into D flip-flop.