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TPS565201
SLVSE71 – SEPTEMBER 2017

TPS565201 4.5-V to 17-V Input, 5-A Synchronous Step-Down Voltage Regulator

1 Features 3 Description
•
1 5-A Maximum Output Current The TPS565201 is a simple, easy-to-use, 5-A
synchronous step-down converter.
• Integrated 31-mΩ and 16-mΩ FETs
• D-CAP2™ Mode Control with Fast Transient The device is optimized to operate with minimum
Response external component counts and also optimized to
achieve low standby current.
• Input Voltage Range: 4.5 V to 17 V
This switch mode power supply (SMPS) device
• Output Voltage Range: 0.76 V to 7 V
employs D-CAP2™ control, which provides fast
• High Efficiency at Light Loads with Pulse-skipping transient response and requires no external
Eco-mode™ compensation components. D-CAP2 also allows the
• 500-kHz Switching Frequency use of low-equivalent series resistance (ESR)
• ≤1 µA Shutdown Current specialty polymer capacitors and ceramic output
capacitors.
• 1% Feedback Voltage Accuracy
The TPS565201 operates in pulse skip mode,
• Startup from Pre-Biased Output Voltage
maintaining high efficiency during light load operation.
• Cycle-by-Cycle Current Limit
The TPS565201 device is available in a 6-pin 1.6-mm
• Hiccup-mode Overcurrent Protection
× 2.9-mm SOT (DDC) package, and operates over a
• Non-Latch UVP, UVLO and TSD Protections –40°C to 125°C junction temperature range.

2 Applications Device Information(1)

• Digital TV Power Supply PART NUMBER PACKAGE BODY SIZE (NOM)

• High Definition Blu-ray™ Disc Players TPS565201 DDC (6) 1.60 mm × 2.90 mm

• Networking Home Terminal (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Digital Set Top Box (STB)
• Surveillance spacer
spacer
Simplified Schematic
CBST
TPS565201 Efficiency
100%
TPS565201
90%
1 6
GND VBST 80%
LO 2 5
VOUT SW EN EN 70%
60%
Efficiency

CO 3 4
VIN VIN VFB VOUT

RFB2 RFB1 50%

CIN

40%
Copyright © 2016, Texas Instruments Incorporated
30% VOUT = 1.05 V
VOUT = 1.5 V
20% VOUT = 1.8 V
10% VOUT = 3.3 V
VOUT = 5 V
0
0.001 0.01 0.1 1 5
Output Current (A) D017

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 11
2 Applications ........................................................... 1 8 Application and Implementation ........................ 12
3 Description ............................................................. 1 8.1 Application Information............................................ 12
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 12
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 17
6 Specifications......................................................... 4 10 Layout................................................................... 18
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 18
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 18
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 19
6.4 Thermal Information .................................................. 4 11.1 Receiving Notification of Documentation Updates 19
6.5 Electrical Characteristics........................................... 5 11.2 Community Resources.......................................... 19
6.6 Typical Characteristics .............................................. 6 11.3 Trademarks ........................................................... 19
7 Detailed Description .............................................. 9 11.4 Electrostatic Discharge Caution ............................ 19
7.1 Overview ................................................................... 9 11.5 Glossary ................................................................ 19
7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 10 Information ........................................................... 19

4 Revision History
DATE REVISION NOTES
September 2017 * Initial release.

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5 Pin Configuration and Functions

DDC Package
6-Pin SOT
Top View

GND 1 6 VBST

SW 2 5 EN

VIN 3 4 VFB

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Ground pin. Source terminal of low-side power NFET as well as the ground terminal for
GND 1 —
controller circuit. Connect sensitive VFB to this GND at a single point.
SW 2 O Switch node connection between high-side NFET and low-side NFET.
VIN 3 I Input voltage supply pin. The drain terminal of high-side power NFET.
VFB 4 I Converter feedback input. Connect to output voltage with feedback resistor divider.
EN 5 I Enable input control. Active high and must be pulled up to enable the device.
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST 6 O
VBST and SW pins.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN, EN –0.3 19 V
VBST –0.3 25 V
VBST (10 ns transient) –0.3 27 V
Input voltage VBST (vs SW) –0.3 6.5 V
VFB –0.3 6.5 V
SW –2 19 V
SW (10 ns transient) –3.5 21 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Supply input voltage range 4.5 17 V
VBST –0.1 23
VBST (10 ns transient) –0.1 26
VBST (vs SW) –0.1 6.0
VI Input voltage range EN –0.1 17 V
VFB –0.1 5.5
SW –1.8 17
SW (10 ns transient) –3.5 20
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

TPS565201
THERMAL METRIC (1) DDC (SOT) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 95.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35.6 °C/W
RθJB Junction-to-board thermal resistance 16.4 °C/W
ψJT Junction-to-top characterization parameter 1.4 °C/W
ψJB Junction-to-board characterization parameter 16.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Operating – non-switching
IVIN VIN current, EN = 5 V, VFB = 1 V 320 510 µA
supply current
IVINSDN Shutdown supply current VIN current, EN = 0 V 0.8 5 µA
LOGIC THRESHOLD
VENH EN high-level input voltage 1.6 V
VENL EN low-level input voltage 0.8 V
REN EN pin resistance to GND VEN = 12 V 120 245 400 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH VFB threshold voltage 753 760 767 mV
IVFB VFB input current VFB = 0.8 V. TA = 25°C 0 ±0.1 µA
MOSFET
RDS(on)h High-side switch resistance TA = 25°C, VBST – VSW = 5.5 V 31 mΩ
RDS(on)l Low-side switch resistance TA = 25°C 16 mΩ
CURRENT LIMIT
IOCL Current limit 5.3 6.7 8 A
THERMAL SHUTDOWN
Thermal shutdown Shutdown temperature 172
TSDN °C
threshold (1) Hysteresis 38
ON-TIME TIMER CONTROL
tOFF(MIN) Minimum off time VFB = 0.61 V 236 280 ns
SOFT START
tSS Soft-start time Internal soft-start time 1.0 ms
FREQUENCY
Fsw Switching frequency VIN = 12 V, VO = 5 V, CCM mode 500 kHz
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP Output UVP threshold Hiccup detect (H > L) 65 %
THICCUP_WAIT Hiccup on time 1.8 ms
THICCUP_RE Hiccup time before restart 14.9 ms
UVLO
Wake up VIN voltage 4.0 4.3
UVLO UVLO threshold Shutdown VIN voltage 3.3 3.6 V
Hysteresis VIN voltage (1) 0.4

(1) Not production tested.

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6.6 Typical Characteristics

VIN = 12 V (unless otherwise noted)

0.45 0.763
Buck Quiescent Current ( mA)

0.4 0.762

FB Voltage ( V)
0.35 0.761

0.3 0.76

0.25 0.759

0.2 0.758
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature (qC) D001
Junction Temperature (qC) D002

Figure 1. TPS565201 Supply Current vs Junction Figure 2. VFB Voltage vs Junction Temperature
Temperature
1.23 1.45

1.2
1.42
EN Pin UVLO - High (V)
EN Pin UVLO - Low (V)

1.17

1.39
1.14

1.11
1.36

1.08
1.33
1.05

1.02 1.3
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature (qC) D004
Junction Temperature (qC) D003

Figure 3. EN Pin UVLO Low Voltage vs Junction Figure 4. TPS565201 EN Pin UVLO High Voltage vs Junction
Temperature Temperature
60 28

55
High-Side Rds_on (m:)

50 24
Low Side Rds_on (m:)

45

40 20

35

30 16

25

20 12
-50 -30 -10 10 30 50 70 90 110 130 -50 -20 10 40 70 100 130
Junction Temperature (qC) D042
Junction Temperature (qC) D006

Figure 5. TPS565201 High-Side Rds-On vs Junction Figure 6. Low-Side Rds-On vs Junction Temperature
Temperature

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Typical Characteristics (continued)

VIN = 12 V (unless otherwise noted)
600 600
VOUT = 1.8 V
VOUT = 3.3 V
580 VOUT = 5 V 500

Switching Frequency (KHz)

Switching Frequency (kHz)

560 400

540 300

520 200

500 100 VOUT = 1.05V

VOUT = 3.3V
VOUT = 5V
480 0
4 6 8 10 12 14 16 18 0.001 0.01 0.1 1 5
Input Voltage (V) D018
Output Current (A) D046

Figure 7. TPS565201 Switching Frequency Figure 8. TPS565201 Switching Frequency

vs Input Voltage vs Output Current
100% 100%
90% 90%
80% 80%
70% 70%
60% 60%
Efficiency

Efficiency

50% 50%
40% 40%
30% 30%
VIN = 5 V VIN = 5 V
20% VIN = 9 V 20% VIN = 9 V
10% VIN = 12 V 10% VIN = 12 V
VIN = 15 V VIN = 15 V
0 0
0.001 0.01 0.1 1 5 0.001 0.01 0.1 1 5
Output Current (A) D040
Output Current (A) D019
VOUT = 1.05 V L = 2.2 µH VOUT = 1.5 V L = 2.2 µH

Figure 9. TPS565201 Efficiency vs Output Current Figure 10. TPS565201 Efficiency vs Output Current
100% 100%
90% 90%
80% 80%
70% 70%
60% 60%
Efficiency

Efficiency

50% 50%
40% 40%
30% 30%
VIN = 5 V VIN = 5 V
20% VIN = 9 V 20% VIN = 9 V
10% VIN = 12 V 10% VIN = 12 V
VIN = 15 V VIN = 15 V
0 0
0.001 0.01 0.1 1 5 0.001 0.01 0.1 1 5
Output Current (A) D020
Output Current (A) D041
VOUT = 1.8 V L = 2.2 µH VOUT = 3.3 V L = 2.2 µH

Figure 11. TPS565201 Efficiency vs Output Current Figure 12. TPS565201 Efficiency vs Output Current

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Typical Characteristics (continued)

VIN = 12 V (unless otherwise noted)
100%
90%
80%
70%
60%

Efficiency
50%
40%
30%
20% VIN = 9 V
10% VIN = 12 V
VIN = 15 V
0
0.001 0.01 0.1 1 5
Output Current (A) D021
VOUT = 5 V L = 3.3 µH

Figure 13. TPS565201 Efficiency vs Output Current

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7 Detailed Description

7.1 Overview
The TPS565201 is a 5-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports
low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without
complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the
output capacitance required to meet a specific level of performance.

7.2 Functional Block Diagram

EN 5 3 VIN

VUVP + Hiccup
UVP Control Logic VREG5
Regulator

+
OVP UVLO
VOVP
VFB 4
+ 6 VBST
Voltage PWM
+
+
Reference

Soft Start SS
HS
+
Internal Ramp 2 SW
One-Shot XCON
Ripple Injection VREG5
TSD
LS
OCL
threshold OCL 1 GND
+

+
ZC

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7.3 Feature Description

7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS565201 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control
with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration
with low-ESR ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN,
and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range,
hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on
again when the feedback voltage falls below the reference voltage. An ripple is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode control.

7.3.2 Pulse Skip Mode

The TPS565201 is designed with Eco-mode™ to maintain high light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The transition point to the light load
operation IOUT(LL) current can be calculated in Equation 1.
1 (V - VOUT ) ´ VOUT
IOUT(LL) = ´ IN
2 ´ L ´ ¦ SW VIN (1)

7.3.3 Soft Start and Pre-Biased Soft Start

The TPS565201 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converter ramps up smoothly into regulation point.

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Feature Description (continued)

7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The
inductor current is monitored during the OFF state by measuring the low-side FET drain to source voltage, which
is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, and the output inductor value. During the on time of the low-side FET switch, this current decreases
linearly. The average value of the switch current is the load current IOUT. If the monitored current is above the
OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage
feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles,
the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time
(typically 24 µs) and re-starts after the hiccup time (typically 14.9 ms).
When the over current condition is removed, the output voltage returns to the regulated value.

7.3.5 Undervoltage Lockout (UVLO) Protection

UVLO protection monitors input voltage. When the voltage is lower than UVLO threshold voltage, the device is
shut off. This protection is non-latching.

7.3.6 Thermal Shutdown

The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),
the device is shut off. This is a non-latch protection.

7.4 Device Functional Modes

7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS565201 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS565201 operates at a quasi-fixed frequency of 500
kHz.

7.4.2 Eco-mode™ Operation

When the TPS565201 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS565201
begins operating in pulse skipping eco-mode. Each switching cycle is followed by a period of energy saving sleep
time. The sleep time ends when the VFB voltage falls below the eco-mode threshold voltage. As the output
current decreases, the perceived time between switching pulses increases.

7.4.3 Standby Operation

When the TPS565201 is operating in either normal CCM or Eco-mode™, it may be placed in standby by
asserting the EN pin low.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with
a maximum available output current of 5 A. The following design procedure can be used to select component
values for the TPS565201. Alternately, the WEBENCH® software may be used to generate a complete design.
The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design. This section presents a simplified discussion of the design process.

8.2 Typical Application

The application schematic in Figure 14 shows the TPS565201 4.5-V to 17-V input, 1.05-V output converter
design meeting the requirements for 5-A output. This circuit is available as the evaluation module (EVM). The
sections provide the design procedure.

C7 0.1 F

TPS565201

1 6
GND VBST

VOUT = 1.05 V / 5 L1
A 2 5 R3 10 k
VOUT SW EN EN
2.2 H
C9 C8
3 4
22 F 22 F VIN VFB VOUT
R1 3.74 k

R2
10 k
1 C4
C1 C2 C3
10 F 10 F 0.1 F
Not Installed 1

VIN
VIN = 4.5 V to 17 V
Copyright © 2016, Texas Instruments Incorporated

Figure 14. TPS565201 1.05-V, 5-A Reference Design

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Typical Application (continued)

8.2.1 Design Requirements
Table 1 shows the design parameters for this application.

Table 1. Design Parameters

PARAMETER EXAMPLE VALUE
Input voltage range 4.5 to 17 V
Output voltage 1.05 V
Transient response, 1-A/us slew rate ΔVout = ±5%
Input ripple voltage 400 mV
Output ripple voltage 20 mV
Output current rating 5A
Operating frequency 550 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors. However, using too high of
resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will
be more noticeable.
æ R1 ö
VOUT = 0.760 ´ ç 1 +
è R2 ÷ø (2)

8.2.2.2 Output Filter Selection

The LC filter used as the output filter has double pole at:
1
fP
2S LOUT u COUT (3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.

Table 2. Recommended Component Values

OUTPUT L1 (µH)
R1 (kΩ) R2 (kΩ) C8 + C9 (µF)
VOLTAGE (V) MIN TYP MAX
1 3.09 10.0 1.0 2.2 4.7 20 to 68
1.05 3.74 10.0 1.0 2.2 4.7 20 to 68
1.2 5.76 10.0 1.0 2.2 4.7 20 to 68
1.5 9.53 10.0 1.5 2.2 4.7 20 to 68
1.8 13.7 10.0 1.5 2.2 4.7 20 to 68
2.5 22.6 10.0 2.2 2.2 4.7 20 to 68
3.3 33.2 10.0 2.2 2.2 4.7 20 to 68
5 54.9 10.0 3.3 3.3 4.7 20 to 68
6.5 75 10.0 3.3 3.3 4.7 20 to 68

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The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 550 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 7.
VOUT VIN(MAX) - VOUT
IP-P = u
VIN(MAX) LO u fSW (4)
IIP P
IPEAK = IO
2 (5)
1
ILO(RMS) IO2 IlP P
2
12 (6)
For this design example, the calculated peak current is 5.4 A and the calculated RMS current is 5 A. The
inductor used is a WE 744311220 with a peak current rating of 13 A and an RMS current rating of 9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS565201 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7
to determine the required RMS current rating for the output capacitor.
VOUT u VIN VOUT
ICO(RMS)
12 u VIN u LO u fSW (7)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.229 A.

8.2.2.3 Input Capacitor Selection

The TPS565201 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.

8.2.2.4 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.

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8.2.3 Application Curves

3% 3%

2% 2%

1% 1%
Output Voltage

Output Voltage
0 0

-1% -1%

-2% -2%

-3% -3%
0 1 2 3 4 5 0 1 2 3 4 5
Output Current (A) D050
Output Current (A) D051
VIN = 5 V VOUT = 1.05 V VIN = 12 V VOUT = 1.05 V

Figure 15. Load Regulation, VIN = 5 V Figure 16. Load Regulation, VIN = 12 V

1.05 100%
90%
1.048
80%
1.046 70%
Output Voltage (V)

60%
Efficiency

1.044
50%
1.042
40%

1.04 30%
VIN = 5 V
20% VIN = 9 V
1.038 VIN = 12 V
10%
VIN = 15 V
1.036 0
4 6 8 10 12 14 16 18 0.001 0.01 0.1 1 5
Input Voltage (V) D045
Output Current (A) D040
VOUT = 1.05 V

Figure 17. Line Regulation Figure 18. Efficiency vs Output Current

1 µs/div 1 µs/div

Figure 19. TPS565201 Input Voltage Ripple Figure 20. TPS565201 Output Voltage Ripple, No Load

Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS565201
TPS565201
SLVSE71 – SEPTEMBER 2017 www.ti.com

1 µs/div 1 µs/div

Figure 21. TPS565201 Output Voltage Ripple, IOUT 2.5 A Figure 22. TPS565201 Output Voltage Ripple, IOUT 5 A

100 µs/div 100 µs/div

Figure 23. TPS565201 Transient Response 0.1 to 2.5 A Figure 24. TPS565201 Transient Response, 1.25 to 3.75 A

100 µs/div 2 ms/div

Figure 25. TPS565201 Transient Response, 2.5 to 5 A Figure 26. TPS565201 Startup Relative to VIN

16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

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 TPS565201
www.ti.com SLVSE71 – SEPTEMBER 2017

400 µs/div 20 ms/div

Figure 27. TPS565201 Startup Relative to EN Figure 28. TPS565201 Shutdown Relative to VIN

400 µs/div

Figure 29. TPS565201 Shutdown Relative to EN

9 Power Supply Recommendations

The TPS565201 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 83%. Using that criteria, the minimum recommended input voltage is VO / 0.83.

Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPS565201
TPS565201
SLVSE71 – SEPTEMBER 2017 www.ti.com

10 Layout

10.1 Layout Guidelines

1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.

10.2 Layout Example

Trace on the
VOUT GND bottom layer

Additional
OUTPUT Vias to the
CAPACITOR GND plane
BOOST
CAPACITOR

GND VBST
FEEDBACK
TO ENABLE RESISTORS
SW EN CONTROL

OUTPUT
INDUCTOR
VFB
VIN VIN

GND trace under IC

On top layer
INPUT BYPASS
CAPACITOR GND

Figure 30. TPS565201 Layout Example

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 TPS565201
www.ti.com SLVSE71 – SEPTEMBER 2017

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TPS565201
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS565201DDCR ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5201

TPS565201DDCT ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5201

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS565201DDCR SOT-23- DDC 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
THIN
TPS565201DDCT SOT-23- DDC 6 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
THIN

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS565201DDCR SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
TPS565201DDCT SOT-23-THIN DDC 6 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DDC0006A SCALE 4.000
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR

3.05 1.1
2.55 0.7
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

4X 0.95

3.05
1.9
2.75

4
3

0.5 0.1
6X TYP
0.3 0.0
0.2 C A B

C
0 -8 TYP

SEATING PLANE 0.25

0.20
TYP GAGE PLANE
0.12
0.6
TYP
0.3

ALTERNATIVE PACKAGE
SINGULATION VIEW

4214841/D 06/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDC0006A SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR

SYMM
6X (1.1)
1

6X (0.6) 6

SYMM

4X (0.95)

4
3

(R0.05) TYP
(2.7)

LAND PATTERN EXAMPLE

EXPLOSED METAL SHOWN
SCALE:15X

METAL UNDER SOLDER MASK

SOLDER MASK METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL

EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDERMASK DETAILS

4214841/D 06/2024

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDC0006A SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR

SYMM
6X (1.1)
1

6X (0.6) 6

SYMM

4X(0.95)

4
3

(R0.05) TYP
(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:15X

4214841/D 06/2024

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
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