®
82C86H
June 2004 CMOS Octal Bus Transceiver
Features Description
• Full Eight Bit Bi-Directional Bus Interface The Intersil 82C86H is a high performance CMOS Octal
Transceiver manufactured using a self-aligned silicon gate
• Industry Standard 8286 Compatible Pinout
CMOS process (Scaled SAJI IV). The 82C86H provides a full
• High Drive Capability eight-bit bi-directional bus interface in a 20 lead package. The
- B Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Transmit (T) control determines the data direction. The active
low output enable (OE) permits simple interface to the 80C86,
- A Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
80C88 and other microprocessors. The 82C86H has gated
• Three-State Outputs inputs, eliminating the need for pull-up/pull-down resistors and
reducing overall system operating power dissipation.
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs
- Reduce Operating Power Ordering Information
- Eliminate the Need for Pull-Up Resistors
PART NUMBER
• Single 5V Power Supply
8MHz PACKAGE TEMP. RANGE PKG DWG. #
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA ID82C86H 20 Ld CERDIP -40oC to +85oC F20.3
• Operating Temperature Range
- ID82C86H . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Pinout
82C86H (CERDIP) TRUTH TABLE
TOP VIEW
T OE A B
X H Hi-Z Hi-Z
A0 1 20 VCC H L I O
A1 2 19 B0 L L O I
A2 3 18 B1 H = Logic One
A3 4 17 B2 L = Logic Zero
I = Input Mode
A4 5 16 B3
O = Output Mode
A5 6 15 B4 X = Don’t Care
A6 7 14 B5 Hi-Z = High Impedance
A7 8 13 B6
PIN NAMES
OE 9 12 B7
PIN DESCRIPTION
GND 10 11 T
A0-A7 Local Bus Data I/O Pins
B0-B7 System Bus Data I/O Pins
T Transmit Control Input
OE Active Low Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. FN2977.2
Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved
1
82C86H
Functional Diagram Decoupling Capacitors
The transient current required to charge and discharge the
A0 300pF load capacitance specified in the 82C86H/87H data
B0 sheet is determined by:
I = C L ( dv ⁄ dt ) (EQ. 1)
A1 B1
A2 B2
Assuming that all outputs change state at the same time and
A3 B3 that dv/dt is constant;
A4 B4 ( VCC × 80% ) (EQ. 2)
I = C L -------------------------------------
A5 B5
tR ⁄ tF
A6 B6 where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight out-
puts.
A7 B7
– 12 –9
I = ( 80 × 300 × 10 ) × ( 5.0V × 0.8 ) ⁄ ( 20 × 10 ) (EQ. 3)
= 480mA
OE
T VCC VCC
P
Gated Inputs P
During normal system operation of a latch, signals on the N
STB
bus at the device inputs will become high impedance or P
make transitions unrelated to the operation of the latch. INTERNAL
DATA IN
These unrelated input transitions switch the input circuitry DATA
and typically cause an increase in power dissipation in N
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input switch- N
ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in device FIGURE 1. 82C82/83H
operation.
VCC
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
P
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the VCC and OE
ground power supply pins by turning off the upper P-channel P
and lower N-channel (See Figures 1 and 2). No current flow INTERNAL
DATA IN DATA
from VCC to GND occurs during input transitions and invalid
VCC N
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device. P
D.C. input voltage levels can also cause an increase in ICC if N
these input levels approach the minimum VIH or maximum N
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi- FIGURE 2. 82C86H/87H GATED INPUTS
tion will occur only during the time the device is in the trans- This current spike may cause a large negative voltage spike
parent mode (STB = logic one). ICC remains below the on VCC which could cause improper operation of the device.
maximum ICC standby specification of 10µA during the time To filter out this noise, it is recommended that a 0.1µF
inputs are disabled, thereby greatly reducing the average ceramic disc capacitor be placed between VCC and GND at
power dissipation of the 82C8X series devices. each device, with placement being as near to the device as
possible.
2
82C86H
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V CERDIP Package . . . . . . . . . . . . . . . . 70 16
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Maximum Storage Temperature Range . . . . . . . . . -65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Operating Conditions Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5.0V ± 10%; TA = -40oC to +85oC
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
VIH Logical One 2.0 - V C82C86H, I82C86H
Input Voltage 2.2 V M82C86H (Note 1)
VIL Logical Zero Input Voltage - 0.8 V
VOH Logical One Output Voltage
B Outputs 3.0 V IOH = -8mA
A Outputs 3.0 V IOH = -4mA
A or B Outputs VCC -0.4 V IOH = -100µA
VOL Logical Zero Output Voltage
B Outputs 0.45 V IOL = 20mA
A Outputs 0.45 V IOL = 12mA
II Input Leakage Current -10.0 10.0 µA VIN = GND or VCC DIP Pins 9, 11
IO Output Leakage Current -10.0 10.0 µA VO = GND or VCC, OE Š Š≥ VCC -0.5V
DIP Pins 1 - 8, 12 - 19
ICCSB Standby Power Supply - 10 µA VIN = VCC or GND, VCC = 5.5V, Outputs Open
Current
ICCOP Operating Power Supply - 1 mA/MHz TA = +25oC, Typical (See Note 2)
Current
NOTES:
1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data input at a time and checking the corresponding device output for
a valid logical “1” during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at VCC -0.4
2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA).
Capacitance TA = +25oC
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIN Input Capacitance
B Inputs 18 pF Freq = 1MHz, all measurements are
referenced to device GND
A Inputs 14 pF
3
82C86H
AC Electrical Specifications VCC = 5.0V ± 10%; Freq = 1MHz: TA = -40oC to +85oC
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
(1) TIVOV Input to Output Delay Notes 1, 2
Inverting 5 30 ns
Non-Inverting 5 32 ns
(2) TEHTV Transmit/Receive Hold Time 5 - ns Notes 1, 2
(3) TTVEL Transmit/Receive Setup Time 10 - ns Notes 1, 2
(4) TEHOZ Output Disable Time 5 30 ns Notes 1, 2
(5) TELOV Output Enable Time 10 50 ns Notes 1, 2
(6) TR, TF Input Rise/Fall Times - 20 ns Notes 1, 2
(7) TEHEL Minimum Output Enable High Time Note 3
82C86H 30 - ns
82C86H-5 35 - ns
NOTES:
1. All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven
at 1ns/V.
2. Input test signals must switch between VIL - 0.4V and VIH +0.4V.
3. A system limitation only when changing direction. Not a measured parameter.
Timing Waveform
TR, TF (6)
2.0V
INPUTS
0.8V
TEHEL (7)
OE
(1) (4)
TELOV (5)
TIVOV TEHOZ
VOH -0.1V 3.0V
OUTPUTS
VOL +0.1V 0.45V
TEHTV (2) TTVEL (3)
NOTE: All timing measurements are made at 1.5V unless otherwise noted.
4
82C86H
Test Load Circuits
A SIDE OUTPUTS
TELOV OUTPUT HIGH TELOV OUTPUT LOW TEHOZ OUTPUT LOW/HIGH
TIVOV LOAD CIRCUIT ENABLE LOAD CIRCUIT ENABLE LOAD CIRCUIT DISABLE LOAD CIRCUIT
2.36V 1.5V 1.5V 2.36V
160Ω 375Ω 91Ω 160Ω
TEST TEST TEST TEST
OUTPUT OUTPUT OUTPUT OUTPUT
POINT POINT POINT POINT
100pF 100pF 100pF 50pF
(SEE NOTE) (SEE NOTE) (SEE NOTE) (SEE NOTE)
B SIDE OUTPUTS
TELOV OUTPUT HIGH TELOV OUTPUT LOW TEHOZ OUTPUT LOW/HIGH
TIVOV LOAD CIRCUIT ENABLE LOAD CIRCUIT ENABLE LOAD CIRCUIT DISABLE LOAD CIRCUIT
2.27V 1.5V 1.5V 2.27V
91Ω 180Ω 51Ω 91Ω
TEST TEST TEST TEST
OUTPUT OUTPUT OUTPUT OUTPUT
POINT POINT POINT POINT
300pF 300pF 300pF 50pF
(SEE NOTE) (SEE NOTE) (SEE NOTE) (SEE NOTE)
NOTE: Includes jig and stray capacitance.
Die Characteristics
DIE DIMENSIONS:
138.6 x 155.5 x 19 ± 1mils
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
5
82C86H
Metallization Mask Layout
82C86H
A2 A1 A0 VCC B0 B1
B2
A3
B3
A4
B4
A5
B5
A6
A7 OE GND T B7 B6
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