Ministry of Education and Sciences of Ukraine National Aviation University Radio-electronics Department

COURSE PROJECT
from discipline

DIGITAL ENGINEERING The theme of project: SYNTHESIS OF DIGITAL COUNTER

Prepared by: student of group IACS 312 Managadze Yuriy

Kyiv 2011

CONTENT

1. The problem of course project 2. Introduction 3. Essay 4. Synthesis of digital counter 5. Conclusions 6. References.

NAU
Done by Supervisor Critic . . Adopted by Managadze Y. Bidnyi M.S. . Page 1 Pages

Digital engineering

IACS-312

THE PROBLEM OF COURSE PROJECT Theme of yearly project: digital counter with two mode of operation. Initial data: counter with permitting input M. - counting coefficient is specified by table 1 in accordance with variant: M=0 binary counter; M=1 counter in the given code (in accordance with the table). integral circuits, used for combination circuit construction, are specified by table 1. - types of flip-flops also are specified. - integral digital circuits and flip-flops of specified types are chosen by student himself. Problem: to design digital counter with two operation modes controlled by permitting signal M. 9 Kc 16 Code Comb. circ. Flip-flop Direct DC JK code/Additional Annotation DC with inverted out.

1. ESSAY Introduction 1. In this paper designing of digital counter with two operation modes, controlled by switching signal M, is presented. 2. The object of the work is to learn different methods of counter realization, which implementation is possible using different types of flip-flops and combinational parts. 3. The method of learning and familiarization is structural synthesis of Meally and Moore counters. 4. Combination circuit can be constructed with the help of logic gates, multiplexers, integral circuits of programmable memory, programmable logic matrix, etc. Digital counters Counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Digital counters are devices, the outputs of which are dependent not only on meaning of input signal, but also on inner state of circuit in one and previous moments of time. So one of the main peculiarities of such circuits is that the ones have inner states which are sousing reaction of circuit on input signal. Usually, counter circuits are digital in nature, and count in natural binary. Many types of counter circuits are available as digital building blocks. Occasionally there are advantages to using a counting sequence other than the natural binary sequencesuch as the binary coded decimal counter, a linear feedback shift register counter, a Gray-code counter or excess-3 counter. The elements of memory could be asynchronous or synchronous. Synchronous counters operate in accordance with external signals. Abstract counter model is a counter A. Counter A is specified by sets X, , Z, and two functions and . A={X, Y, Z, , , Z0 } (1)

where X={X1, X2,.., Xn} a finite set called the input alphabet; Y={Y1, Y2,.., Ym}-a finite set called the output alphabet; Z={Z0, Z1,, Zk} set of states; function of counter transition; function of counter outputs, Z0 initial state. In every moment t=0,1,2,... of discrete time the counter is stand in some state Z(t) from set Z. In initial moment t the counter is always in state Z(0)=Z0.

Fig. 1

In accordance with method of output signal determining counters are divided into Mealy and Moore machines. In the theory of computation, a Mealy machine is a finite-state machine whose output values are determined both by its currentstate and the current inputs. The low of Mealy machine functioning is set by equation: Z (t+1) = (Z(t), (t)); Y(t) = (Z(t), (t)); (2) (3)

where t=0,1,2.. moments of discrete time, function (Z(t),(t)) determines next state of counter and called function of transition, function (Z(t),(t)) determines output signals and called function of counter output.

Structural scheme of Mealy machine is:

Combin. circuit of inputs

Circuit of memory

Combin. circuit of outputs

Fig. 2 Structural scheme of Mealy machine

The outputs change asynchronously with respect to the clock, meaning that the outputs change at unpredictable times, making timing analysis harder. This is in contrast to a Moore machine, whose output values are determined solely by its current state. The low of Moore machine functioning is set by equation: Z (t+1) = (Z(t), X(t)); Y(t)= (Z(t)). (4) (5)

where t=0,1,2.. moments of discrete time, function (Z(t),(t)) determines next state of counter and called function of transition, function (Z(t)) determines output signals and called function of counter output. Moore machine is a finite-state machine, whose output values are determined solely by its current state. Structural scheme of Moore Machine:

Combin. circuit of inputs

Circuit of memory

Combin. circuit of outputs

Fig. 3 Structural scheme of Moore Machine

Methods of counter specifying For the complete specifying of counter A it is necessary to describe all elements of set ={,,Z, , , z0}. The most exploiting methods of counter specifying is graphical and table ones. Principle of graphical method lies in construction of graph of counters working. A graph is an abstract representation of a set of objects where some objects are connected by links. The interconnected objects are represented by mathematical abstractions called nodes, and the links that connect some pairs of vertices are called edges. Nodes of graph of counters working present its states, and adges present trnsitions between states.

COUNTER SYNTHESIS

Designing of counter with two operation modes, controlled by input signal M. Counting coefficient is 16. M=0 - Direct code is a way of representing binary numbers with fixed point in computer arithmetic. Usually used for representing of positive numbers. M=1 Ones Complement code

Constructing of counters transitions truth table: Table 1. Truth table of JK-flip-flop.

Qt
0 0 1 1

Q t 1 J K
0 1 0 1 0 1 - 1 - 0

Table 2.
M 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Karnaugh maps and minimization for JK-flip-flop

000 00 01 11 10

001

011

010

110

111

101

100

000 00 01 11 10

001

011

010

110

111

101

100

0 0 0 0

0 0 1 0

0 0 0 0

1 0 0 0

0 0 1 0

0 0 0 0

1 0 0 0

0 0 0 0

000 00 01 11 10

001

011

010

110

111

101

100

000 00 01 11 10

001

011

010

110

111

101

100

0 0 1 0

0 0 1 0

1 0 0 0

1 0 0 0

0 0 1 0

0 0 1 0

1 0 0 0

1 0 0 0

000 00 01 11 10

001

011

010

110

111

101

100

000 00 01 11 10

001

011

010

110

111

101

100

1 0

1 0

1 0

1 0

0 1

0 1

0 1

0 1

0 1 -

0 1 -

0 1 -

0 1 -

1 0 -

1 0 -

1 0 -

1 0 -

000 00 01 11 10

001

011

010

110

111

101

100

000 00 01 11 10

001

011

010

110

111

101

100

1 1 -

1 1 -

1 1 -

1 1 -

1 1 -

1 1 -

1 1 -

1 1 -

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

Fig. Combination circuit of counter

5. CONCLUSIONS In this work we construct digital counter with two operation modes: counting in direct code and counting in additional code. Controlling of modes switching is carried out by controlling signal M. M=0, direct code; M=1, additional code; The designing of circuit was done in accordance with such algorithm: - Constructing of counter operating graph. - Constructing of truth table of states. - Constructing of K-maps of JK-flip-flops - Minimization - Realization of circuit on JK-flip-flops.

6. REFERENCES 1. . ., . X., . . . - 2- ., . . - .: -, 2006. - 736 .: . 2. . ., . . +Plus 2 II. . - .:"", 2004, - 253.

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 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

K 16 10 10 16 10 16 10 10 16 10 16 10 10 16 10 16 10 10 16 10 16 10 10 16 10 16 10 10 16 10 \ \ \ \ \ 3 \ \ \ \ \ 3 \ \ \ \ \ 3 \ \ \ \ \ 3 \ \ \ \ \ 3 \ \ \ \ \ 3

. . - - DC MS - - MS DC DC MS - - MS - - DC MS - - DC - - DC MS

RS JK D T JK JK D JK RS D T JK RS JK T JK RS JK D JK RS JK D T JK RS JK D

--------DC . MS . ---------------------MS . DC . -------DC .. MS . ---------------------MS . -----------------D . MS . ---------------------------------DC .. ---------------------------------D . MS .

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