Digital Electronics Practical Course File

Practical Course File

DIGITAL ELECTRONICS

FOR

B.E (IT) 3rd Semester

Text

Course Code: IT375

PREPARED BY: Roopali Garg

Assistant Professor
ascnsxsxa
Deptt. Of IT, UIET

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IT 3rd Sem Digital Electronics

Paper Code: ITText
365 Max Marks: 50 Time: 3 Hours

List of Experiments

1.To test the truth table of all the gates of : IC 7400 (Quad NAND gates), (ii) (Hex 7404
Inverter), (iii) 7402 (NOR), (iv) 7408(AND)
2.To test the truth table of all the gates of :(i)7411(3-i/p AND) (ii) 7432(OR) (iii)
7486(EX-OR) (iv) 7410(3-i/p NAND)(v)7420(4-i/p NAND)
3.To study and realize half adder and full adder using X-OR and basic gates
4.To study and realize half and full subtractor using X-OR and basic gates
5.To design and implement multiplexer using logic gates and study of IC 74150.
6.To design and implement demultiplexer using logic gates and study of IC 74154.
7.To convert given binary numbers to gray codes.
8.To verify the truth table of one bit and four bit comparators using logic Gates and IC
7485
9.Truth table verification of Flip-Flops: (i) RS-Type (ii) D- Type
10.Truth table verification of Flip-Flops: (i) JK-Type and (ii) T-Type
11.To study shift register using IC 7495 in all its modes i.e. SIPO and SISO.
12.To study shift register using IC 7495 in all its modes i.e. PISO and PIPO.
13.To design and implement (i) Serial in serial out (ii) Serial in parallel out
14.Realization of 3-bit Asynchronous up counter and down counter design using JK flip
flop.
15.To design and Implement a 3-bit synchronous counter design.

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Table of Contents
Introduction to the course and Familiarizing with the Trainer Kit ..................................... 6
Experiment 1: Study Truth Table ..................................................................................... 12
Experiment 2: Study Truth Table ..................................................................................... 12
Experiment 3: Half Adder And Full Adder ...................................................................... 25
Experiment 4: Half And Full Subtractor........................................................................... 25
Experiment 5: Design, Implementation And Study Of Multiplexer................................. 29
Experiment 6: Design And Implementation Of Demultiplexer....................................... 29
Experiment 7: Binary To Gray Code Conversion And Gray To Binary Code Conversion
........................................................................................................................................... 36
Experiment: 8 Comparators .............................................................................................. 39
Experiment 9: Flip-Flop- RS and D.................................................................................. 41
Experiment 10: Flip-Flop-JK and T.................................................................................. 41
Experiment 11: Shift Register SIPO and SISO................................................................. 45
Experiment 12: Shift Register PISO and PIPO................................................................. 45
Experiment 13: Design And Implementation Of Shift Register....................................... 50
Experiment 14: Asynchronous Counter Design ............................................................... 53
Experiment 15: Synchronous Counter Design.................................................................. 56

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Paper Title: Digital Electronics (Practical)

Paper Code: IT 375 MM: 50

Credits: 2

Objective:
The students will be able to verify the truth table of gates; demonstrate the
operation of flip flops ; develop, test and troubleshoot the combinational
and sequential circuits.

The Laboratory Notebook:

Each student must have their own laboratory notebook. All pre-lab exercises

and laboratory reports are to be entered into your notebook.

Your notebook must be clearly labelled on the cover with the following

information:

Subject: Digital Electronics -

Name:

Class:

Group Members:

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Introduction to the course and Familiarizing with the

Trainer Kit

Introduction

There are 3 hours allocated to a laboratory session in Digital Electronics. It

is a necessary part of the course at which attendance is compulsory.

Here are some guidelines to help you perform the experiments and to submit

the reports:

1. Read all instructions carefully and carry them all out.

2. Ask a demonstrator if you are unsure of anything.

3. Record actual results (comment on them if they are unexpected!)

4. Write up full and suitable conclusions for each experiment.

5. If you have any doubt about the safety of any procedure, contact the

demonstrator beforehand.

6. THINK about what you are doing!

The Breadboard

The breadboard consists of two terminal strips and two bus strips (often

broken in the centre). Each bus strip has two rows of contacts. Each of the

two rows of contacts are a node. That is, each contact along a row on a bus

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strip is connected together (inside the breadboard). Bus strips are used

primarily for power supply connections, but are also used for any node

requiring a large number of connections. Each terminal strip has 60 rows and

5 columns of contacts on each side of the centre gap. Each row of 5 contacts

is a node.

You will build your circuits on the terminal strips by inserting the leads of

circuit components into the contact receptacles and making connections with

22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the

lab. It is a good practice to wire +5V and 0V power supply connections to

separate bus strips.

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Fig 1. The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the

ICs (Integrated circuits) used during the experiments. Incorrect connection

of power to the ICs could result in them exploding or becoming very hot -

with the possible serious injury occurring to the people working on the

experiment! Ensure that the power supply polarity and all components and

connections are correct before switching on power .

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Trainer Kit

Trainer Kit has Breadboard, Power supply (fixed and variable), Input

switches, Output LED, clock for frequency generation.

Building the Circuit

Throughout these experiments we will use TTL chips to build circuits. The

steps for wiring a circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything!

2. Make sure the power is off before you build anything!

3. Connect the +5V and ground (GND) leads of the power supply to

the power and ground bus strips on your breadboard.

4. Plug the chips you will be using into the breadboard. Point all the

chips in the same direction with pin 1 at the upper-left corner. (Pin

1 is often identified by a dot or a notch next to it on the chip

package)

5. Connect +5V and GND pins of each chip to the power and ground

bus strips on the breadboard.

6. Select a connection on your schematic and place a piece of hook-up

wire between corresponding pins of the chips on your breadboard.

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It is better to make the short connections before the longer ones.

Mark each connection on your schematic as you go, so as not to try

to make the same connection again at a later stage.

7. Get one of your group members to check the connections, before

you turn the power on.

8. If an error is made and is not spotted before you turn the power on.

Turn the power off immediately before you begin to rewire the

circuit.

9. At the end of the laboratory session, collect you hook-up wires,

chips and all equipment and return them to the demonstrator.

10.Tidy the area that you were working in and leave it in the same

condition as it was before you started.

Common Causes of Problems

1. Not connecting the ground and/or power pins for all chips.

2. Not turning on the power supply before checking the operation of

the circuit.

3. Leaving out wires.

4. Plugging wires into the wrong holes.

5. Driving a single gate input with the outputs of two or more gates

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6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads,

components at the start of the experiment and return them to their proper

place after you have finished the experiment. Please inform the demonstrator

or technician if you locate faulty equipment. If you damage a chip, inform a

demonstrator, don't put it back in the box of chips for somebody else to use.

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Experiment 1: Study Truth Table

Aim: To test the truth table of all the gates of :

(i) IC 7400 (Quad NAND gates), (ii) (Hex 7404

Inverter),

(iii) 7402 (NOR), (iv) 7408(AND)

Experiment 2: Study Truth Table

Aim: To test the truth table of all the gates of :

(i) 7411(3-i/p AND) (ii) 7432(OR)

(iii) 7486(EX-OR) (iv) 7410(3-i/p NAND)

(v) 7420(4-i/p NAND)

Build a circuit to implement the Boolean function F = /(/A./B), please note

that the notation /A refers to . You should use that notation during the

write-up of your laboratory experiments.

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Quad 2 Input 7400 Hex 7404 Inverter

Fig 2. The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small
indented circle above the first pin of the chip. Place your chips in the same

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direction, to save confusion at a later stage. Remember that you must

connect power to the chips to get them to work.

Useful IC Pin details

7400(NAND) 7402(NOR)

7404(NOT) 7408(AND)

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7411(3-i/p AND) 7432(OR)

7486(EX-OR)

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7410(3-i/p NAND) 7420(4-i/p NAND)

APPARATUS REQUIRED:

THEORY:
Circuit that takes the logical decision and the process are called logic
gates. Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are
known as universal gates. Basic gates form these gates.
AND GATE:
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The AND gate performs a logical multiplication commonly known as

AND function. The output is high when both the inputs are high. The output
is low level when any one of the inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR
function. The output is high when any one of the inputs is high. The output
is low level when both the inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the
input is low. The output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high
when both inputs are low and any one of the input is low .The output is low
level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when
both inputs are low. The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is
low when both the inputs are low and both the inputs are high.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

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OR Gate

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Result/ Observation:

…………………………………………..

Signature of the staff in charge

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Experiment 3: Half Adder And Full Adder

Aim: - To study and realize half adder and full adder using X-OR

and basic gates

Experiment 4: Half And Full Subtractor

Aim: - To study and realize half and full subtractor using X-OR

and basic gates

Apparatus Required: -

IC 7486, IC 7432, IC 7408, IC 7400, IC Trainer Kit, Patch

cords.

Procedure: -

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on VCC and apply various combinations of input according to

truth table.

4. Note down the output readings for half/full adder and half/full

subtractor sum/difference and the carry/borrow bit for different

combinations of inputs.

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Circuit Diagram:-

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Result/ Observation:

…………………………………………..

Signature of the staff in charge

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Experiment 5: Design, Implementation And Study Of

Multiplexer
AIM: To design and implement multiplexer using logic gates and
study of IC 74150.

Experiment 6: Design And Implementation Of

Demultiplexer
AIM: To design and implement demultiplexer using logic gates
and study of IC 74154.

APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC 74150 1
5. IC 74154 1
6. IC TRAINER KIT - 1
7. PATCH CORDS

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there
are 2n input line and n selection lines whose bit combination determine which input is
selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information
from one line and distributes it to a given number of output lines. For this reason, the

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demultiplexer is also known as a data distributor. Decoder can also be used as

demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data
select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

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PIN DIAGRAM FOR IC 74150:

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PIN DIAGRAM FOR IC 74154:

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:

…………………………………………..

Signature of the staff in charge

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Experiment 7: Binary To Gray Code Conversion And Gray To

Binary Code Conversion

Aim: - To convert given binary numbers to gray codes.

Apparatus Required: IC 7486, etc

Procedure: -

1. The circuit connections are made as shown in fig.

2. Pin (14) is connected to +Vcc and Pin (7) to ground.

3. In the case of binary to gray conversion, the inputs B0, B1, B2 and

B3 are given at respective pins and outputs G0, G1, G2, G3 are taken for all

the 16 combinations of the input.

4. In the case of gray to binary conversion, the inputs G0, G1, G2 and

G3 are given at respective pins and outputs B0, B1, B2, and B3 are taken for

all the 16 combinations of inputs.

5. The values of the outputs are tabulated.

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Conclusion: -

…………………………………………..

Signature of the staff in charge

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Experiment: 8 Comparators
Aim: - To verify the truth table of one bit and four bit comparators

using logic Gates and IC 7485

Apparatus Required: IC 7486, IC 7404, IC 7408, IC 7485etc.

Procedure: -

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on Vcc.

4. Applying i/p and Check for the outputs.

5. The readings of outputs should be tabulated .

Circuit diagram& truth tables:-

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Tabular column :-

Conclusion: -

…………………………………………..

Signature of the staff in charge

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Experiment 9: Flip-Flop- RS and D

Aim:- Truth table verification of Flip-Flops: (i) RS-Type

(ii) D- Type

Experiment 10: Flip-Flop-JK and T

Aim:- Truth table verification of Flip-Flops: (i) JK-Type

(ii) T-Type

Apparatus Required: IC 7400,IC 7404 etc.

Procedure: -

1. Connections are made as per circuit diagram.

2. Verify the truth table for various combinations of inputs.

Circuit Diagram& Truth table:

i)RS Flip-Flop

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Qn /Qn R S Qn+1/Qn+1

0 1 0 0

1 0 0 0

0 1 0 1

1 0 0 1

0 1 1 0

1 0 1 0

0 1 1 1

1 0 1 1

ii) D Flip-Flop

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iii) T Flip-flop

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Conclusion:-

………………………………………….

Signature of the staff in charge

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Experiment 11: Shift Register SIPO and SISO

Aim:- To study shift register using IC 7495 in all its modes i.e.

SIPO and SISO.

Experiment 12: Shift Register PISO and PIPO

Aim:- To study shift register using IC 7495 in all its modes i.e.

PISO and PIPO.

Apparatus Required: IC 7495, etc.

Procedure:-

Serial In Parallel Out(SIPO):-

1. Connections are made as per circuit diagram.

2. Apply the data at serial i/p

3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.

4. Apply the next data at serial i/p.

5. Apply one clock pulse at clock 2, observe that the data on QA will shift to

QB and the new data applied will appear at QA.

6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the

shift register.

Serial In Serial Out(SISO):-

1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.

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3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.

4. Apply another clock pulse; the second data ‘d1’ appears at QD.

5. Apply another clock pulse; the third data appears at QD.

6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at

QD. Thus the data applied serially at the input comes out serially at QD

Parallel In Serial Out (PISO):-

1. Connections are made as per circuit diagram.

2. Apply the desired 4 bit data at A, B, C and D.

3. Keeping the mode control M=1 apply one clock pulse. The data applied at

A, B, C and D will appear at QA, QB, QC and QD respectively.

4. Now mode control M=0. Apply clock pulses one by one and observe the

Data coming out serially at QD

Parallel In Parallel Out (PIPO):-

1. Connections are made as per circuit diagram.

2. Apply the 4 bit data at A, B, C and D.

3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).

4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD

respectively.

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Circuit diagram :-

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PISO:-

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Conclusion:-

………………………………………….

Signature of the staff in charge

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Experiment 13: Design And Implementation Of Shift

Register
AIM: To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
APPARATUS REQUIRED:
D FLIP FLOP (IC 7474) , OR GATE (IC 7432), IC TRAINER KIT
PATCH CORDS - 35
THEORY:
A register is capable of shifting its binary information in one or both
directions is known as shift register. The logical configuration of shift
register consist of a D-Flip flop cascaded with output of one flip flop
connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest
possible shift register is one that uses only flip flop. The output of a given
flip flop is connected to the input of next flip flop of the register. Each clock
pulse shifts the content of register one bit position to right.
PIN DIAGRAM:

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LOGIC DIAGRAM (SISO)

LOGIC DIAGRAM (SIPO)

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Conclusion:-

………………………………………….

Signature of the staff in charge

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Experiment 14: Asynchronous Counter Design

Aim: - To Design and Implement a 3-bit Asynchronous up counter

and down counter design using JK flip flop.

Apparatus Required: IC 7476, Trainer Kit, Patch Cords

Procedure: -

1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is

observed at QA, QB & QC for IC 7476.

3. Verify the Truth table .

Circuit Diagram:

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Conclusion:-

………………………………………….

Signature of the staff in charge

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Experiment 15: Synchronous Counter Design

Aim: - To design and Implement a 3-bit synchronous counter design.

Apparatus Required: IC 7408, IC 7476, IC 7400, IC 7432 , IC Trainer

Kit, Patch Cords etc.

Procedure: -
1. Connections are made as per circuit diagram.
2. Clock pulses are applied one by one at the clock I/P and the O/P is
observed at QA, QB & QC for IC 7476.
3. Verify the Truth table .
Circuit Diagram& Truth table:

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Truth table :-

Conclusion:-

………………………………………….

Signature of the staff in charge

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