1.

Computational Architecture (Computer Architecture)

Definition:​
Computer architecture refers to the conceptual design and fundamental operational structure of a
computer system. It focuses on the structure and behavior of the computer as seen by the
programmer — including the instruction set, data types, addressing modes, registers, and
input/output mechanisms.

Key Components:

●​ Instruction Set Architecture (ISA)​

●​ Data representation (binary, signed/unsigned, etc.)​

●​ Memory addressing modes​

●​ I/O operations​

●​ Machine language instructions​

Examples:

●​ x86 Architecture: A complex instruction set computer (CISC) used in most PCs.​

●​ ARM Architecture: A reduced instruction set computer (RISC) used in mobile devices.​

●​ MIPS Architecture: Common in embedded systems and educational environments.​

2. Computational Organization (Computer Organization)

Definition:​
Computer organization refers to the operational units and their interconnections that realize the
architecture's specifications. It deals with the implementation details — how hardware components
such as the CPU, memory, and I/O devices work together to execute programs.

Key Components:

●​ Control Unit​

●​ ALU (Arithmetic Logic Unit)​

●​ Registers​

1
 ●​ Cache memory​

●​ Data paths and buses​

●​ Hardware-level timing and signal control​

Examples:

●​ How pipelining is implemented in a processor.​

●​ The number of clock cycles required per instruction.​

●​ The organization of cache memory and memory hierarchy.​

●​ Use of microprogramming in control units.​

3. Difference Between Computational Architecture and Organization

Feature Computational Architecture Computational Organization

Focus Functional behavior as seen by a Physical and operational structure of

programmer components

Concerned with Instruction sets, data types, Control signals, buses, hardware
memory addressing implementation

Level of High (software-level view) Low (hardware-level view)

Abstraction

Influences Programming model and compiler Performance, cost, and physical

design design

Example x86, ARM instruction set Pipeline structure, cache memory

layout

Users System programmers, compiler Computer engineers, hardware

developers designers

Control Signals

Control signals are electrical signals used in a computer system to coordinate and manage the
actions of its components (like CPU, memory, and I/O devices). They are generated by the control
unit of the processor and are essential for executing instructions correctly.

2
🔧 Purpose of Control Signals
●​ Direct data flow between components (e.g., memory to register)​

●​ Enable or disable writing/reading operations​

●​ Select the operation to be performed by the ALU​

●​ Manage communication with I/O devices​

🧠 Examples of Control Signals

Control Signal Function

READ Enables reading data from memory

WRITE Enables writing data to memory

ALU Operation Specifies the operation to be performed (e.g., add,

subtract)

Register Select Selects which register to read/write

Memory Enable Activates memory access

I/O Enable Activates communication with I/O devices

Functional Units of a Computer

A computer system is made up of several functional units, each responsible for performing specific
tasks during data processing. These units work together to fetch, process, store, and output data.

🔹 1. Input Unit
Function: Accepts data and instructions from the user and converts them into a form the computer
can understand (binary).

●​ Examples: Keyboard, mouse, scanner​

●​ Role: Interface between the user and the system​

3
🔹 2. Memory Unit
Function: Stores data, instructions, and results.

Types:

●​ Primary Memory:​

○​ RAM (Random Access Memory): Temporary storage for currently used

data/programs.​

○​ ROM (Read-Only Memory): Permanent storage for startup programs (e.g., BIOS).​

●​ Secondary Memory:​

○​ Hard disk, SSD, CD/DVD: Permanent storage.​

🔹 3. Arithmetic and Logic Unit (ALU)

Function: Performs all arithmetic (addition, subtraction, etc.) and logic (comparison, AND, OR, etc.)
operations.

●​ Works with the control unit to execute operations.​

●​ Temporary results are stored in registers.​

🔹 4. Control Unit (CU)

Function: Directs and coordinates the operations of all other units.

●​ Interprets instructions from memory.​

●​ Sends control signals to other components.​

●​ Does not process or store data directly.​

🔹 5. Output Unit
Function: Converts binary results from the computer into human-readable form.

4
 ●​ Examples: Monitor, printer, speaker​

●​ Role: Displays processed data or results to the user.​

🔹 6. Central Processing Unit (CPU)

Function: The brain of the computer, responsible for processing instructions.

●​ Includes: ALU + Control Unit​

●​ Communicates with memory and I/O devices​

●​ Executes instructions sequentially or conditionally

System Bus in Computer Organization

🧠 Definition:
A System Bus is a communication pathway that connects the major components of a computer
system, such as the CPU, memory, and input/output devices. It allows data and control signals to
be transmitted between them.

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Think of it as the "nervous system" of a computer that carries information back and forth.

📦 Main Components of the System Bus:

The system bus is typically divided into three types of buses:

Type of Bus Description

1. Data Bus Transfers actual data between CPU, memory, and I/O.

2. Address Carries the address (location in memory or I/O) where data is to be

Bus read/written.

3. Control Carries control signals from the control unit (e.g., Read, Write, Interrupt,
Bus Clock).

🔁 How It Works (Step-by-step)

1.​ CPU issues an address on the address bus.​

2.​ Control signals (like Read/Write) are sent on the control bus.​

3.​ The required data is transferred on the data bus.​

4.​ I/O or memory responds accordingly.​

📊 Explanation of Each Bus:

1. Data Bus

●​ Bidirectional (CPU can read from or write to memory)​

●​ Width (e.g., 8-bit, 16-bit, 32-bit, 64-bit) determines how much data can be transferred at once.​

2. Address Bus

●​ Unidirectional (CPU → memory/I/O)​

●​ The number of lines determines maximum addressable memory.​

Example: 16 address lines → 2¹⁶ = 65,536 memory locations​

6
3. Control Bus

●​ Sends timing and control signals like:​

○​ READ / WRITE​

○​ Memory Enable​

○​ I/O Enable​

○​ Clock​

○​ Interrupt requests​

📌 Diagram (Text Form):

+--------+ +---------+ +---------+
| CPU | <======> | Memory | <=====> | I/O Dev |
+--------+ +---------+ +---------+
↑ ↑ ↑ ↑
| |__________________|___________________|
| System Bus (Data + Address + Control)

🖥️ Example in Action:
CPU wants to read data from memory:

1.​ Places address on address bus​

2.​ Sends READ signal on control bus​

3.​ Memory places data on data bus​

4.​ CPU reads data​

✅ Advantages of System Bus:

●​ Simplifies interconnection between components​

7
 ●​ Reduces hardware complexity​

●​ Cost-effective and scalable​

⚠️ Limitations:
●​ Bus contention: Multiple devices may want to use the bus simultaneously​

●​ Speed bottleneck: Shared bus limits performance compared to dedicated connections​

Synchronous Bus Data Transfer

Definition:​
In synchronous bus data transfer, all devices on the bus share a common clock signal. Data
transfer between devices (like CPU and memory) happens in fixed time intervals (clock cycles), and
all actions are coordinated based on this clock.

🧠 Key Features:
●​ Uses a clock line to synchronize all operations​

●​ Sender and receiver both operate in sync with the clock​

●​ Faster and simpler than asynchronous transfer (but less flexible)​

📦 How It Works (Steps):

1.​ Clock signal starts the cycle​

2.​ CPU places an address and control signal on the bus​

3.​ After a fixed delay (based on the clock), data is placed or read​

4.​ All devices act based on the same clock timing​

8
📊 Diagram: Synchronous Bus Data Transfer

Asynchronous Bus Data Transfer

Definition:​
In asynchronous bus data transfer, data is transmitted without a common clock signal. Instead,
devices use control signals (handshaking) to manage when data is sent and received. Each device
communicates at its own speed.

🔧 How It Works (Handshaking Mechanism)

The transfer typically uses two control lines:

1.​ Request (REQ) – Initiated by the sender to indicate data is ready​

2.​ Acknowledge (ACK) – Sent by the receiver to confirm data receipt​

🔁 Steps in Asynchronous Transfer:

1.​ The sender places data on the data bus.​

2.​ The sender sends a Request signal to the receiver.​

3.​ The receiver reads the data.​

4.​ The receiver sends an Acknowledge signal back.​

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 5.​ The sender removes data and resets the control lines.​

🧠 Key Features:
●​ No global clock required​

●​ Devices can operate at different speeds​

●​ Uses handshaking protocol​

📦 Example: CPU Writing to an I/O Device

Imagine a CPU sends a value to a printer:

1.​ CPU places data on the data bus​

2.​ CPU sends REQ = 1​

3.​ Printer receives data and sends back ACK = 1​

4.​ CPU resets REQ = 0, and printer resets ACK = 0​

📊 Advantages:
●​ More flexible, supports devices of varying speeds​

●​ Ideal for I/O devices​

⚠️ Disadvantages:
●​ More complex than synchronous transfers​

●​ Requires extra control lines and logic

Difference Between Synchronous and Asynchronous Bus

Feature Synchronous Bus Asynchronous Bus

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 Clock Signal Uses a common clock signal to No global clock; uses handshaking
coordinate transfer (REQ/ACK) signals

Timing Transfers occur at fixed Transfers occur when devices are

intervals (clock cycles) ready

Speed All devices must operate in sync Devices operate at their own speed
Coordination with the clock

Control Lines Needs a clock line Needs Request and Acknowledge

lines

Implementation Simpler but less flexible More complex but more flexible

Device Slower devices may cause Better suited for devices with
Compatibility bottlenecks variable speeds

Performance Can be faster in uniform Better in heterogeneous or

systems mixed-speed systems

Example Use CPU ↔ RAM communication CPU ↔ I/O devices (keyboard,

printer, etc.)

Instruction Cycle (or Machine Cycle)

📌 Definition:
An Instruction Cycle is the complete process by which a computer fetches, decodes, and
executes a single instruction from memory. It is repeated continuously by the CPU for every
instruction in a program.

🔁 Phases of Instruction Cycle:

Phase Function

1. Fetch CPU fetches the instruction from memory (address in Program Counter
- PC)

2. Decode The Control Unit decodes the instruction to understand what to do

3. Execute The instruction is executed using ALU, registers, or I/O devices

4. Store Result is stored in memory or a register, if needed

(optional)

🖥️ Example:
11
Let’s consider the instruction:

assembly
CopyEdit
ADD R1, R2, R3 ; R1 ← R2 + R3

1.​ Fetch: Get the ADD instruction from memory​

2.​ Decode: Identify operation as ADD and operands R2 and R3​

3.​ Execute: ALU performs addition of R2 and R3​

4.​ Store: Result is stored in register R1​

✅ Types of Instructions (Instruction Format/Data Types)

Instructions are usually classified based on the type of operation they perform.

Instruction Type Purpose Example

1. Data Transfer Move data between memory and MOV R1, 1000 (move value at
registers 1000 to R1)

2. Arithmetic Perform arithmetic operations ADD R1, R2 (R1 ← R1 + R2)

3. Logical Perform logical operations like AND, AND R1, R2

OR, NOT

4. Change the flow of execution JMP 2000 (jump to address

Control/Branch 2000)

5. I/O Interact with input/output devices IN R1, PORT1

Instructions

6. Compare/Test Compare values or set flags CMP R1, R2

📊 Explanation of Each:
1.​ Data Transfer – Moves data without processing.​

2.​ Arithmetic – Adds, subtracts, multiplies, etc.​

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 3.​ Logical – Performs bitwise operations.​

4.​ Control – Used for loops, conditionals, etc.​

5.​ I/O – Handles communication with peripheral devices.​

6.​ Compare – Sets status flags used in decision-making.​

Instruction Set (in Computer Organization)

Definition:​
An Instruction Set is a group of binary-coded commands (instructions) that a computer’s CPU
can execute directly. These instructions tell the CPU what operations to perform, such as arithmetic,
data movement, logic, control flow, etc.

🔹 Examples of Instructions:
●​ ADD R1, R2 – Add contents of R1 and R2​

●​ MOV R1, 1000 – Move the value at address 1000 into register R1​

●​ JMP 2000 – Jump to memory address 2000​

●​ LOAD R3, [R1] – Load data from memory into register​

Every processor has its own specific instruction set. For example:

●​ Intel x86 instruction set​

●​ ARM instruction set​

●​ MIPS instruction set​

✅ Instruction Set Architecture (ISA)

Definition:​
An Instruction Set Architecture (ISA) is the interface between software and hardware. It specifies
the set of instructions, data types, registers, memory addressing modes, and input/output
operations that a processor supports.

Think of ISA as the blueprint that tells how software interacts with the processor.

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🔹 Example of ISA:
Let’s consider the MIPS ISA:

●​ Instruction Format: Fixed 32-bit instruction length​

●​ Registers: 32 general-purpose registers​

●​ Instructions: R-type (register), I-type (immediate), J-type (jump)​

●​ Operations: ADD, SUB, LW, SW, JMP, BEQ, etc.​

🔄 In short:
Term Description

Instruction Set The actual set of binary commands the CPU understands

ISA The complete specification (instructions, registers, formats,

addressing)

Components of Instruction Set Architecture (ISA)

An Instruction Set Architecture (ISA) is the blueprint that defines how a computer's hardware and
software interact. It provides all the essential details required to write and execute machine-level
programs.

Below are the main components of ISA, along with their explanations and examples:

🔹 1. Instruction Format
Definition: Specifies how an instruction is encoded in binary — i.e., how the bits of an instruction are
divided into meaningful fields.

🔧 Typical Fields:
●​ Opcode: Operation code (e.g., ADD, LOAD)​

●​ Operands: Registers or memory addresses​

●​ Mode Bits: Define addressing mode​

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 ●​ Immediate values: Constants encoded directly​

📌 Example (32-bit RISC instruction):

java
CopyEdit
| Opcode (6) | Source Reg (5) | Target Reg (5) | Dest Reg (5) | Shamt (5) |
Funct (6) |

🔹 2. Instruction Types
Definition: Categories of operations supported by the ISA.

Type Purpose Example

Data Transfer Move data between registers/memory MOV, LOAD, STORE

Arithmetic/Logic Perform calculations and ADD, SUB, AND, OR

comparisons

Control Change program flow JMP, CALL, RET,

BRANCH

I/O Instructions Interface with external devices IN, OUT

🔹 3. Addressing Modes
Definition: Methods used to specify the location of an operand.

Mode Description Example

Immediate Operand is part of the instruction ADD R1, R2,

#5

Register Operand is in a register MOV R1, R2

Direct Address of operand is in instruction LOAD R1, 1000

Indirect Address is in a register LOAD R1, [R2]

Indexed Base address + offset LOAD R1,

1000(R2)

🔹 4. Data Types 15
Definition: Specifies the kinds and sizes of data supported by the ISA.

Common Data Types:

●​ Integer (8, 16, 32, 64 bits)​

●​ Floating Point (32-bit float, 64-bit double)​

●​ Character (ASCII, Unicode)​

●​ Boolean (true/false or 0/1)​

🔹 5. Registers
Definition: ISA defines a set of registers accessible to programmers.

Register Type Purpose

General Purpose Temporary storage, arithmetic operations

(GPR)

Special Purpose PC (Program Counter), SP (Stack Pointer), IR (Instruction

Register), Flags

📌 Example: MIPS has 32 general-purpose registers: $t0 – $t9, $s0 – $s7, etc.

🔹 6. Memory Architecture
Definition: Describes how memory is structured and accessed in the system.

●​ Byte vs Word Addressable: Whether each memory address refers to a byte or word.​

●​ Memory Model: Flat or segmented​

●​ Endianness: Little-endian vs Big-endian​

🔹 7. I/O Mechanism
Definition: Specifies how the CPU communicates with external devices.

Type Description
16
 Memory-Mapped I/O Devices use memory address space

Isolated I/O Devices use a separate I/O address

space

📊 Summary Table: Components of ISA

Component Description

Instruction Format Layout of bits in an instruction

Instruction Types Categories like data transfer, arithmetic, control, I/O

Addressing Modes Ways to reference data (immediate, direct, indirect,

etc.)

Data Types Types and sizes of data (int, float, char, etc.)

Registers Number and type of CPU registers

Memory Architecture How memory is organized and accessed

I/O Mechanism How CPU communicates with external devices

Types of Instruction Set Architecture (ISA)

Instruction Set Architectures are categorized based on how instructions are formatted and how
operands are specified. The main types are:

🔹 1. Stack-Based ISA
Definition: Operands are implicitly taken from the top of the stack, and results are pushed back.

●​ No need to specify operand locations in instruction.​

●​ Uses a stack data structure.​

📌 Example:
asm
CopyEdit
PUSH 5 ; Push 5 onto stack
PUSH 7 ; Push 7 onto stack
ADD ; Add top two values → result pushed

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✅ Used In:
●​ JVM (Java Virtual Machine)​

●​ Forth language​

🔹 2. Accumulator-Based ISA
Definition: One operand is in a special register called the accumulator, and the other is from
memory.

●​ Instructions are typically shorter.​

●​ Limited flexibility due to single accumulator.​

📌 Example:
asm
CopyEdit
LOAD A ; Load value from memory A into accumulator
ADD B ; Add value from memory B to accumulator
STORE C ; Store result in memory C

✅ Used In:
●​ Early computers (e.g., Intel 8080)​

🔹 3. Register-Memory ISA
Definition: One operand is in a register and the other in memory.

●​ Mixes access types.​

●​ Reduces number of memory accesses compared to accumulator-based ISAs.​

📌 Example:
asm
CopyEdit
ADD R1, M1 ; Add value at memory M1 to register R1

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✅ Used In:
●​ Intel x86 architecture​

🔹 4. Register-Register (Load/Store) ISA

Definition: All operands must be in registers. Memory is accessed only through explicit load and
store instructions.

●​ Simple instruction format​

●​ Uniform performance​

📌 Example (MIPS):
asm
CopyEdit
LOAD R1, A ; Load value from memory A into R1
LOAD R2, B ; Load value from memory B into R2
ADD R3, R1, R2 ; Add R1 and R2, store result in R3
STORE R3, C ; Store result to memory C

✅ Used In:
●​ MIPS, RISC-V, ARM (modern RISC processors)​

🔹 5. Hybrid ISA
Definition: Combines features of register-memory and load/store architectures.

●​ More flexible​

●​ Complex implementation​

✅ Used In:
●​ x86-64 (combines register-register, register-memory, and accumulator types)​

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📊 Summary Table
ISA Type Operand Location Example Instruction Example System

Stack-Based Implicit (stack) ADD Java VM, Forth

Accumulator-Base Accumulator + memory ADD B Intel 8080

d

Register-Memory Register + memory ADD R1, M1 x86

Register-Register Only registers ADD R3, R1, R2 MIPS, ARM, RISC-V

Hybrid Mix of above MOV AX, [BX] x86-64

Instruction Cycle in Computer Organization

The Instruction Cycle (also called Fetch-Decode-Execute cycle) is the basic operation cycle of a
computer, where the CPU fetches an instruction from memory, decodes it to understand what to do,
and then executes it.

🔄 Phases of Instruction Cycle

1.​ Fetch​

○​ Purpose: Retrieve the next instruction from memory.​

○​ How:​

■​ The Program Counter (PC) holds the address of the next instruction.​

■​ The address is sent to memory and the instruction is fetched into the
Instruction Register (IR).​

■​ PC is incremented.​

2.​ 🧠 Example: Fetch instruction from memory address 1000.​

​

2.​ Decode​

○​ Purpose: Understand what the instruction wants to do.​

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 ○​ How:​

■​ The Control Unit (CU) interprets the opcode in the IR.​

■​ It identifies the operation and the operands (registers or memory locations).​

3.​ 🧠 Example: Instruction ADD R1, R2 is decoded to perform addition of R1 and R2.​
​

3.​ Execute​

○​ Purpose: Perform the operation defined by the instruction.​

○​ How:​

■​ ALU performs arithmetic/logical operations.​

■​ Memory is accessed if needed.​

■​ Registers are updated.​

4.​ 🧠 Example: ALU adds contents of R1 and R2 and stores result in R1.​
​

4.​ Memory Access (If Needed)​

○​ Some instructions require reading or writing from memory (e.g., LOAD, STORE).​

5.​ Write-back (If Needed)​

○​ The result of the operation is written back to a register or memory location.​

🔁 Cycle Repeats
Once one instruction completes, the next instruction is fetched using the updated PC.

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📘 Example:
For the instruction:

asm
CopyEdit
ADD R1, R2

●​ Fetch: Get ADD R1, R2 from memory to IR.​

●​ Decode: Identify ADD as the operation, R1 and R2 as operands.​

●​ Execute: Perform R1 = R1 + R2.​

📊 Summary Table
Phase Description Key Elements Used

Fetch Get instruction from memory PC, MAR, MDR, IR

Decode Interpret the instruction Control Unit

Execute Perform the action ALU, Registers, Memory

Memory Read/write data (if instruction needs it) MAR, MDR

Writeback Store result Registers or memory

Interrupt in Computer Organization

An interrupt is a signal sent to the processor that temporarily stops the current program
execution, so the CPU can respond to an urgent task or event. Once the interrupt is handled, the
CPU resumes the original program.

🔹 Purpose of Interrupts
Interrupts are used to:

●​ Improve CPU efficiency​

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 ●​ Respond quickly to real-time events (like input/output)​

●​ Allow multitasking and asynchronous operations​

🔹 Common Sources of Interrupts

Type Description Example

Hardware Triggered by hardware devices Keyboard press, mouse

click

Software Generated by a running program Division by zero, syscall

Timer Issued by internal timer to manage multitasking OS task switching

I/O Notifies completion of I/O operation Disk read complete

🔹 Steps in Handling an Interrupt

1.​ CPU stops current execution.​

2.​ Saves the current state (program counter, registers).​

3.​ Jumps to a special routine called Interrupt Service Routine (ISR).​

4.​ Executes ISR to handle the event.​

5.​ Restores saved state and resumes original task.​

📘 Real-World Analogy
Imagine you're writing notes, and your phone rings:

●​ You pause writing (main program),​

●​ Answer the call (interrupt service routine),​

●​ Then return to writing exactly where you left off.​

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✅ Instruction Cycle with Interrupt in Computer Organization
The Instruction Cycle describes how the CPU fetches, decodes, and executes instructions. When
interrupts are introduced, the cycle is enhanced to allow the CPU to respond to external or internal
events.

🔄 Phases of Instruction Cycle with Interrupts

🔹 1. Fetch
●​ The Program Counter (PC) holds the address of the next instruction.​

●​ This instruction is fetched from memory and stored in the Instruction Register (IR).​

●​ PC is incremented.​

🔹 2. Decode
●​ The Control Unit (CU) decodes the instruction to determine the operation and the operands.​

🔹 3. Execute
●​ The Arithmetic Logic Unit (ALU) or other parts of the CPU execute the decoded instruction.​

●​ If the instruction is a memory operation, it may involve reading/writing data.​

🔹 4. Interrupt Check (New Step)

●​ After each instruction is executed, the CPU checks if any interrupt signal is pending.​

●​ If no interrupt, go back to fetch the next instruction.​

●​ If interrupt occurs, the CPU performs the interrupt cycle.​

🚨 Interrupt Cycle
If an interrupt is detected:

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 1.​ Save the current program state (PC, flags, registers) onto the stack.​

2.​ Load the address of the appropriate Interrupt Service Routine (ISR) into the PC.​

3.​ Execute ISR to handle the interrupt.​

4.​ After ISR execution, restore the saved state.​

5.​ Resume normal instruction execution from where it was interrupted.​

📘 Example Scenario
Let's say the CPU is executing:

asm
CopyEdit
ADD R1, R2

While executing this, a keyboard interrupt occurs.

●​ CPU finishes ADD R1, R2​

●​ Checks interrupt line and finds a keyboard interrupt​

●​ Saves current PC and registers​

●​ Jumps to keyboard ISR (e.g., store keystroke)​

●​ After ISR, CPU restores PC and registers​

●​ Continues with next instruction in program​

🔁 Modified Instruction Cycle Diagram (Textual)

pgsql
CopyEdit
+-------------------------+
| Start / Reset |
+------------+------------+
|

25
 v
+----------+----------+
| Fetch Instruction |
+----------+----------+
|
v
+----------+----------+
| Decode Instruction |
+----------+----------+
|
v
+----------+----------+
| Execute Instruction |
+----------+----------+
|
v
+---------------+----------------+
| Check for Interrupt? (Yes/No) |
+---------------+----------------+
| |
| No | Yes
v v
+---------+--------+ +--------+----------+
| Fetch Next | | Save PC, Flags, |
| Instruction | | and Registers |
+-------------------+ +--------+----------+
|
v
+-----------+-----------+
| Execute ISR |
+-----------+-----------+
|
v
+-----------+-----------+
| Restore PC and Flags |
+-----------+-----------+
|
v
+-----------+-----------+
| Resume Normal Program |
+-----------------------+

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✅ Summary
Phase Description

Fetch Get instruction from memory

Decode Interpret the instruction

Execute Perform the operation

Interrupt Check Check for pending interrupt after each instruction

Interrupt Cycle Handle interrupt by saving state, executing ISR, and restoring
state

Stages of the Instruction Cycle (in Computer Organization)

The instruction cycle refers to the steps the CPU performs to execute a single machine-level
instruction. Each instruction goes through several stages from fetching to executing and storing the
result.

🔄 Main Stages of the Instruction Cycle

Stage Description

1. Fetch Retrieve instruction from memory.

2. Decode Interpret the instruction’s meaning and operands.

3. Execute Perform the operation (e.g., arithmetic, logical, data transfer).

4. Memory Access Read/write data from/to memory if required by instruction.

5. Write-back Store the result of execution into the destination

(register/memory).

6. Interrupt Check Check and respond to any interrupts before the next cycle.
(optional)

🔍 1. Fetch Stage
●​ The Program Counter (PC) holds the address of the next instruction.​

27
 ●​ This address is sent to memory via the Memory Address Register (MAR).​

●​ The Memory Data Register (MDR) receives the instruction from memory.​

●​ Instruction is placed in the Instruction Register (IR).​

●​ PC is incremented to point to the next instruction.​

📌 Purpose: To bring the instruction from memory to CPU.

🔍 2. Decode Stage
●​ The Control Unit (CU) decodes the instruction in IR.​

●​ Identifies:​

○​ Opcode (type of operation)​

○​ Operands (registers, memory address, etc.)​

○​ Addressing mode​

📌 Purpose: To interpret what action the instruction demands.

🔍 3. Execute Stage
●​ The Arithmetic Logic Unit (ALU) or other components carry out the operation:​

○​ Arithmetic or logic (e.g., ADD, AND)​

○​ Data transfer (e.g., LOAD, STORE)​

○​ Branching (e.g., JMP, CALL)​

📌 Purpose: To perform the actual work indicated by the instruction.

🔍 4. Memory Access Stage

●​ If the instruction needs to access memory (e.g., LOAD, STORE), the CPU:​

28
 ○​ Sends address to MAR​

○​ Reads or writes data to memory using MDR​

📌 Purpose: To move data between memory and CPU.

🔍 5. Write-back Stage
●​ The result from ALU or memory is stored into the appropriate register or memory location.​

●​ Ensures the CPU state is updated correctly.​

📌 Purpose: To save the outcome of execution for future use.

🔍 6. Interrupt Check (Optional Stage)

●​ After each instruction, CPU checks for pending interrupts.​

●​ If found:​

○​ Save current state (PC, flags)​

○​ Jump to Interrupt Service Routine (ISR)​

○​ After ISR, resume original program​

📌 Purpose: To handle external/internal events (e.g., input devices, timers).

📘 Example Instruction:
asm
CopyEdit
ADD R1, R2

Stages:

●​ Fetch: Load ADD R1, R2 from memory to IR.​

●​ Decode: CU identifies ADD and registers R1, R2.​

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 ●​ Execute: ALU performs R1 = R1 + R2.​

●​ Write-back: Result is stored in R1.​

📊 Summary Table
Stage Component Used Action

Fetch PC, MAR, MDR, IR Get instruction from memory

Decode CU Understand opcode and

operands

Execute ALU, CU, Registers Perform operation

Memory Access MAR, MDR, Memory Load or store data

Write-back Register File, Memory Save result

Interrupt ISR, Stack, PC Handle external/internal event

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