MEENAKSHI RAMASWAMY

ENGINEERING COLLEGE

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING(AIML)

CS3351– DIGITAL PRINCIPLES AND

COMPUTER ORGANIZATION

Question Bank

PREPARED BY,
Mrs. R.RADHALAKSHMI, AP/ECE.
 SYLLABUS

CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION L T P C

3024
COURSE OBJECTIVES:
 To analyze and design combinational circuits.
 To analyze and design sequential circuits
 To understand the basic structure and operation of a digital computer.
 To study the design of data path unit, control unit for processor and to familiarize with the
hazards.
 To understand the concept of various memories and I/O interfacing.

UNIT I COMBINATIONAL LOGIC 9

Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder –
Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers -
Demultiplexers

UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9

Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of

FF, Analysis and design of clocked sequential circuits – Design – Moore/Mealy models, state
minimization, state assignment, circuit implementation - Registers – Counters.
UNIT III COMPUTER FUNDAMENTALS 9

Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands
of Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory Location,
Address and Operation – Instruction and Instruction Sequencing – Addressing Modes, Encoding
of Machine Instruction – Interaction between Assembly and High Level Language.
UNIT IV PROCESSOR 9

Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
Microprogrammed Control – Pipelining – Data Hazard – Control Hazards. 67

UNIT V MEMORY AND I/O 9

Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial
Interface – Interrupt I/O – Interconnection Standards: USB, SATA
45 PERIODS

PRACTICAL EXERCISES: 30 PERIODS

1. Verification of Boolean theorems using logic gates.
2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture

COURSE OUTCOMES:
At the end of this course, the students will be able to:
CO1 : Design various combinational digital circuits using logic gates
CO2 : Design sequential circuits and analyze the design procedures
CO3 : State the fundamentals of computer systems and analyze the execution of an instruction
CO4 : Analyze different types of control design and identify hazards
CO5 : Identify the characteristics of various memory systems and I/O communication
TOTAL: 75 PERIODS
TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog
HDL, VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.

REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization
and Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for Performance”,
Tenth Edition, Pearson Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
UNIT I COMBINATIONAL LOGIC 9
Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder – Subtractor –
Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers - Demultiplexers
.

PART – A
CO Mapping : CO202.1
S. Question Blooms Competenc PO
N Taxanomy e
o. Level
1 Find the Octal equivalent of the hexadecimal number
PO1, PO2,
DC.BA. (May/June 2016) BTL-5 Evaluating
PO3
2 What is meant by multilevel gates networks?(May/June BTL-1 Rememberi PO1
2016) ng

3 Discuss the NOR operation with a truth table. BTL-1 Rememberi PO1
(Nov./Dec. 2015) ng

4 Write short notes on weighted binary codes. (Nov./Dec. BTL-1 Rememberi PO1
2015) ng

5 Convert (126)10 to Octal number and binary number. BTL-1 Rememberi PO1
(Nov./Dec. 2015) ng
6 Prove the following using Demorgan’ theorem [(X+Y)’+ BTL-1 Rememberi PO1
(X+Y)’]’= X+Y (May 2015) ng

7 Convert (0.6875)10 to binary. (May 2015) BTL-1 Rememberi PO1

ng
8 Implement AND gate using only NOR gate (December BTL-1 Rememberi PO1
2014) ng

9 State the principle of duality (December 2014) BTL-1 Rememberi PO1

ng
10 State and prove the consensus theorem. (June 2014) BTL-1 Rememberi PO1
ng
11 Find the octal equivalent of hexadecimal numbers BTL-1 Rememberi PO1
AB.CD. (June 2014) ng

12 Realize XOR gate using only 4 NAND gates. (Dec 2013) Understan
BTL-2 PO1, PO2
ding
13 Realize JK flip flop using D flip flop. (Dec 2013) BTL-1 Rememberi PO1
ng
14 Convert the following hexadecimal numbers into BTL-1 Rememberi PO1
 decimal numbers: ( Dec 2012) ng
a)263, b)1C3
15 What is the significance of BCD code. ( Dec 2012) BTL-1 Rememberi PO1
ng
16 Simplify the expression: X = (A’+B)(A+B+D)D’. BTL-1 Rememberi PO1
ng
17 Convert (11001010)2 into gray code. BTL-1 Rememberi PO1
ng
b) Convert a Gray code 11101101 into binary code.

18 State & prove De-Morgan’s theorem. BTL-1 Rememberi PO1

ng
19 Describe the canonical forms of the Boolean function. BTL-1 Rememberi PO1
ng
20 Describe the importance of don’t care conditions. BTL-1 Rememberi PO1
ng
21 What is a prime implicant? BTL-1 Rememberi PO1
ng

22 Define the following: minterm and maxterm? BTL-1 Rememberi PO1

ng
23 Minimize the function using K-map: F=∑m(1,2,3,5,6,7). BTL-1 Rememberi PO1
ng
24 Define Karnaugh map. BTL-1 Rememberi PO1
ng

25 Plot the expression on K-map: F (w,x,y) =∑m (0, 1, 3, 5, BTL-1 Rememberi PO1
6) + d (2, 4). ng

26 Express x + yz as the sum of minterms BTL-1 Rememberi PO1

ng
27 Simplify: a) Y = AB’D + AB’D’ b) Z = (A’+B)(A+B). BTL-1 Rememberi PO1
ng
28 What are Universal Gates? Why are they called so? BTL-1 Rememberi PO1
ng

29 Implement OR using NAND only. BTL-1 Rememberi PO1

ng
30 Implement NOR using NAND only. BTL-1 Rememberi PO1
ng

PART B
1 Reduce the expression using Quine McCluskey's method PO1,
F(x1, x2, x3, x4, x5) = ∑m (0, 2, 4, 5, 6, 7, 8, 10, 14, 17, 18, BTL-6 PO2,
Creating
21, 29, 31) + ∑d (11, 20, 22) (May/June 2016) PO3,
PO4
2 Simplify the following switching functions using Quine
PO1,
McCluskey's tabulation method and realize expression
PO2,
using gates F(A,B,C,D) = Σ(0,5,7,8,9,10, 11, 14,15). BTL-5 Evaluating
PO3,
(Nov/Dec 2015) PO4
3 Simplify the following switching functions using Karnaugh BTL-1 Remembering PO1
map method and realize expression using gates F(A,B,C,D)
= Σ(0,3,5,7,8,9,10,12,15). (Nov/Dec 2015)

4 (a) Express the following function in sum of min-terms and

product of max-terms F(X,Y,Z)=X+YZ (May 2015)

(b) convert the following logic system into NAND gates

only. (May 2015)
PO1,
PO2,
BTL-5 Evaluating
PO3,
PO4

5 Simply the following Boolean expression in (i) sum of PO1,

product (ii) product of sum using k-map PO2,
BTL-5 Evaluating
AC’+B’D+A’CD+ABCD (May 2015) PO3,
PO4
6 Simplify the Boolean function in SOP and POS
F(A,B,C,D)=∑m(0,1,2,5,8,9,10) (Dec2014)
PO1,
(ii) plot the following Boolean function in k-map and PO2,
BTL-5 Evaluating
simplify it. F(w,x,y,z) = ∑m(0,1,2,4,5,6,8,9,12,13,14). PO3,
(Dec2014) PO4

7 Simply the function F(w,x,y,z)= ∑m(2,3,12,13,14,15) using PO1,

tabulation method .Implement the simplified using gates. PO2,
BTL-5 Evaluating
(Dec2014) PO3,
PO4
8 Minimize the expression using quineMccluskey(tabulation) PO1,
F=∑m(0,1,9,15,24,29,30) +∑d(8,11,31). method (June PO2,
BTL-6 Creating
2014) PO3,
PO4
9 Simplify the following functions using K-map technique BTL-5 Evaluating PO1,
PO2,
 (June 2014)
PO3,
G=∑m (0,1,3,7,9,11) (ii)
PO4
f(w,x;y,z)=∑m(0,7,8,9,10,12)+∑d(2,5,13).

10 Simplify the given boolean function in POS form using K-

map and draw the logic diagram using Only NOR gates
F(A,B,C,D)= ∑m (0,1,4,7,8,10,12,15)+d(2,6,11,14).
PO1,
(Dec2013)
PO2,
BTL-5 Evaluating
ii)Convert 78.510 into binary. PO3,
PO4
iii)Find the dual and complement of the following Boolean
expression Xyz’+x’yz+z(xy+w).

11 3.Simplify the Boolean function using QuineMcCluskey method:

PO1,
PO2,
F (A, B, C, D,E) = ∑m (0,1,3,7,13,14,21,26,28) + BTL-5 Evaluating
PO3,
∑d(2,5,9,11,17,24) (Dec 2013) PO4
12 Reduce the following function using K-map technique. (Dec
2012) PO1,
PO2,
BTL-5 Evaluating
i) f (A, B, C) = ∑m (0,1,3,7) + ∑d (2,5) PO3,
PO4
ii) F (w,x,y,z) = ∑m (0,7,8,9,10,12) + ∑d (2,5,13)
13 Simlify the following Boolean function F using Tabulation
method.
i) F (A, B, C, D) = ∑m (0,6,8,13,14) ,d (A, B, C, D)= ∑m PO1,
(2,4,10) (Dec 2012) PO2,
BTL-5 Evaluating
PO3,
ii) F (A, B, C, D) = ∑m (1,3,5,7,9,15) ,d (A, B, C, D)= ∑m PO4
(4,6,12,13)

UNIT II
SYNCHRONOUS SEQUENTIAL LOGIC

Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of FF, Analysis
and design of clocked sequential circuits – Design – Moore/Mealy models, state minimization, state
assignment, circuit implementation - Registers – Counters.

PART – A
CO Mapping : CO202. 2
S. Question Blooms Competence PO
N Taxanom
o. y Level
1 Design the combinational circuit with 3 inputs and 1 BTL-1 Remembering PO1
output. The output is 1 when the binary value of the input
is less than 3. The output is 0 otherwise.
(May/June 2016)

2 Define Combinational circuits. (May/June 2016) BTL-1 Remembering PO1

3 Draw the truth table of half adder. (Nov./Dec. 2015) BTL-1 Remembering PO1

4 Write the Data flow description of a 4-bit Comparator. BTL-1 Remembering PO1
(April/May 2015)

5 Implement a 4 bit even parity generator. BTL-1 Remembering PO1

6 Implement a 4 bit even parity checker. BTL-1 Remembering PO1

7 Write the data flow description of a 4-bit comparator. BTL-1 Remembering PO1
(May 2015)

8 Implement a full adder with 4×1 multiplexer. (May 2015) BTL-1 Remembering PO1

9 Implement the following Boolean function using 8:1 BTL-1 Remembering PO1
multiplexer F(A,B,C)= ∑m(1,3,5,6)(Dec 2014)

10 (June Remembering PO1

Draw a 2 to 1 multiplexer circuit. (June 2014) 2014)

11 What is priority encoder? (Dec 2014) BTL-1 Remembering PO1

12 Draw the truth table and circuit diagram of 4 to 2 BTL-1 Remembering PO1
encoder. (Dec 2013)

13 Obtain the truth table for BCD to Excess-3 code BTL-1 Remembering PO1
converter. (Dec 2013)

14 Write the stimulus for 2 to 1 line MUX. (June 2012) BTL-1 Remembering PO1
15 Distinguish between a decoder and a de multiplexer. (June BTL-1 Remembering PO1
2012)
16 Design a 2-bit binary to gray code converter. BTL-1 Remembering PO1
17 Draw the 4 bit Gray to Binary code converter. BTL-1 Remembering PO1
18 Draw the 4 bit Binary to Gray code converter. BTL-1 Remembering PO1
19 Distinguish between combinational logic and sequential BTL-1 Remembering PO1
logic.
20 Implement half Adder using NAND Gates. BTL-1 Remembering PO1

21 Design a half sub tractor. BTL-1 Remembering PO1

22 Give the truth table for half adder and write the PO1,
expression for sum and carry. PO2,
BTL-5 Evaluating
PO3,
PO4
23 Mention the different type of binary codes. BTL-1 Remembering PO1

24 What is meant by self-complementing code? BTL-1 Remembering PO1

25 Draw the logic diagram of a one to four line de- BTL-1 Remembering PO1
multiplexer.
26 List the advantages and disadvantages of BCD code BTL-1 Remembering PO1
27 Implement a full adder with two half adder. BTL-1 Remembering PO1

28 Define Tristate gates. BTL-5 Evaluating PO4

29 Define logic synthesis and simulation. BTL-1 Remembering PO1

PART B
1 Implement the following Boolean function with 4 X 1
multiplexer and external gates. Connect inputs A and B to the
selection lines. The input requiremnts for the four data lines
will be a function of variables C and D these values are
obatined by expressing F as a function of C and D for each
four cases when AB = 00, 01, 10 and 11. These functions may PO1,
have to be implemented with external gates. F(A, B, C, D) = BTL-5 PO2,
Evaluating
Σ (1, 2, 5, 7, 8, 10, 11, 13, 15). (May/June 2016) PO3,
PO4

2 Design a full adder with x, y, z and two outputs S and C. The BTL-6 Creating PO1,
circuits performs x+y+z, z is the input carry, C is the output PO2,
carry and S is the Sum. PO3
(May/June 2016)

Design a code converter thet converts a 8421 to BCD code. PO1,

3 (Nov./Dec. 2015) PO2,
BTL-5 Evaluating
PO3,
PO4
4 (i) Explain the Analysis procedure. Analyze the following BTL-5 Evaluating PO1,
 logic diagram. (April/May 2015)

PO2,
PO3,
PO4

(ii) With neat diagram explain the 4-bit adder with

carry lookahead.

5 (a) Design 2-bit magnitude comparator and write a verilog BTL-2 Understanding PO1,
HDL code. (Dec 2015) PO2

(b)Implement the following Boolean functions with a

multiplexer: F(w,x,y,z)= ∑(2,3,5,6,11,14,15)

(c) Construct a 5 to 32 line decoder using 3 to 8 line decoders

and 2 to 4 line decoder. (May 2015)

6 Design and implement a 8241 to gray code converter. Realize PO1,

the converter using only NAND gates (Dec 2014) PO2,
BTL-5 Evaluating
PO3,
PO4
7 Design a circuit that converts 8421 BCD code to Excess-3 BTL4
(June 2014)

(b) Implement the following using 8 to 1 multiplexer. (June

2014)

8 (i).Realize 4 x 16 decoder using two 3 x 8 decoders with BTL-2 Understanding PO1,

enable input. PO2

(ii) Implement the following functions using a multiplexer.

F(W,X,Y,Z)= ∑m (0,1,3,4,8,9,15). (Dec 2013)

9 5.(i).Design a combinational circuit to perform BCD addition. Creating PO1,

PO2,
(ii).Design a 4-bit magnitude comparator with three (Dec
PO3
outputs :A<B ,A=B ,A>B. (Dec 2013) 2013)

10 Construct a 4 to 16 line decoder with an enable input using F(W,X,Y, Understanding PO1,
 Z)= ∑m PO2
five 2 to 4 line decoders with
(0,1,3,4,8,
enable inputs. (June 2012) 9,15).

11 Design a BCD to 7 segment decoder and implement it by BTL-6 Creating PO1,

using basic gates. (Dec 2012) PO2,
PO3
12 1. Discuss the need and working principle of Carry Look PO1,
ahead adder. (Dec 2012) PO2,
BTL-5 Evaluating
PO3,
PO4
13 Design a full adder using 2 half adders. PO1,
PO2,
BTL-5 Evaluating
PO3,
PO4
14 Design a logic circuit that accepts a 4 bit Gray code and PO1,
converts it into 4 bit binary code. PO2,
BTL-5 Evaluating
PO3,
PO4

UNIT III
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands of
Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory Location, Address
and Operation – Instruction and Instruction Sequencing – Addressing Modes, Encoding of Machine
Instruction – Interaction between Assembly and High Level Language

PART-A

Bloom’s
Q. No. Questions CO
Level

Write the basic functional units of computer?

C204.
1. The basic functional units of a computer are input unit, output unit, memory unit, BTL1
1
ALU unit and control unit

Write the basic functional units of computer? (APR/MAY 2017,NOV/DEC C204. BTL1
2017) 1
2. The basic functional units of a computer are input unit, output unit, memory unit,
ALU unit and control unit.

3. What is a bus? What are the different buses in a CPU? [ APR/MAY 2011] C204. BTL1
1
 A group of lines that serve as a connecting path for several devices is called
bus .The different buses in a CPU are 1] Data bus 2] Address bus 3] Control bus.

What is meant by stored program concepts? C204. BTL1

4. 1
Stored program concept is an idea of storing the program and data in the memory

Define multiprogramming?(A.U.APR/MAY 2013) C204. BTL1

1
Multiprogramming is a technique in several jobs are in main memory at once
5 and the processor is switched from job as needed to keep several jobs
advancing while keeping the peripheral devices in use.

What is meant by VLSI technology? C204. BTL6

1
VLSI is the abbreviation for Very Large Scale Integration. In this technology
6 millions of transistors are put inside a single chip as tiny components. The VLSI
chips do the function of millions of transistors. These are Used to implement
parallel algorithms directly in hardware

Define multiprocessing? C204. BTL6

1
Multiprocessing is the ability of an operating system to support more than one
7 process at the same time

8 List the eight great ideas invented by computer architecture? APR/MAY-2015 C204. BTL1
1
 Design for Moore’s Law
 Use abstraction to simplify design
 Make the common case fast
 Performance via Parallelism
 Performance via Pipelining
 Performance via Prediction
 Hierarchy of Memory
 Dependability via Redundancy
 Define power wall. C204. BTL1
1
 Old conventional wisdom
 Power is free
 Transistors are expensive
9
 New conventional wisdom: “Power wall”
 Power expensive
 Transistors“free” (Can put more on chip than can afford to turn
on)

What are clock and clock cycles? C204. BTL1

1
The timing signals that control the processor circuits are called as clocks. The
10
clock defines regular time intervals called clock cycles.

What is uniprocessor? C204. BTL1

1
A uniprocessor system is defined as a computer system that has a single central
processing unit that is used to execute computer tasks. As more and more modern
11 software is able to make use of multiprocessing architectures, such as SMP and
MPP, the term uniprocessor is therefore used to distinguish the class of computers
where all processing tasks share a single CPU.

What is multicore processor? C204. BTL1

1
A multi-core processor is a single computing component with two or more
independent actual central processing units (called "cores"), which are the units
12 that read and execute program instructions.The instructions are ordinary CPU
instructions such as add, move data, and branch, but the multiple cores can run
multiple instructions at the same time, increasing overall speed for programs
amenable to parallel computing

13 Differentiate super computer and mainframe computer. C204. BTL1

1
A computer with high computational speed, very large memory and parallel
structured hardware is known as a super computer.EX: CDC 6600. Mainframe
computer is the large computer system containing thousands of IC’s. It is a room-
sized machine placed in special computer centers and not directly accessible to
average users. It serves as a central computing facility for an organization such as
university, factory or bank.
 Differentiate between minicomputer and microcomputer. C204. BTL1
1
Minicomputers are small and low cost computers are characterized by Short word
14 size i.e. CPU word sizes of 8 or 16 bits. They have limited hardware and software
facilities. They are physically smaller in size.Microcomputer is a smaller, slower
and cheaper computer packing all the electronics of the computer in to a handful of
IC’s, including CPU and memory and IO chips

What is instruction register?(NOV/DEC 2016) C204. BTL1

1
The instruction register (IR) holds the instruction that is currently being executed.
15 Its output is available to the control circuits which generate the timing signals that
control the various processing elements involved in executing the instruction.

What is program counter? C204. BTL1

1
The program counter (PC) keeps track of the execution of a program. It contains
16
the memory address of the next instruction to be fetched and executed.

What is processor time? C204. BTL1

1
17 The sum of the periods during which the processor is active is called the processor
time

Give the CPU performance equation. C204. BTL1

1
CPU execution time for a program =Instruction Count XClock cycles per
18
instructionXClock cycle time.

What is superscalar execution? C204. BTL1

1
In this type of execution, multiple functional units are used to create parallel paths
19 through which different instructions can be executed in parallel. So it is possible to
start the execution of several instructions in every clock cycle. This mode of
operation is called superscalar execution

20 What is RISC and CISC? C204. BTL1

1
The processors with simple instructions are called as Reduced Instruction Set
Computers (RISC). The processors with more complex instructions are called as
Complex Instruction Set Computers (CISC).
 List out the methods used to improve system performance. C204. BTL1
1
The methods used to improve system performance are
 Processor clock
 Basic Performance Equation
21
 Pipelining
 Clock rate
 Instruction set
 Compiler

Define addressing modes and its various types.(nov/dec 2017) C204. BTL1
1
The different ways in which the location of a operand is specified in an
22 instruction is referred to as addressing modes. The various types are
Immediate Addressing, Register Addressing, Based or Displacement
Addressing, PC-Relative Addressing, Pseudodirect Addressing.

Define register mode addressing. C204. BTL1

1
In register mode addressing, the name of the register is used to specify the
23 operand. Eg. Add $s3, $s5,$s6.

Define Based or Displacement mode addressing. C204. BTL1

1
In based or displacement mode addressing, the operand is in a memory
24 location whose address is the sum of a register and a constant in the
instruction. Eg. lw $t0,32($s3).

25 State Amdahl’s Law. C204. BTL1

1
Amdahl’s law is a formula used to find the maximum improvement
improvement possible by improving a particular part of a system. In parallel
computing, Amdahl's law is mainly used to predict the theoretical maximum
speedup for program processing using multiple processors.
 Define Relative mode addressing. C204. BTL1
(Nov 2014) 1

In PC-relative mode addressing, the branch address is the sum of the PC and a
26 constant in the instruction. - In the relative address mode, the effective address is
determined by the index mode by using the program counter in stead of general
purpose processor register. This mode is called relative address mode.

Distinguish pipelining from parallelism APR/MAY 2015 C204. BTL1

1
parallelism means we are using more hardware for the executing the desired
task. in parallel computing more than one processors are running in parallel.
there may be some dedicated hardware running in parallel for doing the
specific task.
while the pipelining is an implementation technique in which multiple
27
instructions are overlapped ninexecution.parallelism increases the performance
but the area also increases.
in case of pipelining the performance and througput increases at the cost of
pipelining registers area pipelining there are different hazards like data
hazards, control hazards etc.

28 Distinguish pipelining from parallelism APR/MAY 2015 C204. BTL1

1
parallelism means we are using more hardware for the executing the desired
task. in parallel computing more than one processors are running in parallel.
there may be some dedicated hardware running in parallel for doing the
specific task.
while the pipelining is an implementation technique in which multiple
instructions are overlapped ninexecution.parallelism increases the performance
but the area also increases.
in case of pipelining the performance and througput increases at the cost of
pipelining registers area pipelining there are different hazards like data
hazards, control hazards etc.
 How to represent Instruction in a computer system?MAY/JUNE 2016 C204. BTL3
1
Computer instructions are the basic components of a machine language
program. They are also known as macrooperations, since each one is comprised of
a sequences of microoperations. Each instruction initiates a sequence of
microoperations that fetch operands from registers or memory, possibly perform
arithmetic, logic, or shift operations, and store results in registers or memory.
Instructions are encoded as binary instruction codes. Each instruction code
29 contains of aoperation code, or opcode, which designates the overall purpose of the
instruction (e.g. add, subtract, move, input, etc.). The number of bits allocated for
the opcode determined how many different instructions the architecture supports.
In addition to the opcode, many instructions also contain one or more operands,
which indicate where in registers or memory the data required for the operation is
located. For example, add instruction requires two operands, and a not
instruction requires one.

Brief about relative addressing mode.NOV/DEC 2014 C204. BTL1

1
Relative addressing mode - In the relative address mode, the effective
address is determined by the index mode by using the program counter in
30
stead of general purpose processor register. This mode is called relative
address mode.

31 Distinguish between auto increment and auto decrement addressing mode? C204. BTL1
1
MAY/JUNE 2016

A special case of indirect register mode. The register whose number is included in
the instruction code, contains the address of the operand. Autoincrement Mode =
after operand addressing , the contents of the register is incremented. Decrement
Mode = before operand addressing, the contents of the register is decrement. We
denote the autoincrement mode by putting the specified register in parentheses, to
show that the contents of the register are used as the efficient address, followed by
a plus sign to indicate that these contents are to be incremented after the operand is
accessed. Thus, using register R4, the autoincrement mode is written as (R4)+.

As a companion for the autoincrement mode, another mode is often available in

which operands are accessed in the reverse order. Autodecrementmode The
contents of a register specified in the instruction are decremented. These contents
are then used as the effective address f the operand. We denote the autodecrement
mode by putting the specified register in parentheses, preceded by a minus sign to
indicate that the contents of register are to be decremented before being used as the
 effective address. Thus, we write (R4).

This mode allows the accessing of operands in the direction of descending

addresses. The action performed by the autoincrement and auto decrement
addressing modes can be achieved using two instruction, one to access the operand
and the other to increment or to decrement the register that contains the operand
address. Combining the two operations in one instruction reduces the number if
instructions needed to perform the task.

If computer A runs a program in 10 seconds and computer B runs the same C204. BTL1
program in 15 seconds how much faster is A than B? 1

We know that A is n times as fast as B if

Thus the performance ratio is

32

and A is therefore 1.5 times as fast as B.

In the above example, we could also say that computer B is 1.5 times slower
than computer A, since

means that

33 Our favorite program runs in 10 seconds on computer A, which has a 2 GHz C204. BTL1
clock. We are trying to help a computer designer build a computer, B, which 1
will run this program in 6 seconds. The designer has determined that a
substantial increase in the clock rate is possible, but this increase will affect
the rest of the CPU design, causing computer B to require 1.2 times as many
clock cycles as computer A for this program. What clock rate should we tell
the designer to target?
 Let’s first find the number of clock cycles required for the program on A:

CPU time for B can be found using this equation:

To run the program in 6 seconds, B must have twice the clock rate of A.

34 Suppose we have two implementations of the same instruction set C204. BTL1
architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for 1
some program, and computer B has a clock cycle time of 500 ps and a CPI of
1.2 for the same program. Which computer is faster for this program and by
how much?
 We know that each computer executes the same number of instructions for the
program; let’s call this number I. First, find the number of processor clock cycles
for each computer:

Now we can compute the CPU time for each computer:

Likewise, for B:

Clearly, computer A is faster. The amount faster is given by the ratio of the
execution times:

We can conclude that computer A is 1.2 times as fast as computer B for this
program.

35 Define CPU execution time and list the types. C204. BTL1
1
CPU execution time

Also called CPU time. The actual time the CPU spends computing for a
specific task.

Types:

User CPU time

The CPU time spent in a program itself.

System CPU time

The CPU time spent in the operating system performing tasks on behalf of
 the program
Define response time C204. BTL1
1
Response time:

36 Also called execution time. The total time required for the computer to
complete a task, including disk accesses, memory accesses, I/O activities,
operating system overhead, CPU execution time, and so on.

What is Throughput? C204. BTL1

1
Also called bandwidth. Another measure of performance, it is the number
37 of tasks completed per unit time.

Define Clock cycles: C204. BTL1

1
All computers are constructed using a clock that determines when events
38 take place in the hardware. These discrete time intervals are called clock cycles
(or ticks, clock ticks, clock periods, clocks, cycles).

Write Basic performance equation in terms of instruction count (the number C204. BTL1
of instructions executed by the program), CPI, and clock cycle time. 1

39

or, the clock rate is the inverse of clock cycle time:

Compile given Two C Assignment Statements into MIPS C204. BTL1

a = b + c; 1
d = a – e;
40
Answer
add a, b, c
sub d, a, e
 Compile givenC Assignment Statement into MIPS C204. BTL1
1
f = (g + h) – (i + j);
add t0,g,h # temporary variable t0 contains g + h
41 add t1,i,j # temporary variable t1 contains i + j
sub f,t0,t1 # f gets t0 –t1, which is
(g + h) – (i + j)

Compile givenC Assignment Statement into MIPS C204. BTL1

g = h + A[8]; 1
42 Answer
The first compiled instruction is
lw$t0,8($s3) # Temporary reg $t0 gets A[8]
add$s1,$s2,$t0 # g = h + A[8]

What are the three types of operands in MIPS C204. BTL1

1
1 .word
43
2.Memory Operands
3.Constant or Immediate Operands

Compile givenC Assignment Statement into MIPS C204. BTL1

1
A[12] = h + A[8];
Answer
44 $t0: lw$t0,32($s3)
# Temporary reg $t0 gets A[8]
add$t0,$s2,$t0
# Temporary reg $t0 gets h + A[8]
sw$t0,48($s3)
# Stores h + A[8] back into A[12]

Write MIPS To add 4 to register $s3. C204. BTL1

1
45 addi$s3,$s3,4# $s3 = $s3 + 4
 Define Instruction format C204. BTL1
A form of representation of an instruction composed of fields of binary 1
numbers.The numeric version of instructions machine language and a sequence of
46 such instructions machine code.

What are the types of instruction format in MIPS C204. BTL1

1
1. R-type (for register) or R-format.
47
2.I-type (for immediate) or I-format

3.J-type or Jump
What are the types of instruction in MIPS.(APR/MAY2018) C204. BTL1
1
1. Arithmetic instruction
2. Data transfer Instruction
48 3. Logical Instruction
4. Conditional Branch Instruction
5. Unconditional jump Instruction

Compile givenC Statement into MIPS C204. BTL1

if (i == j) f = g + h; else f = g – h; 1

49 bne $s3,$s4,Else# go to Else if i ≠ j

add $s0,$s1,$s2# f = g + h (skipped if i ≠ j)

Compile givenC Statement into MIPS C204. BTL1

1
while (save[i] == k)
i += 1;
Ans:
Loop: sll$t1,$s3,2# Temp reg $t1 = i * 4
add $t1,$t1,$s6# $t1 = address of save[i]
50 lw $t0,0($t1)
# Temp reg $t0 = save[i]
bne $t0,$s5, Exit
# go to Exit if save[i] ≠ k
addi $s3,$s3,1# i = i + 1
jLoop# go to Loop
Exit:

51 State indirect addressing mode give example.(APR/May 2017) C204. BTL1

 Indirect Mode. The effective address of the operand is the contents of a register or 1
main memory location, location whose address appears in the instruction. ...
Once it's there, instead of finding an operand, it finds an address where the
operand is located.
LOAD R1, @R2 Load the content of the memory address stored
atregister R2 to register R1.

PART-B

Bloom’s
Q. No. Questions CO
Level

i)Discuss in detail about Eight great ideas of computer Architecture.(8)

Page.No:11-13)
C204.
1. ii) Explain in detail about Technologies for Building Processors and BTL5
1
Memory (8) )(Page.No:24-28)

Explain the various components of computer System with neat diagram (16) C204. BTL5
1
.(NOV/DEC2014,NOV/DEC2015,APR/MAY 2016,NOV/DEC
2. 2016,APR/MAY2018)) (Page.No:16-17)

Discuss in detail the various measures of performance of a computer(16) C204. BTL6

1
(Page.No:28-40)
3.

Define Addressing mode and explain the different types of basic C204. BTL5
addressing modes with an example 1

4. (APRIL/MAY2015 ,NOV/DEC2015,APR/MAY 2016,NOV/DEC

2016,APR/MAY2018)

(Page.No:116-117)

5. i)Discuss the Logical operations and control operations of computer (12) C204. BTL6
 (Page.No:87-89) 1

ii)Write short notes on Power wall(6)

(Page.No:40-42)

Consider three diff erent processors P1, P2, and P3 executing the same instruction C204. BTL5
set. P1 has 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a 1
CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. (APR/MAY 2018)

a. Which processor has the highest performance expressed in instructions

per second?

b. If the processors each execute a program in 10 seconds, find the number

6. of cycles and the number of instructions.

c. We are trying to reduce the execution time by 30% but this leads to an
increase

of 20% in the CPI. What clock rate should we have to get this time
reduction?

(Refer Notes)

Explain various instruction format illustrate the same with an example C204. BTL5
7. 1
NOV/DEC2017 (Page.No:80-86)

Explain direct ,immediate ,relative and indexed addressing modes with C204. BTL5
8. example APR/MAY2018 (Page.No:116-117) 1

State the CPU performance equation and the factors that affect performance C204. BTL5
(8) 1
9.
(NOV/DEC2014) (Refer Notes)

Discuss about the various techniques to represent instructions in a computer C204. BTL6
system. 1
10.
(APRIL/MAY2015,NOV/DEC 2017) (Page.No:80-86)

11. What is the need for addressing in a computer system?Explain the different C204. BTL5
addressing modes with suitable examples.(APRIL/MAY2015) 1
 (Page.No:116-117)

Explain types of operations and operands with examples.(NOV/DEC 2017) C204. BTL5
12. 1
(Page.No:63-70)

Consider two diff erent implementations of the same instruction C204. BTL5
1
set architecture. Th e instructions can be divided into four classes according
to

their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs
of 1, 2, 3,

and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2.

Given a program with a dynamic instruction count of 1.0E6 instructions

13. divided

into classes as follows: 10% class A, 20% class B, 50% class C, and 20%
class D,

which implementation is faster?

a. What is the global CPI for each implementation?

b. Find the clock cycles required in both cases.

(Refer Notes)

To what should the CPI of load/store instructions be C204. BTL5

1
reduced in order for a single processor to match the performance of four
14.
processors using the original CPI values?

(Refer Notes)

Describe the steps that transform a program written in a high-level C204. BTL4
1
language such as C into a representation that is directly executed by a
15.
computer processor.

(Refer Notes)

UNIT IV 9

Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
Microprogrammed Control – Pipelining – Data Hazard – Control Hazards – Exceptions.
 PART-A

Bloom’s
Q. No. Questions CO
Level

What is pipelining?

The technique of overlapping the execution of successive instruction for

substantial improvement in performance is called pipelining. C204.
1. BTL1
3
.

What is and precise C204. BTL1

exception? 3

2. A precise exception is one in which all instructions prior to the faulting

instruction are complete and instruction following the faulting instruction,
including the faulty instruction; do not change the state of the machine.

Define processor cycle in C204. BTL1

pipelining. 3

The time required between moving an instruction one step down the pipeline is
a processor cycle.
3.

What is meant by pipeline bubble?(NOV/DEC 2016) C204. BTL1

3
To resolve the hazard the pipeline is stall for 1 clock cycle. A stall is
4. commonly called a pipeline bubble, since it floats through the pipeline taking
space but carrying no useful work.
 What is pipeline register delay? C204. BTL1
3
Adding registers between pipeline stages me adding logic between stages and
5 setup and hold times for proper operations. This delay is known as pipeline
register delay.

What are the major characteristics of a pipeline? C204. BTL6

3
The major characteristics of a pipeline are:

6 1. Pipelining cannot be implemented on a single task, as it works by

splitting multiple tasks into a number of subtasks and operating on
them simultaneously.

The speedup or efficiency achieved by suing a pipeline depends on the number of

pipe stages and the number of available tasks that can be subdivided

What is data path?(NOV/DEC 2016,APR/MAY2018) C204. BTL6

3
As instruction execution progress data are transferred from one instruction to
7 another, often passing through the ALU to perform some arithmetic or logical
operations. The registers, ALU, and the interconnecting bus are collectively
referred as the data path.

What is a pipeline hazard and what are its types? C204. BTL1
3
Any condition that causes the pipeline to stall is called hazard. They are
8
also called as stalls or bubbles. The various pipeline hazards are:

Hazard Control Hazard

What is Instruction or control hazard? C204. BTL1

3
The pipeline may be stalled because of a delay in the availability of an
9 instruction. For example, this may be a result of a miss in the cache, requiring
the instruction to be fetched from the main memory. Such hazards are often
called control hazards or instruction hazard.

10 Define structural hazards. C204. BTL1

3
 This is the situation when two instruction require the use of a given hardware
resource at the same time. The most common case in which this hazard may arise
is in access to memory

What is side effect? C204. BTL1

3
11
When a location other than one explicitly named in an instruction as a destination
operand is affected, the instruction is said to have a side effect

What do you mean by branch penalty? C204. BTL1

12 3
The time lost as a result of a branch instruction is often referred to as branch
penalty

What is branch folding? C204. BTL1

3
When the instruction fetch unit executes the branch instruction concurrently
13 with the execution of the other instruction, then this technique is called branch
folding.

What do you mean by delayed branching? C204. BTL1

3
Delayed branching is used to minimize the penalty incurred as a result of
conditional branch instruction. The location following the branch instruction is
14 called delay slot. The instructions in the delay slots are always fetched and they are
arranged such that they are fully executed whether or not branch is taken. That is
branching takes place one instruction later than where the branch instruction
appears in the instruction sequence in the memory hence the name delayed
branching

Define exception and interrupt. C204. BTL1

Dec 2012,NOV/DEC 3
14,MAY/JUNE
2016,APR/MAY2018))
Exception:

The term exception is used to refer to any event that causes an interruption.
15
Interrupt:

An exception that comes from outside of the processor. There are two
types of interrupt.

1. Imprecise interrupt and 2.Precise interrupt

 Why is branch prediction algorithm needed? Differentiate between the C204. BTL1
static and dynamic techniques. (May 2013,APR/MAY 2015,NOV/DEC 15) 3

The branch instruction will introduce branch penalty which would reduce the
gain in performance expected from pipelining. Branch instructions can be
handled in several ways to reduce their negative impact on the rate of
execution of instructions. Thus the branch prediction algorithm is needed.

Static Branch prediction

16 The static branch prediction, assumes that the branch will not take place and to
continue to fetch instructions in sequential address order.

Dynamic Branch prediction

The idea is that the processor hardware assesses the likelihood of a given
branch being taken by keeping track of branch decisions every time that
instruction is executed. The execution history used in predicting the outcome
of a given branch instruction is the result of the most recent execution of that
instruction.

What is branch Target Address? C204. BTL1

3
17 The address specified in a branch, which becomes the new program counter, if the
branch is taken. In MIPS the branch target address is given by the sum of the offset
field of the instruction and the address of the instruction following the branch

How do control instructions like branch, cause problems in a pipelined C204. BTL1
processor? 3

Pipelined processor gives the best throughput for sequenced line instruction.
In branch instruction, as it has to calculate the target address, whether the
18
instruction jump from one memory location to other. In the meantime, before
calculating the larger, the next sequence instructions are got into the pipelines,
which are rolled back, when target is calculated.

What is meant by super scalar processor? C204. BTL1

3
Super scalar processors are designed to exploit more instruction level
19
parallelism in user programs. This means that multiple functional units are
used. With such an arrangement it is possible to start the execution of
several instructions in every clock cycle. This mode of operation is called
 super scalar execution.

Define pipeline speedup. [ APR/MAY 2012] (A.U.NOV/DEC 2012) C204. BTL1

3
Speed up is the ratio of the average instruction time without pipelining to
20 the average instruction time with pipelining. Average instruction time
without pipelining Speedup= Average instruction time with pipelining

What is Vectorizer? C204. BTL1

3
The process to replace a block of sequential code by vector instructions is
21 called vectorization. The system software, which generates parallelism, is
called as vectorizing compiler.

What is pipelined computer? C204. BTL1

3
When hardware is divided in to a number of sub units so as to perform the sub
22
operations in an overlapped fashion is called as a pipelined computer.

List the various pipelined processors. C204. BTL1

3
23 8086, 8088, 80286, 80386. STAR 100, CRAY 1 and CYBER 205 etc

Classify the pipeline computers. C204. BTL1

3
Based on level of processing → processor pipeline, instruction pipeline,
arithmetic pipelines

Based on number of functions→ Uni-functional and multi functional pipelines.

24
Based on the configuration → Static and Dynamic pipelines and linear and non
linear pipelines

Based on type of input→ Scalar and vector pipelines.Asf

 C204. BTL1
3
Write down the expression for speedup factor in a pipelined architecture.
[MAY/JUNE ‘11]

The speedup for a pipeline computer is S = (k + n -1) tp

26
Where,K → number of segments in a pipeline,N → number of instructions to
be executed. Tp → cycle time

What are the problems faced in instruction pipeline. C204. BTL1

3
Resource conflicts → Caused by access to the memory by two at the same
time. Most of the conflicts can be resolved by using separate instruction and
data memories.

27 Data dependency → Arises when an instruction depends on the results of the

previous instruction but this result is not yet available.

Branch difficulties → Arises from branch and other instruction that change the
value of PC (Program Counter).

What is meant by vectored interrupt? (Nov/Dec 2013) C204. BTL1

3
An interrupt for which the address to which control is transferred is determined
28
by the cause of the exception.

29 What is the need for speculation?NOV/DEC 2014 C204. BTL3

3

One of the most important methods for finding and exploiting more ILP is
speculation. It is an approach whereby the compiler or processor guesses the
outcome of an instruction to remove it as dependence in executing other
instructions. For example, we might speculate on the outcome of a branch, so
that instructions after the branch could be executed earlier.

Speculation (also known as speculative loading ), is a process implemented in

Explicitly Parallel Instruction Computing ( EPIC ) processors and their
compiler s to reduce processor-memory exchanging bottlenecks or latency by
putting all the data into memory in advance of an actual load instruction
 Define Imprecise , Precise interrupt C204. BTL1
3
Imprecise interrupt

Also called imprecise exception. Interrupts or exceptions in pipelined

computers that are not associated with the exact instruction that was the cause of
30
the interrupt or exception.

Precise interrupt

Also called precise exception. An interrupt or exception that is always

associated with the correct instruction in pipelined computers

What are the advantages of pipelining?MAY/JUNE 2016 C204. BTL1

3

The cycle time of the processor is reduced; increasing the instruction

31 throughput.Some combinational circuits such as adders or multipliers can be made faster by
adding more circuitry. If pipelining is used instead, it can save circuitry vs. a more complex
combinational circuit.

What is Program counter (PC)(Fetching) C204. BTL1

32 The register containing the address of the instruction in the program being executed 3

What is Adder: C204. BTL1

An adder is needed to compute the next instruction address. The adder is 3
an ALU wired to always add its two 32-bit inputs and place the sum on its output.
33

What is Register file(decoding): C204. BTL1

A state element that consists of a set of registers that can be read and 3
written by supplying a register number to be accessed.
34
 Define Sign-extend in data path. C204. BTL1
To increase the size of a data item by replicating the high-order sign bit of 3
the original data item in the high-order bits of the larger, destination data item.
35
a unit to sign-extend the 16-bit offset field in the instruction to a 32-bit signed
value

Define Shifter: C204. BTL1

■ The jump instruction operates by replacing the lower 28 bits of the PC with the 3
lower 26 bits of the instruction shifted left by 2 bits. Simply concatenating 00
36 to the jump offset accomplishes this shift

What is Delayed branch? C204. BTL1

A type of branch where the instruction immediately following the branch is always 3
executed, independent of whether the branch condition is true or false.
37

What are the control lines of MIPS functions. C204. BTL1

3

ALU control lines Function

0000 AND

0001 OR
38

0010 add

0110 sub

0111 Set lessthan

1100 NOR
 Define Don’t-care term C204. BTL1
An element of a logical function in which the output does not depend on 3
the values of all the inputs
39

What are the Function of seven control lines? C204. BTL1

3

40

What are the Disadvantages of single cycle implementation? C204. BTL1

 Although the single-cycle design will work correctly, it would not be used 3
in modern designs because it is inefficient.
 Although the CPI is 1 the overall performance of a single-cycle
implementation is likely to be poor, since the clock cycle is too long.
 The penalty for using the single-cycle design with a fixed clock cycle is
41
significant,.
 To implement the floating-point unit or an instruction set with more
complex instructions, this single-cycle design wouldn’t work well .
 A single-cycle implementation thus violates the great idea of making the
common case fast.

42 What is Structural hazard? C204. BTL1

When a planned instruction cannot execute in the proper clock cycle 3
because the hardware does not support the combination of instructions that are set
to execute.
 If there is a single memory instead of two memories. If the pipeline had a
fourth instruction, that in the same clock cycle the first instruction is accessing
data from memory while the fourth instruction is fetching an instruction from that
same memory. Without two memories, pipeline could have a structural hazard.
To avoid structural hazards
 When designing a pipeline designer can change the design
By providing sufficient resources

Define Data Hazards. .(APR/MAY 2017) C204. BTL1

Data hazard is also called a pipeline data hazard. When a planned 3
instruction cannot execute in the proper clock cycle because data that is needed to
execute the instruction is not yet available.
 In a computer pipeline, data hazards arise from the dependence of one
instruction on an earlier one that is still in the pipeline
43
 Example:
add instruction followed immediately by a subtract instruction that
uses the sum ($s0):
add$s0, $t0, $t1
sub$t2, $s0, $t3

Define data Forwarding C204. BTL1

Forwarding is also called as bypassing. A method of resolving a data 3
hazard by retrieving the missing data element from internal buffers rather than
44 waiting for it to arrive from programmer-visible registers or memory.

Define load-use data hazard C204. BTL1

A specific form of data hazard in which the data being loaded by a load 3
instruction has not yet become available when it is needed by another
45
instruction

Define Pipeline stall C204. BTL1

Pipeline stall is also called as bubble. A stall initiated in order to resolve a 3
hazard.

46
 What is Control Hazard? C204. BTL1
Control hazard is also called as branch hazard. When the proper 3
instruction cannot execute in the proper pipeline clock cycle because the
47 instruction that was fetched is not the one that is needed; that is, the flow of
instruction addresses is not what the pipeline expected.

What are theSchemes for resolving control hazards ? C204. BTL1

3
1. Assume Branch Not Taken:

48 2. Reducing the Delay of Branches:

3. Dynamic Branch Prediction:

D e fine Branch delay slot C204. BTL1

The slot directly after a delayed branch instruction, which in the MIPS 3
architecture is filled by an instruction that does not affect the branch.
49

Define Correlating , Tournament branch predictor C204. BTL1

3
Correlating predictor
A branch predictor that combines local behavior of a particular branch and
global information about the behavior of some recent number of executed
50 branches.

Tournament branch predictor

A branch predictor with multiple predictions for each branch and a
selection mechanism that chooses which predictor to enable for a given branch

Name control signal to perform arithmetic operation.(APR/MAY 2017) C204. BTL1

1.Regdst 3
2.Regwrite
51 3.ALU Src
 what is ideal cycle per instruction in pipelining?(APR/MAY 2018) C204. BTL1
With pipelining, a new instruction is fetched every clock cycle by exploiting 3
instruction-level parallelism, therefore, since one could theoretically have five
52 instructions in the five pipeline stages at once (one instruction per stage), a
different instruction would complete stage 5 in every clock cycle

UNIT V MEMORY & I/O SYSTEMS 9

Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial Interface
– Interrupt I/O – Interconnection Standards: USB, SATA

PART -A

Bloom’s
Q. No. Questions CO
Level

What is principle of locality?

C204.
1. BTL1
The principle of locality states that programs access a relatively small 5
portion of their address space at any instant of time

Define spatial locality. C204. BTL1

5
2. The locality principle stating that if a data location is referenced, data locations
with nearby addresses will tend to be referenced soon.
 Define Memory Hierarchy.(MAY/JUNE 2016) C204. BTL1
5

A structure that uses multiple levels of memory with different speeds and
3. sizes. The faster memories are more expensive per bit than the slower memories.

Define hit ratio. (A.U.APR/MAY 2013,NOV/DEC 2015) C204. BTL1

5
When a processor refers a data item from a cache, if the referenced item is in
the cache, then such a reference is called Hit. If the referenced data is not in the
4. cache, then it is called Miss, Hit ratio is defined as the ratio of number of Hits
to number of references.

Hit ratio =Total Number of references

What is TLB? What is its significance? C204. BTL1

5
Translation look aside buffer is a small cache incorporated in memory
management unit. It consists of page table entries that correspond to most
5
recently accessed pages. Significance The TLB enables faster address
computing. It contains 64 to 256 entries

Define temporal locality. C204. BTL6

5
The principle stating that a data location is referenced then it will tend to be
referenced again soon.
6

7 How cache memory is used to reduce the execution time. (APR/MAY’10) C204. BTL6
5
If active portions of the program and data are placed in a fast small memory,
the average memory access time can be reduced, thus reducing the total
execution time of the program. Such a fast small memory is called as cache
memory.
 Define memory interleaving. (A.U.MAY/JUNE ’11) (apr/may2017) C204. BTL1
5
In order to carry out two or more simultaneous access to memory, the memory
8 must be partitioned in to separate modules. The advantage of a modular memory is
that it allows the interleaving i.e. consecutive addresses are assigned to different
memory module

Define Hit and Miss? (DEC 2013) C204. BTL1

5

9 The performance of cache memory is frequently measured in terms of a quantity

called hit ratio. When the CPU refers to memory and finds the word in cache, it is
said to produce a hit. If the word is not found in cache, then it is in main memory
and it counts as a miss

What is cache memory?NOV/DEC 2016 C204. BTL1

5
10
It is a fast memory that is inserted between the larger slower main memory and the
processor. It holds the currently active segments of a program and their data

What is memory system? [MAY/JUNE ‘11] [APR/MAY 2012] C204. BTL1

5
Every computer contains several types of devices to store the instructions and data
11 required for its operation. These storage devices plus the algorithm-implemented
by hardware and/or software-needed to manage the stored information from the
memory system of computer

What is Read Access Time? [APR/MAY 2012] C204. BTL1

5
12 A basic performance measure is the average time to read a fixed amount of
information, for instance, one word, from the memory. This parameter is called the
read access time

13 What is the necessary of virtual memory? State C204. BTL1

the advantages of virtual memory? MAY/JUNE 5
2016

Virtual memory is an important concept related to memory management. It is

used to increase the apparent size of main memory at a very low cost. Data are
addressed in a virtual address space that can be as large as the addressing
capability of CPU.

Virtual memory is a technique that uses main memory as a “cache” for

secondary
 storage. Two major motivations for virtual memory: to allow efficient and safe
sharing of memory among multiple programs, and to remove the programming
burdens of a small, limited amount of main memory

What are the units of an interface? (Dec 2012) C204. BTL1

5
14 DATAIN, DATAOUT, SIN, SOUT

Distinguish between isolated and memory mapped I/O? (May 2013) C204. BTL1
5
The isolated I/O method isolates memory and I/O addresses so that memory
address values are not affected by interface address assignment since each has its
15 own address space.

In memory mapped I/O, there are no specific input or output instructions. The
CPU can manipulate I/O data residing in interface registers with the same
instructions that are used to manipulate memory words

Distinguish between memory mapped I/O and C204. BTL1

I/O mapped I/O. Memory mapped I/O: 5

When I/O devices and the memory share the same address space, the
arrangement is called memory mapped I/O. The machine instructions that can
access memory is used to trfer data to or from an I/O device.

16
I/O mapped I/O:

Here the I/O devices the memories have different address space. It has special
I/O instructions. The advantage of a separate I/O address space is that I/O
devices deals with fewer address lines.

Define virtual memory.(nov/dec 2017) C204. BTL1

5
The data is to be stored in physical memory locations that have addresses
17 different from those specified by the program. The memory control circuitry
translates the address specified by the program into an address that can be used
to access the physical memory
 What is Semi Random Access? C204. BTL1
5
Memory devices such as magnetic hard disks and CD-ROMs contain many
rotating storage tracks. If each track has its own read write head, the tracks can
18
be accessed randomly, but access within each track is serial. In such cases the
access mode is semi random.

What is the use of DMA? (Dec 2012)(Dec 2013,APR/MAY2018) C204. BTL1

5
DMA (Direct Memory Access) provides I/O transfer of data directly to and from
19
the memory unit and the peripheral.

Mention the advantages of USB. (May 2013) C204. BTL1

5
The Universal Serial Bus (USB) is an industry standard developed to provide two
20 speed of operation called low-speed and full-speed. They provide simple, low cost
and easy to use interconnect system.

What is meant by vectored interrupt?(Dec 2013) C204. BTL1

5
Vectored Interrupts are type of I/O interrupts in which the device that generates the
21 interruptrequest (also called IRQ in some text books) identifies itself directly to the
processor

22 Compare Static RAM and Dynamic RAM.(Dec 2013,APR/MAY2018) C204. BTL1

5
Static RAM is more expensive, requires four times the amount of space for a given
amount of data than dynamic RAM, but, unlike dynamic RAM, does not need to be
power-refreshed and is therefore faster to access. Dynamic RAM uses a kind of
capacitor that needs frequent power refreshing to retain its charge. Because reading
a DRAM discharges its contents, a power refresh is required after each read. Apart
from reading, just to maintain the charge that holds its content in place, DRAM
must be refreshed about every 15 microseconds. DRAM is the least expensive kind
of RAM.

SRAMs are simply integrated circuits that are memory arrays with a single
access port that can provide either a read or a write. SRAMs have a fixed access
time to any datum.

SRAMs don’t need to refresh and so the access time is very close to the cycle

time. SRAMs typically use six to eight transistors per bit to prevent the
information from being disturbed when read. SRAM needs only minimal power to
 retain the charge in standby mode.

In a dynamic RAM (DRAM), the value kept in a cell is stored as a charge

in a capacitor. A single transistor is then used to access this stored charge, either to
read the value or to overwrite the charge stored there. Because DRAMs use only a
single transistor per bit of storage, they are much denser and cheaper per bit than
SRAM

DRAMs store the charge on a capacitor, it cannot be kept indefinitely and

must periodically be refreshed.

what is DMA ?(NOV/DEC 2014) C204. BTL1

5
Direct memory access (DMA) is a method that allows an input/output
23 (I/O) device to send or receive data directly to or from the main memory,
bypassing the CPU to speed up memory operations. The process is managed by a
chip known as a DMA controller (DMAC).

Differentiate programmed I/O and interrupt i/O..(NOV/DEC2014) C204. BTL1

5

programmed I/O interrupt i/O

Programmed IO is the process of IO Interrupt Initiated IO is done by using

24 instruction written in computer interrupt and some special command.
program

In Programmed IO technique to In Interrupt Initiated IO once data

transfer data,required constant transfer initiated ,CPU execute next
motoring on peripheral by CPU,once program without wasting time and
data transfer is initiated, CPU have to the interface keep monitoring the
wait for next transfer. device.
what is the purpose of dirty /modified bit in cache memory.(NOV/DEC2014) C204. BTL1
5
A dirty bit or modified bit is a bit that is associated with a block of computer
memory and indicates whether or not the corresponding block of memory has been
25 modified.[1] The dirty bit is set when the processor writes to (modifies) this
memory. The bit indicates that its associated block of memory has been modified
and has not yet been saved to storage.
 C204. BTL1
What is the need to implement memory as a hierarchy? (APRIL/MAY2015) 5

26

C204. BTL1
Point out how DMA can improve I/O speed? APRIL/MAY 2015 5

CPU speeds continue to increase, and new CPUs have multiple processing
elements on the same chip.A large amount of data can be processed very quickly
Problem in the transfer of data to CPU or even memory in a reasonable amount of
time so that CPU has some work to do at all time . Without DMA, when the CPU
27
is using programmed input/output, it is typically fully occupied for the entire
duration of the read or write operation, and is thus unavailable to perform other
work. With DMA, the CPU first initiates the transfer, then it does other operations
while the transfer is in progress, and it finally receives an interrupt from the DMA
controller when the operation is done.

28 C204. BTL1
What are the various memory Technologies?NOV/DEC 2015 5

Memory Technologies

Main memory is implemented from DRAM (dynamic random access memory),

while levels closer to the processor (caches) use SRAM (static random access
memory). DRAM is less costly per bit than SRAM, although it is substantially
slower. The price difference arises because DRAM uses significantly less area per
bit of memory, and DRAMs thus have larger capacity for the same amount of
silicon;

Memory technology Typical access time $ per GiB in 2012

SRAM semiconductor memory 0.5–2.5 ns $500–$1000

DRAM semiconductor memory 50–70 ns $10–$20

 Flash semiconductor memory 5,000–50,000 ns $0.75–$1.00

Magnetic disk 5,000,000–20,000,000 ns $0.05–$0

C204. BTL3
5
What is flash memory?

Flash memory is a type of electrically erasable programmable read-only

29 memory (EEPROM). Unlike disks and DRAM, EEPROM technologies can wear
out flash memory bits. To cope with such limits, most flash products include a
controller to spread the writes by remapping blocks that have been written many
times to less trodden blocks. This technique is called wear leveling.

In many computers the cache block size is in the range 32 to 128 bytes. C204. BTL1
What would be the main Advantages and disadvantages of making the size 5
of the cache blocks larger or smaller?
30
Larger the size of the cache fewer be the cache misses if most of the data in the
block are actually used. It will be wasteful if much of the data are not used before
the cache block is moved from cache. Smaller size means more misses

Define USB. C204. BTL1

5
Universal Serial Bus, an external busstandard that supports data transfer ratesof
12 Mbps. A single USB portcan be used to connect up to 127 peripheral devices,
such as mice, modems, and keyboards. USB also supportsPlug-and-Play
31 installationandhot plugging.

Define Memory latency C204. BTL1

5
The amount of time it takes to transfer a word of data to or from the
32
memory.

33 Define Memory bandwidth C204. BTL1

 Tthe number of bits or bytes that can be transferred in one second. It is used 5
to measure how much time is needed to transfer an entire block of data.

Define miss Rate. C204. BTL1

34 5
The miss rate (1−hit rate) is the fraction of memory accesses not found in the
upper level.

Define Hit rate. C204. BTL1

35 5
Hit rate The fraction of memory accesses found in a level of the memory
hierarchy. •

C204. BTL1
5
Define miss rate.
36
Miss rate The fraction of memory accesses not found in a level of the
memory hierarchy.

Define Hit time. C204. BTL1

37 5
Hit time is the time to access the upper level of the memory hierarchy, which
includes the time needed to determine whether the access is a hit or a miss

Define miss penalty C204. BTL1

5
38 The miss penalty is the time to replace a block in the upper level with the
corresponding block from the lower level, plus the time to deliver this block to
the processor

Define tag in TLB C204. BTL1

5
39
Tag A field in a table used for a memory hierarchy that contains the address
information required to identify whether the associated block in the hierarchy
corresponds to a requested word.

40 C204. BTL1
5
What are the steps to be taken on an instruction cache miss:

1. Send the original PC value (current PC – 4) to the memory.

2. Instruct main memory to perform a read and wait for the memory to
complete its access.

3. Write the cache entry, putting the data from memory in the data portion of
the entry, writing the upper bits of the address (from the ALU) into the tag
field, and turning the valid bit on.
 4. Restart the instruction execution at the first step, which will refetch the
instruction, this time finding it in the cache

What is write through cache C204. BTL1

5
41
The simplest way to keep the main memory and the cache consistent is always
to write the data into both the memory and the cache. • This scheme is called
write-through.

What is write back cache C204. BTL1

5
42
In a write back scheme, when a write occurs, the new value is written only to
the block in the cache.

C204. BTL1
5
What are the techniques to improve cache performance?

43 Two different techniques for improving cache performance. • One focuses on

reducing the miss rate by reducing the probability that two different memory
blocks will participate for the same cache location. • The second technique
reduces the miss penalty by adding an additional level to the hierarchy. This
technique, called multilevel caching

C204. BTL1
5
Define dirty bit
44
dirty bit is commonly used. This status bit indicates whether the block is dirty
(modified while in the cache) or clean (not modified).

What is TLB. C204. BTL1

5
45
Translation-lookaside buffer (TLB)A cache that keeps track of recently used
address mappings to try to avoid an access to the page table.

C204. BTL1
5
What are the messages transferred in DMA?
46

To initiate the transfer of a block of words , the processor sends, i) Starting

address ii) Number of words in the block iii)Direction of transfer.

47 Define Burst mode. C204. BTL1

5
 Burst Mode: The DMA controller may be given exclusive(limited) access to
the main memory to transfer a block of data without interruption. This is
known as Burst/Block Mode. •

Define bus master C204. BTL1

5
48
Bus Master: The device that is allowed to initiate data transfers on the bus at
any given time is called the bus master

Define bus arbitration. C204. BTL1

5
49
Bus Arbitration: It is the process by which the next device to become the bus
master is selected and the bus mastership is transferred to it.

What are the approaches for bus arbitration? C204. BTL1

5
50
There are 2 approaches to bus arbitration. They are i)Centralized arbitration
( A single bus arbiter performs arbitration) ii)Distributed arbitration (all
devices participate in the selection of next bus master).

PART -B

Bloom’s
Q. No. Questions CO
Level

Explain in detail about memory C204.

1. . BTL5
Technologies(APRIL/MAY2015,NOV/DEC2017) ( Page.No:-378-383) 5

Expain in detail about memory Hierarchy with neat diagram C204. BTL5
2. . 5
( Page.No:-374-378)

Discuss the various mapping schemes used in cache C204. BTL6

3. .
memory(NOV/DEC2014) ( Page.No:-383-397) 5

Discuss the methods used to measure and improve the performance of the C204. BTL6
4. .
cache.(NOV/DEC 2017) ( Page.No:-398-417) 5

5. Explain the virtual memory address translation and TLB with necessary C204. BTL5
diagram.(APRIL/MAY2015,NOV/DEC 2015,NOV/DEC 5
 2016,APR/MAY2018) ( Page.No:-427-452)

C204. BTL5
5
Draw the typical block diagram of a DMA controller and explain how it is
6.
used for direct data transfer between memory and peripherals. (NOV/DEC
2015,MAY/JUNE 2016,NOV/DEC 2016,MAY/JUN 2018) Page.No:-399-
402)

Explain in detail about interrupts with diagram C204. BTL5

7. 5
(Page.No:-436-242)

Describe in detail about programmed Input/Output with neat diagram C204. BTL5
8. 5
(MAY/JUN 2018) (Refer notes)

Explain in detail about the bus arbitration techniques.(NOV/DEC2014)(8) C204. BTL5

9. 5
(Page.No:-237-242)

Draw different memory address layouts and brief about the technique used C204. BTL5
to increase the average rate of fetching words from the main memory (8) 5
10. (NOV/DEC2014)

(Refer notes)

Explain in detail about any two standard input and output interfaces C204. BTL5
required to connect the I/O devices to the bus.(NOV/DEC2014) 5
11.
(Page.No:-438-452)

Explain mapping functions in cache memory in cache memory to determine C204. BTL5
how memory blocks are placed in cache (Nov/Dec 2014) (Refer notes) 5
12.

Explain the various mapping techniques associated with cache memories C204. BTL5
(MAY/JUNE 2016,MAY/JUN 2018) 5
13.
(Refer notes)

14. Explain sequence of operations carried on by a processor when interrupted C204. BTL5
by a peripheral device connected to it(MAY/JUN 2018) (Page.No:-436- 5
 242)

Explain virtual memory and the advantages of using virtual memory C204. BTL5
15. 5
(Page.No:-427-252)

PART-B

Bloom’s
Q. No. Questions CO
Level

Explain the basic MIPS implementation with binary multiplexers and C204.3 BTL5
1. .
control lines(16) NOV/DEC 15 (Page.No:244-251)

What is hazards ?Explain the different types of pipeline hazards with C204.3 BTL5
suitable examples.(NOV/DEC2014,APRIL/MAY2015,MAY/JUNE
2. 2016,NOV/DEC2017) (Page.No:303-324)

Explain how the instruction pipeline works. What are the various situations C204.3 BTL5
where an instruction pipeline can stall? Illustration with an example?
3. NOV/DEC 2015,NOV/DEC 2016.( Page.No:301-302)
 Explain data path in detail(NOV/DEC 14,NOV/DEC2017) C204.3 BTL5
4.
( Page.No:251-259)

5. Explain dynamic branch prediction .( Page.No:321-323) C204.3 BTL5

Explain in detail How exceptions are handled in MIPS architecture. C204.3 BTL5
6.
(APRIL/MAY2015) .( Page.No:325-332)

Explain in detail about building a datapath(NOV/DEC2014 C204.3 BTL5

7.
( Page.No:251-259)

Explain in detail about control implementation scheme(APR/MAY 2018) C204.3 BTL5

8.
( Page.No:259-271)

What is pipelining?Discuss about pipelined datapath and C204.3 BTL6

9.
control(16)MAY/JUNE2016 ( Page.No :286-303)

C204.3 BTL3
10. Why is branch prediction algorithm needed?Differentiate between static
and dynamic techniques?NOV/DEC 2016 .( Page.No:321-323)

Design a simple path with control implementation and explain in C204.3 BTL6
11.
detail(MAY/JUN 2018) ( Page.No:251-271)

Discuss the limitation in implementing the processor path. Suggest the C204.3 BTL6
12.
methods to overcome them(NOV/DEC 2018) (Refer notes)

13. When processor designers consider a possible improvement to the processor C204.3 BTL5

datapath, the decision usually depends on the cost/performance trade-off .

In

the following three problems, assume that we are starting with a datapath

where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have

latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps,
respectively,and costs of 1000, 30, 10, 100, 200, 2000, and 500,
respectively.Consider the addition of a multiplier to the ALU. Th is addition
will add 300 ps to the latency of the ALU and will add a cost of 600 to the
ALU. Th e result will be 5% fewer instructions executed since we will no
longer need to emulate the MUL instruction.
 1 What is the clock cycle time with and without this improvement?

2 What is the speedup achieved by adding this improvement?

3 Compare the cost/performance ratio with and without this improvement.

(Refer notes)

For the problems in this exercise, assume that there are no pipeline stalls C204.3 BTL3
and that the breakdown of executed instructions is as follows:

add addi not beq lw sw

20% 20% 0% 25% 25% 10%

14.
14.1 In what fraction of all cycles is the data memory used?

14.2 In what fraction of all cycles is the input of the sign-extend

circuit needed? What is this circuit doing in cycles in which its input is not
needed? (Refer notes)

Consider the following loop. C204.3 BTL3

loop:lw r1,0(r1)

and r1,r1,r2

lw r1,0(r1)
15. lw r1,0(r1)

beq r1,r0,loop

Assume that perfect branch prediction is used (no stalls due to control
hazards),that there are no delay slots, and that the pipeline has full
forwarding support. Also assume that many iterations of this loop are
executed before the loop exits. (Refer notes)