📘 Instruction Format – Complete Theory with Types (Full Marks
Answer)
✅ Definition of Instruction Format
An Instruction Format is the layout or structure of bits in a computer instruction. It defines how the CPU
decodes, fetches, and executes operations using the instruction set.\ Each instruction typically contains:
• Operation code (Opcode): Specifies the operation to perform.
• Operand(s): Specifies the data or memory/registers on which operation is to be performed.
• Addressing mode bits: Indicates the method to locate the operand.
• Other control bits (e.g., mode, flags, etc.)
🔩 Components of Instruction Format
1. Opcode (Operation Code)
This field identifies the operation to be performed (e.g., ADD, SUB, LOAD).
2. Operand(s)
These are the addresses or registers where data is stored or needed.
3. Mode Field
Specifies the addressing mode to interpret the operand (immediate, register, direct, etc.).
🧱 General Structure of Instruction Format:
+-------+--------+-----------+
| Mode | Opcode | Operand(s)|
+-------+--------+-----------+
• Mode: 2–3 bits typically
• Opcode: 5–8 bits
• Operand: 8–16 bits depending on architecture
1
📘 Types of Instruction Format – With Diagram + Explanation
🔹 1. Zero Address Instruction Format
Theory:\ This format has no operand field. It is used in stack-based computers. The data is already
present in the stack, and instructions like ADD , SUB use the top two values of the stack. Result is again
pushed to the stack.
Structure:
+--------+
| Opcode |
+--------+
Example:
PUSH A
PUSH B
ADD → (Adds top two stack values)
✅ Used in: Stack Machines
🔹 2. One Address Instruction Format
Theory:\ This format has one operand. The second operand is accumulator (AC) which is built-in. All
operations happen using the accumulator.
Structure:
+--------+------------+
| Opcode | Address |
+--------+------------+
Example:
LOAD A → AC ← M[A]
ADD B → AC ← AC + M[B]
STORE C → M[C] ← AC
✅ Used in: Accumulator-based processors
2
🔹 3. Two Address Instruction Format
Theory:\ This format uses two operands. The result is stored in the first operand. It is more flexible than
one-address format and commonly used in CISC architectures.
Structure:
+--------+-----------+-----------+
| Opcode | Operand1 | Operand2 |
+--------+-----------+-----------+
Example:
ADD A, B → A ← A + B
✅ Used in: Compact instructions (destructive to one operand)
🔹 4. Three Address Instruction Format
Theory:\ This format uses three operands — two sources and one destination. It is useful for complex
expressions and doesn't destroy any input value. It is powerful but needs more space in memory.
Structure:
+--------+-----------+-----------+---------------+
| Opcode | Source 1 | Source 2 | Destination |
+--------+-----------+-----------+---------------+
Example:
ADD R1, R2, R3 → R3 ← R1 + R2
✅ Used in: Expression evaluation, RISC & compiler-friendly systems
🔹 5. Register Instruction Format (R-Type)
Theory:\ This is used in RISC processors. All operands are in registers only, so no memory access is
needed. It makes instruction execution very fast.
Structure:
3
+--------+--------+--------+--------+
| Opcode | Reg1 | Reg2 | Reg3 |
+--------+--------+--------+--------+
Example:
SUB R4, R2, R1 → R1 ← R4 - R2
✅ Used in: ARM, MIPS, SPARC CPUs
📝 Final Conclusion:
Each instruction format is suited for different types of processors:
Format Type Operand Count Best For
Zero Address 0 Stack Machines
One Address 1 Accumulator Systems
Two Address 2 Compact code
Three Address 3 Expression eval
Register (R) 3 Registers Fast execution in RISC
