4.

1 The Ideal Diode 181

(a) (b)

Figure 4.5 Diode logic gates: (a) OR gate; (b) AND gate (in a positive-logic system).

notation is expressed as

Y = A+B+C

Similarly, the reader is encouraged to show that using the same logic system mentioned
above, the circuit of Fig. 4.5(b) implements the logic AND function,

Y = A·B·C

Example 4.2

Assuming the diodes to be ideal, find the values of I and V in the circuits of Fig. 4.6.

D D D D

(a) (b)

Figure 4.6 Circuits for Example 4.2.

182 Chapter 4 Diodes

Example 4.2 continued

Solution
In these circuits it might not be obvious at first sight whether none, one, or both diodes are conducting. In
such a case, we make a plausible assumption, proceed with the analysis, and then check whether we end up
with a consistent solution. For the circuit in Fig. 4.6(a), we shall assume that both diodes are conducting.
It follows that VB = 0 and V = 0. The current through D2 can now be determined from

10 − 0
ID2 = = 1 mA
10

Writing a node equation at B,

0 − (−10)
I +1 =
5

results in I = 1 mA. Thus D1 is conducting as originally assumed, and the final result is I = 1 mA and
V = 0 V.
For the circuit in Fig. 4.6(b), if we assume that both diodes are conducting, then VB = 0 and V = 0.
The current in D2 is obtained from

10 − 0
ID2 = = 2 mA
5

The node equation at B is

0 − (−10)
I +2 =
10

which yields I = −1 mA. Since this is not possible, our original assumption is not correct. We start again,
assuming that D1 is off and D2 is on. The current ID2 is given by

10 − (−10)
ID2 = = 1.33 mA
15

and the voltage at node B is

VB = −10 + 10 × 1.33 = +3.3 V

Thus D1 is reverse biased as assumed, and the final result is I = 0 and V = 3.3 V.
 4.1 The Ideal Diode 183

EXERCISES

4.4 Find the values of I and V in the circuits shown in Fig. E4.4.

(a) (b) (c) (d)

(e) (f )

Figure E4.4

Ans. (a) 2 mA, 0 V; (b) 0 mA, 5 V; (c) 0 mA, 5 V; (d) 2 mA, 0 V; (e) 3 mA, +3 V; (f) 4 mA, +1 V
4.5 Figure E4.5 shows a circuit for an ac voltmeter. It utilizes a moving-coil meter that gives a full-scale
reading when the average current flowing through it is 1 mA. The moving-coil meter has a 50-
resistance.
 4.2 Terminal Characteristics of Junction Diodes 189

4.2.2 The Reverse-Bias Region

The reverse-bias region of operation is entered when the diode voltage v is made negative.
Equation (4.1) predicts that if v is negative and a few times larger than VT (25 mV) in
magnitude, the exponential term becomes negligibly small compared to unity, and the diode
current becomes
i −IS
That is, the current in the reverse direction is constant and equal to IS . This constancy is the
reason behind the term saturation current.
Real diodes exhibit reverse currents that, though quite small, are much larger than IS .
−14 −15
For instance, a small-signal diode whose IS is on the order of 10 A to 10 A could
show a reverse current on the order of 1 nA. The reverse current also increases somewhat
with the increase in magnitude of the reverse voltage. Note that because of the very small
magnitude of the current, these details are not clearly evident on the diode i–v characteristic
of Fig. 4.8.
A large part of the reverse current is due to leakage effects. These leakage currents are
proportional to the junction area, just as IS is. Their dependence on temperature, however,
is different from that of IS . Thus, whereas IS doubles for every 5°C rise in temperature, the
corresponding rule of thumb for the temperature dependence of the reverse current is that it
doubles for every 10°C rise in temperature.

EXERCISE

4.9 The diode in the circuit of Fig. E4.9 is a large high-current device whose reverse leakage is reasonably
independent of voltage. If V = 1 V at 20°C, find the value of V at 40°C and at 0°C.

Figure E4.9

Ans. 4 V; 0.25 V
 VR = E - VK (2.5) SERIES DIODE 63
CONFIGURATIONS

VR
ID = IR = (2.6)
R

In Fig. 2.10 the diode of Fig. 2.7 has been reversed. Mentally replacing the diode with
a resistive element as shown in Fig. 2.11 will reveal that the resulting current direction
does not match the arrow in the diode symbol. The diode is in the “off” state, resulting in
the equivalent circuit of Fig. 2.12. Due to the open circuit, the diode current is 0 A and the
voltage across the resistor R is the following:
VR = IR R = ID R = (0 A)R = 0 V

VD = E
+ –
IR
ID = 0 A
+ + + +
VR VR E R VR
– – – –

FIG. 2.10 FIG. 2.11 FIG. 2.12

Reversing the diode of Fig. 2.8. Determining the state of the diode Substituting the equivalent model
of Fig. 2.10. for the “off” diode of Fig. 2.10.

The fact that VR 0 V will establish E volts across the open circuit as defined by Kirchhoff’s
voltage law. Always keep in mind that under any circumstances—dc, ac instantaneous
values, pulses, and so on—Kirchhoff’s voltage law must be satisfied!

EXAMPLE 2.4 For the series diode configuration of Fig. 2.13, determine VD, VR, and ID.

+ VD –
IR
ID Si
+ +
E 8V R 2.2 kΩ VR
– –

FIG. 2.13
Circuit for Example 2.4.

Solution: Since the applied voltage establishes a current in the clockwise direction to
match the arrow of the symbol and the diode is in the “on” state,
VD = 0.7 V
VR = E - VD = 8 V - 0.7 V = 7.3 V
VR 7.3 V
ID = IR = = 3.32 mA
R 2.2 k
64 DIODE APPLICATIONS
EXAMPLE 2.5 Repeat Example 2.4 with the diode reversed.
Solution: Removing the diode, we find that the direction of I is opposite to the arrow in
the diode symbol and the diode equivalent is the open circuit no matter which model is
employed. The result is the network of Fig. 2.14, where ID 0 A due to the open circuit.
Since VR = IR R, we have VR = (0)R = 0 V. Applying Kirchhoff’s voltage law around
the closed loop yields
E - VD - VR = 0
and VD = E - VR = E - 0 = E = 8 V

ID = 0 A
+ VD – IR = 0 A

+ +
E 8V R 2.2 kΩ VR
– –

FIG. 2.14
Determining the unknown quantities for
Example 2.5.

In particular, note in Example 2.5 the high voltage across the diode even though it is an
“off” state. The current is zero, but the voltage is significant. For review purposes, keep the
following in mind for the analysis to follow:
An open circuit can have any voltage across its terminals, but the current is always 0 A.
A short circuit has a 0-V drop across its terminals, but the current is limited only by the
surrounding network.
In the next example the notation of Fig. 2.15 will be employed for the applied voltage. It
is a common industry notation and one with which the reader should become very familiar.
Such notation and other defined voltage levels are treated further in Chapter 4.

E = + 10 V +10 V E = –5 V –5 V
+ –
E 10 V E 5V
– +

FIG. 2.15
Source notation.

+0.5 V
ID
+ EXAMPLE 2.6 For the series diode configuration of Fig. 2.16, determine VD, VR, and ID.
Si VD
– Solution: Although the “pressure” establishes a current with the same direction as the
+ arrow symbol, the level of applied voltage is insufficient to turn the silicon diode “on.”
R 1.2 kΩ VR The point of operation on the characteristics is shown in Fig. 2.17, establishing the open-
– circuit equivalent as the appropriate approximation, as shown in Fig. 2.18. The resulting
voltage and current levels are therefore the following:
ID = 0 A
FIG. 2.16
Series diode circuit for VR = IR R = ID R = (0 A) 1.2 k = 0V
Example 2.6. and VD = E = 0.5 V
 SERIES DIODE 65
CONFIGURATIONS
+0.5 V
ID = 0 mA
+
VD = 0.5 V
–
+
R VR = 0 V
–

FIG. 2.17 FIG. 2.18

Operating point with E 0.5 V. Determining I D, VR, and VD for
the circuit of Fig. 2.16.

EXAMPLE 2.7 Determine Vo and ID for the series circuit of Fig. 2.19.
Solution: An attack similar to that applied in Example 2.4 will reveal that the resulting
current has the same direction as the arrowheads of the symbols of both diodes, and the
network of Fig. 2.20 results because E 12 V (0.7 V 1.8 V [Table 1.8]) 2.5 V.
Note the redrawn supply of 12 V and the polarity of Vo across the 680- resistor. The
resulting voltage is
Vo = E - VK1 - VK2 = 12 V - 2.5 V = 9.5 V
VR Vo 9.5 V
and ID = IR = = = = 13.97 mA
R R 680

VK1 VK 2
Si IR + –+ –
+12 V Vo
IR
ID
red
+ ID 0.7 V 1.8 V +
680 Ω E 12 V 680 Ω Vo
– –

FIG. 2.19 FIG. 2.20

Circuit for Example 2.7. Determining the unknown quantities for
Example 2.7.

EXAMPLE 2.8 Determine ID, VD2, and Vo for the circuit of Fig. 2.21.
Solution: Removing the diodes and determining the direction of the resulting current I
result in the circuit of Fig. 2.22. There is a match in current direction for one silicon diode
but not for the other silicon diode. The combination of a short circuit in series with an open
circuit always results in an open circuit and ID 0 A, as shown in Fig. 2.23.

+ VD
2
–
Si Si
+20 V Vo
IR
ID + I + + +
5.6 kΩ E R 5.6 kΩ Vo Vo
– – – –

FIG. 2.21 FIG. 2.22 FIG. 2.23

Circuit for Example 2.8. Determining the state of the diodes Substituting the equivalent state for
of Fig. 2.21. the open diode.
66 DIODE APPLICATIONS VD 1 = 0 V
I= 0 A

ID 1 = 0 A +
Vo
–

FIG. 2.24
Determining the unknown quantities for the
circuit of Example 2.8.

The question remains as to what to substitute for the silicon diode. For the analysis to
follow in this and succeeding chapters, simply recall for the actual practical diode that when
ID 0 A, VD 0 V (and vice versa), as described for the no-bias situation in Chapter 1.
The conditions described by ID 0 A and VD1 = 0 V are indicated in Fig. 2.24. We have
Vo = IR R = ID R = (0 A)R = 0 V
and VD2 = Vopen circuit = E = 20 V
Applying Kirchhoff’s voltage law in a clockwise direction gives
E - VD1 - VD2 - Vo = 0
and VD2 = E - VD1 - Vo = 20 V - 0 - 0
= 20 V
with Vo = 0 V

EXAMPLE 2.9 Determine I, V1, V2, and Vo for the series dc configuration of Fig. 2.25.

+ V1 –
R1
E1 = 10 V Vo
4.7 kΩ Si I
+
R2 2.2 kΩ V2
–

E2 = –5 V

FIG. 2.25
Circuit for Example 2.9.

Solution: The sources are drawn and the current direction indicated as shown in Fig. 2.26.
The diode is in the “on” state and the notation appearing in Fig. 2.27 is included to indicate
this state. Note that the “on” state is noted simply by the additional VD 0.7 V on the
figure. This eliminates the need to redraw the network and avoids any confusion that may

R1 R1

R2

FIG. 2.26 FIG. 2.27

Determining the state of the diode for the Determining the unknown quantities for the network
network of Fig. 2.25. of Fig. 2.25. KVL, Kirchhoff voltage loop.
result from the appearance of another source. As indicated in the introduction to this sec- PARALLEL AND 67
tion, this is probably the path and notation that one will take when a level of confidence SERIES–PARALLEL
CONFIGURATIONS
has been established in the analysis of diode configurations. In time the entire analysis will
be performed simply by referring to the original network. Recall that a reverse-biased
diode can simply be indicated by a line through the device.
The resulting current through the circuit is
E1 + E2 - VD 10 V + 5 V - 0.7 V 14.3 V
I = = =
R1 + R2 4.7 k + 2.2 k 6.9 k
2.07 mA
and the voltages are
V1 = IR1 = (2.07 mA)(4.7 k ) = 9.73 V
V2 = IR2 = (2.07 mA)(2.2 k ) = 4.55 V
Applying Kirchhoff’s voltage law to the output section in the clockwise direction results in
- E2 + V2 - Vo = 0
and Vo = V2 - E2 = 4.55 V - 5 V = 0.45 V
The minus sign indicates that Vo has a polarity opposite to that appearing in Fig. 2.25.

2.4 PARALLEL AND SERIES–PARALLEL

CONFIGURATIONS
●
The methods applied in Section 2.3 can be extended to the analysis of parallel and series–
parallel configurations. For each area of application, simply match the sequential series of
steps applied to series diode configurations.

EXAMPLE 2.10 Determine Vo, I1, ID1, and ID2 for the parallel diode configuration of Fig. 2.28.

I1 0.33 kΩ
ID ID
+
R 1 2
+
E 10 V D1 Si D2 Si Vo
–
–

FIG. 2.28 FIG. 2.29

Network for Example 2.10. Determining the unknown quantities for
the network of Example 2.10.

Solution: For the applied voltage the “pressure” of the source acts to establish a current
through each diode in the same direction as shown in Fig. 2.29. Since the resulting current
direction matches that of the arrow in each diode symbol and the applied voltage is greater
than 0.7 V, both diodes are in the “on” state. The voltage across parallel elements is always
the same and
Vo = 0.7 V
The current is
VR E - VD 10 V - 0.7 V
I1 = = = = 28.18 mA
R R 0.33 k
Assuming diodes of similar characteristics, we have
I1 28.18 mA
ID1 = ID2 = = = 14.09 mA
2 2
68 DIODE APPLICATIONS This example demonstrates one reason for placing diodes in parallel. If the current rat-
ing of the diodes of Fig. 2.28 is only 20 mA, a current of 28.18 mA would damage the
device if it appeared alone in Fig. 2.28. By placing two in parallel, we limit the current to
a safe value of 14.09 mA with the same terminal voltage.
+8 V

R EXAMPLE 2.11 In this example there are two LEDs that can be used as a polarity detec-
tor. Apply a positive source voltage and a green light results. Negative supplies result in a
red light. Packages of such combinations are commercially available.
Find the resistor R to ensure a current of 20 mA through the “on” diode for the configu-
Red Green ration of Fig. 2.30. Both diodes have a reverse breakdown voltage of 3 V and an average
turn-on voltage of 2 V.
Solution: The application of a positive supply voltage results in a conventional current
that matches the arrow of the green diode and turns it on.
The polarity of the voltage across the green diode is such that it reverse biases the red
FIG. 2.30 diode by the same amount. The result is the equivalent network of Fig. 2.31.
Network for Example 2.11. Applying Ohm’s law, we obtain
E - VLED 8V - 2V
I = 20 mA = =
R R
+8 V
20 mA 6V
and R = = 300
20 mA
R Note that the reverse breakdown voltage across the red diode is 2 V, which is fine for an
LED with a reverse breakdown voltage of 3 V.
However, if the green diode were to be replaced by a blue diode, problems would
+ develop, as shown in Fig. 2.32. Recall that the forward bias required to turn on a blue diode
2V
is about 5 V. The result would appear to require a smaller resistor R to establish the current
– of 20 mA. However, note that the reverse bias voltage of the red LED is 5 V, but the
reverse breakdown voltage of the diode is only 3 V. The result is the voltage across the red
LED would lock in at 3 V as shown in Fig. 2.33. The voltage across R would be 5 V and
the current limited to 20 mA with a 250 resistor but neither LED would be on.
FIG. 2.31
Operating conditions for the
network of Fig. 2.30. +8 V +8 V

R –3 V R
0 V2 V

+ + +
5 V > Vr 5V 3V
– max
– –

FIG. 2.32 FIG. 2.33

Network of Fig. 2.31 Demonstrating damage to the red LED if the
with a blue diode. reverse breakdown voltage is exceeded.

A simple solution to the above is to add the appropriate resistance level in series with
each diode to establish the desired 20 mA and to include another diode to add to the
reverse-bias total reverse breakdown voltage rating, as shown in Fig. 2.34. When the blue
LED is on, the diode in series with the blue LED will also be on, causing a total voltage
drop of 5.7 V across the two series diodes and a voltage of 2.3 V across the resistor R1,
establishing a high emission current of 19.17 mA. At the same time the red LED diode and
 8V PARALLEL AND 69
SERIES–PARALLEL
CONFIGURATIONS
IR = 8 V – 5.7 V = 19.17 mA
1
120 Ω

R2 120 Ω R1 120 Ω (standard value)

+ +
Si Si 0.7 V
–
Blue + 5.7 V
Red
5V
– –

FIG. 2.34
Protective measure for the red LED of Fig. 2.33.

its series diode will also be reverse biased, but now the standard diode with a reverse
breakdown voltage of 20 V will prevent the full reverse-bias voltage of 8 V from appear-
ing across the red LED. When forward biased, the resistor R2 will establish a current of
19.63 mA to ensure a high level of intensity for the red LED.

12 V
EXAMPLE 2.12 Determine the voltage Vo for the network of Fig. 2.35.
Solution: Initially, it might appear that the applied voltage will turn both diodes “on”
because the applied voltage (“pressure”) is trying to establish a conventional current
through each diode that would suggest the “on” state. However, if both were on, there Si green
would be more than one voltage across the parallel diodes, violating one of the basic rules
of network analysis: The voltage must be the same across parallel elements.
The resulting action can best be explained by remembering that there is a period of Vo
build-up of the supply voltage from 0 V to 12 V even though it may take milliseconds or
2.2 kΩ
microseconds. At the instant the increasing supply voltage reaches 0.7 V the silicon diode will
turn “on” and maintain the level of 0.7 V since the characteristic is vertical at this voltage—the
current of the silicon diode will simply rise to the defined level. The result is that the volt-
age across the green LED will never rise above 0.7 V and will remain in the equivalent
open-circuit state as shown in Fig. 2.36.
FIG. 2.35
The result is
Network for Example 2.12.
Vo = 12 V - 0.7 V = 11.3 V

FIG. 2.36
Determining Vo for the network of
Fig. 2.35.
70 DIODE APPLICATIONS
EXAMPLE 2.13 Determine the currents I1, I2, and ID2 for the network of Fig. 2.37.

R1
Si 3.3kΩ I1

D1
+
E 20 V Si D2
– ID 2
I2 R2

5.6 kΩ

FIG. 2.37 FIG. 2.38

Network for Example 2.13. Determining the unknown quantities for
Example 2.13.

Solution: The applied voltage (pressure) is such as to turn both diodes on, as indicated
by the resulting current directions in the network of Fig. 2.38. Note the use of the abbrevi-
ated notation for “on” diodes and that the solution is obtained through an application of
techniques applied to dc series–parallel networks. We have
VK2 0.7 V
I1 = = = 0.212 mA
R1 3.3 k
Applying Kirchhoff’s voltage law around the indicated loop in the clockwise direction
yields
-V2 + E - VK1 - VK2 = 0
and V2 = E - VK1 - VK2 = 20 V - 0.7 V - 0.7 V = 18.6 V
V2 18.6 V
with I2 = = = 3.32 mA
R2 5.6 k
At the bottom node a,
ID2 + I1 = I2
and ID2 = I2 - I1 = 3.32 mA - 0.212 mA 3.11 mA

2.5 AND/OR GATES

Si
●
The tools of analysis are now at our disposal, and the opportunity to investigate a computer
(1) E = 10 V configuration is one that will demonstrate the range of applications of this relatively sim-
1 D1
ple device. Our analysis will be limited to determining the voltage levels and will not
Si include a detailed discussion of Boolean algebra or positive and negative logic.
(0) 0V Vo The network to be analyzed in Example 2.14 is an OR gate for positive logic. That is, the
2 D2 10-V level of Fig. 2.39 is assigned a “1” for Boolean algebra and the 0-V input is assigned
a “0.” An OR gate is such that the output voltage level will be a 1 if either or both inputs is
R 1 kΩ a 1. The output is a 0 if both inputs are at the 0 level.
The analysis of AND/OR gates is made easier by using the approximate equivalent for
a diode rather than the ideal because we can stipulate that the voltage across the diode must
be 0.7 V positive for the silicon diode to switch to the “on” state.
FIG. 2.39 In general, the best approach is simply to establish a “gut” feeling for the state of the
Positive logic OR gate. diodes by noting the direction and the “pressure” established by the applied potentials. The
analysis will then verify or negate your initial assumptions.

EXAMPLE 2.14 Determine Vo for the network of Fig. 2.39.

Solution: First note that there is only one applied potential; 10 V at terminal 1. Terminal 2
with a 0-V input is essentially at ground potential, as shown in the redrawn network of
2.3 Series Diode Configurations PROBLEMS 121
5. Determine the current I for each of the configurations of Fig. 2.155 using the approximate
equivalent model for the diode.

–
+
I
+ –

(a)

(b) (c)

FIG. 2.155
Problem 5.

6. Determine Vo and ID for the networks of Fig. 2.156.

ID

Vo Vo

ID

–6 V
(a) (b)

FIG. 2.156
Problems 6 and 49.

*7. Determine the level of Vo for each network of Fig. 2.157.

12 V

10 k

10 V

(a) (b)

FIG. 2.157
Problem 7.

*8. Determine Vo and ID for the networks of Fig. 2.158.

Vo

2.2 k
–20 V

(a) (b)

FIG. 2.158
Problem 8.
122 DIODE APPLICATIONS *9. Determine Vo1 and Vo2 for the networks of Fig. 2.159.

GaAs kΩ

(a) (b)

FIG. 2.159
Problem 9.

2.4 Parallel and Series–Parallel Configurations

10. Determine Vo and ID for the networks of Fig. 2.160.

20 V

12 V
Ge

GaAs

4V
(a) (b)

FIG. 2.160
Problems 10 and 50.

*11. Determine Vo and I for the networks of Fig. 2.161.

1V

GaAs

–4 V
(a) (b)

FIG. 2.161
Problem 11.

12. Determine Vo1, Vo2, and I for the network of Fig. 2.162.
*13. Determine Vo and ID for the network of Fig. 2.163.
 PROBLEMS 123

+
Si
– GaAs

FIG. 2.162 FIG. 2.163

Problem 12. Problems 13 and 51.

2.5 AND/OR Gates

14. Determine Vo for the network of Fig. 2.39 with 0 V on both inputs.
15. Determine Vo for the network of Fig. 2.39 with 10 V on both inputs.
16. Determine Vo for the network of Fig. 2.42 with 0 V on both inputs.
17. Determine Vo for the network of Fig. 2.42 with 10 V on both inputs.
18. Determine Vo for the negative logic OR gate of Fig. 2.164.
19. Determine Vo for the negative logic AND gate of Fig. 2.165.

–5 V –5 V

Si Si

0V 0V
Vo Vo
Si Si

1 kΩ 2.2 kΩ

–5 V

FIG. 2.164 FIG. 2.165

Problem 18. Problem 19.

20. Determine the level of Vo for the gate of Fig. 2.166.

21. Determine Vo for the configuration of Fig. 2.167.

FIG. 2.166 FIG. 2.167

Problem 20. Problem 21.

2.6 Sinusoidal Inputs; Half-Wave Rectification

22. Assuming an ideal diode, sketch vi, vd, and id for the half-wave rectifier of Fig. 2.168. The
input is a sinusoidal waveform with a frequency of 60 Hz. Determine the profit value of vi from
the given dc level.
23. Repeat Problem 22 with a silicon diode (VK 0.7 V).
24. Repeat Problem 22 with a 10 k load applied as shown in Fig. 2.169. Sketch vL and iL.