Input/Output
+ Shatabdi Roy Moon
Lecturer
Department of CSE
East West University
Address L ines
System
Data L ines Bus
C ontrol L ines
I/O Module
L inks to
peripheral
devices
Figure 7.1 Generic Model of an I/O Module
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n Provide a means of exchanging
d a t a b e t we e n t h e ex t e r n a l
environment and the computer
n Human readable
n Attach to the computer by a n Suitable for communicating with
the computer user
link to an I/O module n Video display terminals (VDTs),
n The link is used to exchange printers
control, status, and data between
the I/O module and the external n Machine readable
device n Suitable for communicating with
equipment
n Magnetic disk and tape systems,
n Peripheral device sensors and actuators
n An external device connected to
an I/O module n Communication
n Suitable for communicating with
remote devices such as a terminal,
a machine-readable device, or
another computer
Interface to Interface to
System Bus E xternal Device
Data
Data Registers E xternal
Device
Data Status
Interface
L ines
L ogic
Status/Control Registers Control
Address
L ines Data
E xternal
I/O Device
L ogic Status
Interface
Control L ogic
L ines Control
Figure 7.3 Block Diagram of an I/O Module
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n Figure 7.3 provides a general block diagram of an I/O module. The
module connects to the rest of the computer through a set of signal lines
(e.g., system bus lines). Data transferred to and from the module are
buffered in one or more data registers. There may also be one or more
status registers that provide current status information. A status register
may also function as a control register, to accept detailed control
information from the processor. The logic within the module interacts with
the processor via a set of control lines. The processor uses the control
lines to issue commands to the I/O module. Some of the control lines may
be used by the I/O module. The module must also be able to recognize
and generate addresses associated with the devices it controls. Each I/O
module has a unique address or, if it controls more than one external
device, a unique set of addresses. Finally, the I/O module contains logic
specific to the interface with each device that it controls.
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n There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:
1) Control
- used to activate a peripheral and tell it what to do
2) Test
- used to test various status conditions associated with an I/O
module and its peripherals
3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer
4) Write
- causes the I/O module to take an item of data from the data bus
and subsequently transmit that data item to the peripheral
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Three techniques are possible for I/O operations:
n Programmed I/O
n Interrupt driven I/O
n Direct memory access (DMA)
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n The computer executes a program to communicate with an external
device via a register called the I/O port for programmed I/O.
n I/O ports are usually of two types. For one type, each bit in the port can
be individually configured as either input or output.
n For the other type, all bits in the port can be set up as either all parallel
input or output bits. Each port can be configured as an input or output
port by another register called the command or data-direction register.
n The data direction register is an output register and can be used to
configure the bits in the port as inputs or outputs.
n Each bit in the port can be set up as an input or output by writing a 0 or
1 in the corresponding bit of the data direction register.
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n If an 8-bit data-direction register 00110100, then the corresponding port is defined as
in the following figure:
n Here bits 0,1,3,6 and 7, of the port are set up as inputs and bits 2,4 and 5 of the port are
defined as outputs.
n For parallel I/O, there is only one data-direction register known as the command
register for all ports.
n A particular bit in the command register configures all bits in the port as either inputs
or outputs.
n A 0 or 1 in the particular bit position defines all bits of ports A or B as inputs or outputs.
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0
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n An external device requests the computer to transfer data by activating
a signal on the computer’s interrupt line during interrupt I/O. In
response, the computer executes a program called the interrupt-service
routine (ISR) to carry out the function desired by the external device.
n Interrupt I/O is a device-initiated I/O transfer. The external device is
connected to a pin called the interrupt (INT) pin on the processor chip.
n When the device needs an I/O transfer with the computer, it activates
the interrupt pin of the processor chip.
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n DMA is a method that allows an input/output (I/O) device to send or
receive data directly to or from the main memory, bypassing the CPU to
speed up memory operations.
n The process is managed by a chip known as a DMA controller (DMAC).
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n DMA is a technique that transfers data between a computer’s memory and I/O
device without involving the CPU.
n DMA is widely used in transferring large blocks of data between a peripheral
device and the computer’s memory.
n The DMA technique uses a DMA controller chip for the data transfer operation.
n Main functions of DMA controller:
n The I/O devices request DMA operation via the DMA request line of the
controller chip.
n The controller chip activates the CPU HOLD pin, requesting the CPU to
release the bus.
n The processor sends HLDA (Hold acknowledge) back to the DMA controller,
indicating the bus is disabled. The DMA controller completes the DMA
transfer.
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n The I/O device asserts DRQ signal
n DMA controller send HOLD signal to microprocessor
n Microprocessor Send HLDA to DMA Controller & DMA takes charge
of the system buses
n DMA give DMA ACK signal to I/O devices
n Now, DMA controller places memory address on address bus and
data bytes from memory transfer to I/O .
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n First what happens is I/O device sends the DMA request to DMA Controller,
then further DMAC device sends HOLD signal to CPU by which it asks CPU
for several information which are needed while transferring data.
n CPU then shares two basic information with DMAC before the Data transfer:
n Starting address (memory address starting from where data transfer
should be performed)
n Data Count (no of bytes or words to be transferred).
n CPU then sends HLDA (Hold Acknowledgement) back to DMAC illustrating
that now DMAC can successfully pass on the information.
n Then further DMAC shares the DACK (DMA Acknowledgement) to the I/O
device which would eventually let I/O device to access or transfer the data
from memory in a direct and efficient manner.
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n The DMA Controller has several options available for the transfer of data.
n Types of DMA:
1. Block Transfer or Burst Transfer DMA
2. Cycle Stealing DMA
3. Interleaved or Hidden DMA
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n In this mode, Burst of data (entire data or burst of block containing data) is
transferred before CPU takes control of the buses back from DMA controller.
n This is the quickest mode of DMA Transfer since at once a huge amount of
data is being transferred.
n Since at once only the huge amount of data is being transferred so time will
be saved in huge amount.
Pros:
n Fastest mode of DMA Transfer
Cons:
n Less user friendly because during the DMA transfer CPU will be blocked.
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n Slow I/O device will take some time to prepare data (or word) and
within that time CPU keeps the control of the buses.
n Once the data or the word is ready CPU give back control of system
buses to DMA controller for 1-cycle in which the prepared word is
transferred to memory.
n As compared to Burst mode, this mode is little bit slower since it
requires little bit of time which is actually consumed by I/O device
while preparing the data.
Pros:
n Most Efficient way for DMA Transfer.
Cons:
n Rate of DMA Transfer will be less.
n CPU won’t be blocked entire time.
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n A DMA controller transfers 16 bits words to memory using
cycle stealing .The words are assembled from a device that
transmit characters at an average rate of 2400 characters/sec.
The CPU fetching instructions at an average rate of 1 Million
instructions/sec. By how much will the CPU be slowed down
because of DMA transfer ( Eash character is 8 bits)
10^6 --------1 sec
1 ---------1/10^6 =1 micro sec
2400 ------- 1 sec
1 --------1/2400 sec
2 --------2/2400 sec = 1/1200 sec =833.3 micro sec
1/833.3 = .0012 =12%
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n Whenever CPU does not require the system buses then only
control of buses will be given to the DMA controller.
n In this mode, CPU will not be blocked due to DMA at all.
n This is the slowest mode of DMA Transfer since DMA controller
might have to wait for a long time to just get the access of system
buses from the CPU itself.
n Less amount of data will be transferred.
Pros:
n CPU will not be blocked at all.
Cons:
n Slowest DMA transfer rate.
