0% found this document useful (0 votes)

10 views74 pages

C 5 Sim

The System Integration Module (SIM) consists of six functional blocks that manage system configuration, clock generation, protection, external bus interfacing, chip-select signals, and testing. The SIM configuration register (SIMCR) controls various operational aspects, including module mapping, interrupt arbitration, and access levels. Additionally, the system clock synthesizes timing signals from internal or external sources, with specific configurations affecting clock frequency and stability.

Uploaded by

Chris

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

10 views74 pages

C 5 Sim

Uploaded by

Chris

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 74

SECTION 5

SYSTEM INTEGRATION MODULE

This section is an overview of the system integration module (SIM) function. Refer to
the SIM Reference Manual (SIMRM/AD) for a comprehensive discussion of SIM
capabilities. Refer to APPENDIX D REGISTER SUMMARY for information concern-
ing the SIM address map and register structure.

5.1 General
The SIM consists of six functional blocks. Figure 5-1 shows a block diagram of the
SIM.

The system configuration block controls MCU configuration parameters.

The system clock generates clock signals used by the SIM, other IMB modules, and
external devices.

The system protection block provides bus and software watchdog monitors. In addi-
tion, it also provides a periodic interrupt timer to support execution of time-critical
control routines.

The external bus interface handles the transfer of information between IMB modules
and external address space.

The chip-select block provides 12 chip-select signals. Each chip-select signal has an
associated base address register and option register that contain the programmable
characteristics of that chip-select.

The system test block incorporates hardware necessary for testing the MCU. It is used
to perform factory tests, and its use in normal applications is not supported.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-1
SYSTEM CONFIGURATION

XTAL
CLKOUT
CLOCK SYNTHESIZER EXTAL
MODCLK

SYSTEM PROTECTION

CHIP-SELECTS CHIP-SELECTS

EXTERNAL BUS
EXTERNAL BUS INTERFACE
RESET

TSTME/TSC
FACTORY TEST
FREEZE/QUOT

300 S(C)IM BLOCK

Figure 5-1 System Integration Module Block Diagram

5.2 System Configuration

The SIM configuration register (SIMCR) governs several aspects of system operation.
The following paragraphs describe those configuration options controlled by SIMCR.

5.2.1 Module Mapping

Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping bit (MM) in the SIM configuration register
(SIMCR) determines where the control register block is located in the system memory
map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when MM
= 1, register addresses range from $FFF000 to $FFFFFF.

5.2.2 Interrupt Arbitration

Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbi-
tration between interrupt requests of the same priority is performed by serial
contention between IARB field bit values. Contention must take place whenever an
interrupt request is acknowledged, even when there is only a single request pending.
For an interrupt to be serviced, the appropriate IARB field must have a non-zero value.
If an interrupt request from a module with an IARB field value of %0000 is recognized,
the CPU32 processes a spurious interrupt exception.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-2
Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field
value is used for arbitration between internal and external interrupts of the same prior-
ity. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other
modules is %0000, which prevents SIM interrupts from being discarded during initial-
ization. Refer to 5.8 Interrupts for a discussion of interrupt arbitration.

5.2.3 Show Internal Cycles

A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in SIMCR determines what the external bus interface does during internal transfer
operations. Table 5-1 shows whether data is driven externally, and whether external
bus arbitration can occur. Refer to 5.6.6.1 Show Cycles for more information.

Table 5-1 Show Cycle Enable Bits

SHEN[1:0] Action
00 Show cycles disabled, external arbitration enabled
01 Show cycles enabled, external arbitration disabled
10 Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
11
internal activity is halted by a bus grant

5.2.4 Register Access

The CPU32 can operate at one of two privilege levels. Supervisor level is more privi-
leged than user level — all instructions and system resources are available at
supervisor level, but access is restricted at user level. Effective use of privilege level
can protect system resources from uncontrolled access. The state of the S bit in the
CPU status register determines access level, and whether the user or supervisor stack
pointer is used for stacking operations. The SUPV bit places SIM global registers in
either supervisor or user data space. When SUPV = 0, registers with controlled access
are accessible from either the user or supervisor privilege level; when SUPV = 1, reg-
isters with controlled access are restricted to supervisor access only.

5.2.5 Freeze Operation

The FREEZE signal halts MCU operations during debugging. FREEZE is asserted
internally by the CPU32 if a breakpoint occurs while background mode is enabled.
When FREEZE is asserted, only the bus monitor, software watchdog, and periodic
interrupt timer are affected. The halt monitor and spurious interrupt monitor continue
to operate normally. Setting the freeze bus monitor (FRZBM) bit in SIMCR disables the
bus monitor when FREEZE is asserted. Setting the freeze software watchdog
(FRZSW) bit disables the software watchdog and the periodic interrupt timer when
FREEZE is asserted.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-3
5.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an
external peripheral bus. Because the MCU is a fully static design, register and memory
contents are not affected when the clock rate changes. System hardware and software
support changes in clock rate during operation.

The system clock signal can be generated from one of two sources. An internal phase-
locked loop (PLL) can synthesize the clock from a slow reference, or the clock signal
can be directly input from an external frequency source. The slow reference is typically
a32.768 kHz crystal, but may be generated by sources other than a crystal. Keep
these sources in mind while reading the rest of this section. Refer to APPENDIX A
ELECTRICAL CHARACTERISTICS for clock specifications.

Figure 5-2 is a block diagram of the clock submodule.

MODCLK EXTAL XTAL XFC VDDSYN CLKOUT

CRYSTAL
÷ 128 PHASE LOW-PASS
OSCILLATOR VCO
COMPARATOR FILTER

W
FEEDBACK DIVIDER
Y

X
SYSTEM CLOCK CONTROL

SYSTEM
CLOCK

16/32 PLL BLOCK 4M

Figure 5-2 System Clock Block Diagram

5.3.1 Clock Sources

The state of the clock mode (MODCLK) pin during reset determines the system clock
source. When MODCLK is held high during reset, the clock synthesizer generates a
clock signal from an external reference frequency. The clock synthesizer control reg-
ister (SYNCR) determines operating frequency and mode of operation. When
MODCLK is held low during reset, the clock synthesizer is disabled and an external
system clock signal must be driven onto the EXTAL pin.

The input clock is referred to as fref, and can be either a crystal or an external clock
source. The output of the clock system is referred to as fsys. Ensure that fref and fsys
are within normal operating limits.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-4
To generate a reference frequency using the crystal oscillator, a reference crystal must
be connected between the EXTAL and XTAL pins. Typically, a 32.768 kHz crystal is
used, but the frequency may vary between 25 kHz to 50 kHz. Figure 5-3 shows a typ-
ical circuit.

C1
22 pF* R1
330K
XTAL
R2
10M
EXTAL
C2
22 pF*

VSSI

*RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-KHZ CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
32 OSCILLATOR

Figure 5-3 System Clock Oscillator Circuit

If a slow reference frequency is provided to the PLL from a source other than a crystal,
or an external system clock signal is applied through the EXTAL pin, the XTAL pin
must be left floating.

When an external system clock signal is applied (MODCLK = 0 during reset), the PLL
is disabled. The duty cycle of this signal is critical, especially at operating frequencies
close to maximum. The relationship between clock signal duty cycle and clock signal
period is expressed as follows:

Minimum External Clock Period =

Minimum External Clock High/Low Time
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
50% – Percentage Variation of External Clock Input Duty Cycle

5.3.2 Clock Synthesizer Operation

VDDSYN is used to power the clock circuits when the system clock is synthesized from
either a crystal or an externally supplied reference frequency. A separate power
source increases MCU noise immunity and can be used to run the clock when the
MCU is powered down. A quiet power supply must be used as the VDDSYN source.
Adequate external bypass capacitors should be placed as close as possible to the
VDDSYN pin to assure a stable operating frequency. When an external system clock
signal is applied and the PLL is disabled, VDDSYN should be connected to the VDD sup-
ply. Refer to the SIM Reference Manual (SIMRM/AD) for more information regarding
system clock power supply conditioning.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-5
A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To
maintain a 50% clock duty cycle, the VCO frequency (fVCO) is either two or four times
the system clock frequency, depending on the state of the X bit in SYNCR. The clock
signal is fed back to a divider/counter. The divider controls the frequency of one input
to a phase comparator. The other phase comparator input is a reference signal, either
from the crystal oscillator or from an external source. The comparator generates a con-
trol signal proportional to the difference in phase between the two inputs. This signal
is low-pass filtered and used to correct the VCO output frequency.

Filter circuit implementation can vary, depending upon the external environment and
required clock stability. Figure 5-4 shows two recommended system clock filter
networks. XFC pin leakage must be kept as low as possible to maintain optimum sta-
bility and PLL performance.

An external filter network connected to the XFC pin is not required when an external
system clock signal is applied and the PLL is disabled (MODCLK = 0 at reset). The
XFC pin must be left floating in this case.

C3 C1 C3 C1 R1
0.1 µF 0.1 µF 0.1 µF 0.1 µF 18 kΩ
XFC1 XFC1, 2

VDDSYN
C4 C4 C2
0.01 µF 0.01 µF 0.01 µF
VDDSYN
VSS VSS

NORMAL OPERATING ENVIRONMENT HIGH-STABILITY OPERATING ENVIRONMENT

1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION.
2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE.
NORMAL/HIGH-STABILITY XFC CONN

Figure 5-4 System Clock Filter Networks

The synthesizer locks when the VCO frequency is equal to fref. Lock time is affected
by the filter time constant and by the amount of difference between the two comparator
inputs. Whenever a comparator input changes, the synthesizer must relock. Lock sta-
tus is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come
out of reset until the synthesizer locks. Crystal type, characteristic frequency, and lay-
out of external oscillator circuitry affect lock time.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-6
When the clock synthesizer is used, SYNCR determines the system clock frequency
and certain operating parameters. The W and Y[5:0] bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. When the W or
Y values change, VCO frequency changes, and there is a VCO relock delay. The
SYNCR X bit controls a divide-by circuit that is not in the synthesizer feedback loop.
When X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock fre-
quency is one-fourth the VCO frequency (fVCO). When X = 1, a divide-by-two circuit is
enabled and system clock frequency is one-half the VCO frequency (fVCO). There is
no relock delay when clock speed is changed by the X bit.

Clock frequency is determined by SYNCR bit settings as follows:

( 2W + X )
f sys = 4f ref ( Y + 1 ) ( 2 )

The reset state of SYNCR ($3F00) results in a power-on fsys of 8.388 MHz when fref
is 32.768 kHz.

For the device to operate correctly, the clock frequency selected by the W, X, and Y
bits must be within the limits specified for the MCU.

Internal VCO frequency is determined by the following equations:

f VCO = 4f sys if X = 0

f VCO = 2f sys if X = 1

Tables 5-2, 5-3, and 5-4 show clock control multipliers for all possible combinations of
SYNCR bits. To obtain clock frequency, find counter modulus in the leftmost column,
then multiply the reference frequency by the value in the appropriate prescaler cell.
Shaded areas indicate which values exceed the specifications for a device rated at a
particular operating frequency. For information on the maximum allowable clock rate,
refer to APPENDIX A ELECTRICAL CHARACTERISTICS.
Tables 5-5, 5-6, and 5-7 show actual clock frequencies for the same combinations of
SYNCR bits. To obtain clock frequency, find counter modulus in the leftmost column,
then refer to appropriate prescaler cell. Shaded areas indicate which values exceed
the specifications for a device rated at a particular operating frequency. For informa-
tion on the maximum system frequency (fsys), refer to APPENDIX A ELECTRICAL
CHARACTERISTICS.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-7
Table 5-2 16.78 MHz Clock Control Multipliers
(Shaded cells represent values that exceed 16.78 MHz specifications.)

Prescalers
Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
(fVCO = 2 × Value) (fVCO = Value) (fVCO = 2 × Value) (fVCO = Value)
Y Slow Fast Slow Fast Slow Fast Slow Fast
000000 4 .03125 8 .625 16 .125 32 .25
000001 8 .0625 16 .125 32 .25 64 .5
000010 12 .09375 24 .1875 48 .375 96 .75
000011 16 .125 32 .25 64 .5 128 1
000100 20 .15625 40 .3125 80 .625 160 1.25
000101 24 .1875 48 .375 96 .75 192 1.5
000110 28 .21875 56 .4375 112 .875 224 1.75
000111 32 .25 64 .5 128 1 256 2
001000 36 .21825 72 .5625 144 1.125 288 2.25
001001 40 .3125 80 .625 160 1.25 320 2.5
001010 44 .34375 88 .6875 176 1.375 352 2.75
001011 48 .375 96 .75 192 1.5 384 3
001100 52 .40625 104 .8125 208 1.625 416 3.25
001101 56 .4375 112 .875 224 1.75 448 3.5
001110 60 .46875 120 .9375 240 1.875 480 3.75
001111 64 .5 128 1 256 2 512 4
010000 68 .53125 136 1.0625 272 2.125 544 4.25
010001 72 .5625 144 1.125 288 2.25 576 4.5
010010 76 .59375 152 1.1875 304 2.375 608 4.75
010011 80 .625 160 1.25 320 2.5 640 5
010100 84 .65625 168 1.3125 336 2.625 672 5.25
010101 88 .6875 176 1.375 352 2.75 704 5.5
010110 92 .71875 184 1.4375 368 2.875 736 5.75
010111 96 .75 192 1.5 384 3 768 6
011000 100 .78125 200 1.5625 400 3.125 800 6.25
011001 104 .8125 208 1.625 416 3.25 832 6.5
011010 108 .84375 216 1.6875 432 3.375 864 6.75
011011 112 .875 224 1.75 448 3.5 896 7
011100 116 .90625 232 1.8125 464 3.625 928 7.25
011101 120 .9375 240 1.875 480 3.75 960 7.5
011110 124 .96875 248 1.9375 496 3.875 992 7.75
011111 128 1 256 2 512 4 1024 8

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-8
Table 5-2 16.78 MHz Clock Control Multipliers (Continued)
(Shaded cells represent values that exceed 16.78 MHz specifications.)

Prescalers
Modulus [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
(fVCO = 2 × Value) (fVCO = Value) (fVCO = 2 × Value) (fVCO = Value)
Y Slow Fast Slow Fast Slow Fast Slow Fast
100000 132 1.03125 264 2.0625 528 4.125 1056 8.25
100001 136 1.0625 272 2.125 544 4.25 1088 8.5
100010 140 1.09375 280 2.1875 560 4.375 1120 8.75
100011 144 1.125 288 2.25 576 4.5 1152 9
100100 148 1.15625 296 2.3125 592 4.675 1184 9.25
100101 152 1.1875 304 2.375 608 4.75 1216 9.5
100110 156 1.21875 312 2.4375 624 4.875 1248 9.75
100111 160 1.25 320 2.5 640 5 1280 10
101000 164 1.28125 328 2.5625 656 5.125 1312 10.25
101001 168 1.3125 336 2.625 672 5.25 1344 10.5
101010 172 1.34375 344 2.6875 688 5.375 1376 10.75
101011 176 1.375 352 2.75 704 5.5 1408 11
101100 180 1.40625 360 2.8125 720 5.625 1440 11.25
101101 184 1.4375 368 2.875 736 5.75 1472 11.5
101110 188 1.46875 376 2.9375 752 5.875 1504 11.75
101111 192 1.5 384 3 768 6 1536 12
110000 196 1.53125 392 3.0625 784 6.125 1568 12.25
110001 200 1.5625 400 3.125 800 6.25 1600 12.5
110010 204 1.59375 408 3.1875 816 6.375 1632 12.75
110011 208 1.625 416 3.25 832 6.5 1664 13
110100 212 1.65625 424 3.3125 848 6.625 1696 13.25
110101 216 1.6875 432 3.375 864 6.75 1728 13.5
110110 220 1.71875 440 3.4375 880 6.875 1760 13.75
110111 224 1.75 448 3.5 896 7 1792 14
111000 228 1.78125 456 3.5625 912 7.125 1824 14.25
111001 232 1.8125 464 3.625 928 7.25 1856 14.5
111010 236 1.84375 472 3.6875 944 7.375 1888 14.75
111011 240 1.875 480 3.75 960 7.5 1920 15
111100 244 1.90625 488 3.8125 976 7.625 1952 15.25
111101 248 1.9375 496 3.875 992 7.75 1984 15.5
111110 252 1.96875 504 3.9375 1008 7.875 2016 15.75
111111 256 2 512 4 1024 8 2048 16

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-9
Table 5-3 20.97 MHz Clock Control Multipliers
(Shaded cells represent values that exceed 20.97 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-10
Table 5-3 20.97 MHz Clock Control Multipliers (Continued)
(Shaded cells represent values that exceed 20.97 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-11
Table 5-4 25.17 MHz Clock Control Multipliers
(Shaded cells represent values that exceed 25.17 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-12
Table 5-4 25.17 MHz Clock Control Multipliers (Continued)
(Shaded cells represent values that exceed 25.17 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-13
Table 5-5 16.78 MHz System Clock Frequencies
(Shaded cells represent values that exceed 16.78 MHz specifications.)

Modulus Prescaler
[W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
Y
(fVCO = 2 × Value) (fVCO = Value) (fVCO = 2 × Value) (fVCO = Value)
000000 131 kHz 262 kHz 524 kHz 1049 kHz
000001 262 524 1049 2097
000010 393 786 1573 3146
000011 524 1049 2097 4194
000100 655 1311 2621 5243
000101 786 1573 3146 6291
000110 918 1835 3670 7340
000111 1049 2097 4194 8389
001000 1180 2359 4719 9437
001001 1311 2621 5243 10486
001010 1442 2884 5767 11534
001011 1573 3146 6291 12583
001100 1704 3408 6816 13631
001101 1835 3670 7340 14680
001110 1966 3932 7864 15729
001111 2097 4194 8389 16777
010000 2228 4456 8913 17826
010001 2359 4719 9437 18874
010010 2490 4981 9961 19923
010011 2621 5243 10486 20972
010100 2753 5505 11010 22020
010101 2884 5767 11534 23069
010110 3015 6029 12059 24117
010111 3146 6291 12583 25166
011000 3277 6554 13107 26214
011001 3408 6816 13631 27263
011010 3539 7078 14156 28312
011011 3670 7340 14680 29360
011100 3801 7602 15204 30409
011101 3932 7864 15729 31457
011110 4063 8126 16253 32506
011111 4194 8389 16777 33554

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-14
Table 5-5 16.78 MHz System Clock Frequencies (Continued)
(Shaded cells represent values that exceed 16.78 MHz specifications.)

Modulus Prescaler
[W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
Y
(fVCO = 2 × Value) (fVCO = Value) (fVCO = 2 × Value) (fVCO = Value)
100000 4325 kHz 8651 kHz 17302 kHz 34603 kHz
100001 4456 8913 17826 35652
100010 4588 9175 18350 36700
100011 4719 9437 18874 37749
100100 4850 9699 19399 38797
100101 4981 9961 19923 39846
100110 5112 10224 20447 40894
100111 5243 10486 20972 41943
101000 5374 10748 21496 42992
101001 5505 11010 22020 44040
101010 5636 11272 22544 45089
101011 5767 11534 23069 46137
101100 5898 11796 23593 47186
101101 6029 12059 24117 48234
101110 6160 12321 24642 49283
101111 6291 12583 25166 50332
110000 6423 12845 25690 51380
110001 6554 13107 26214 52428
110010 6685 13369 26739 53477
110011 6816 13631 27263 54526
110100 6947 13894 27787 55575
110101 7078 14156 28312 56623
110110 7209 14418 28836 57672
110111 7340 14680 29360 58720
111000 7471 14942 2988 59769
111001 7602 15204 30409 60817
111010 7733 15466 30933 61866
111011 7864 15729 31457 62915
111100 7995 15991 31982 63963
111101 8126 16253 32506 65011
111110 8258 16515 33030 66060
111111 8389 16777 33554 67109

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-15
Table 5-6 System Clock Frequencies for a 20.97 MHz System
(Shaded cells represent values that exceed 20.97 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-16
Table 5-6 System Clock Frequencies for a 20.97 MHz System (Continued)
(Shaded cells represent values that exceed 20.97 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-17
Table 5-7 System Clock Frequencies for a 25.17 MHz System
(Shaded cells represent values that exceed 25.17 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-18
Table 5-7 System Clock Frequencies for a 25.17 MHz System (Continued)
(Shaded cells represent values that exceed 25.17 MHz specifications.)

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-19
5.3.3 External Bus Clock
The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the E-
clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for M6800 devices
and peripherals. ECLK frequency can be set to system clock frequency divided by
eight or system clock frequency divided by sixteen. The clock is enabled by the CS10
field in chip-select pin assignment register 1 (CSPAR1). ECLK operation during low-
power stop is described in the following paragraph. Refer to 5.9 Chip-Selects for
more information about the external bus clock.

5.3.4 Low-Power Operation

Low-power operation is initiated by the CPU32. To reduce power consumption selec-
tively, the CPU can set the STOP bits in each module configuration register. To
minimize overall microcontroller power consumption, the CPU can execute the
LPSTOP instruction, which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.

When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the
current interrupt mask into the clock control logic. The SIM brings the MCU out of low-
power stop mode when one of the following exceptions occur:

• RESET
• Trace
• SIM interrupt of higher priority than the stored interrupt mask
Refer to 5.6.4.2 LPSTOP Broadcast Cycle and 4.8.2.1 Low-Power Stop (LPSTOP)
for more information.

During low-power stop mode, unless the system clock signal is supplied by an external
source and that source is removed, the SIM clock control logic and the SIM clock sig-
nal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the
RESET and IRQ pins are clocked by SIMCLK, and can be used to bring the processor
out of LPSTOP. Optionally, the SIM can also continue to generate the CLKOUT signal
while in low-power stop mode.

STSIM and STEXT bits in SYNCR determine clock operation during low-power stop
mode.

The flowchart shown in Figure 5-5 summarizes the effects of the STSIM and STEXT
bits when the MCU enters normal low power stop mode. Any clock in the off state is
held low. If the synthesizer VCO is turned off during low-power stop mode, there is a
PLL relock delay after the VCO is turned back on.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-20
SET UP INTERRUPT
TO WAKE UP MCU
FROM LPSTOP

NO
USING
EXTERNAL CLOCK?

YES
NO
USE SYSTEM CLOCK
AS SIMCLK IN LPSTOP?

YES

SET STSIM = 1 SET STSIM = 0

fsimclk1 = fsys fsimclk1 = fref
IN LPSTOP IN LPSTOP

NO NO
WANT CLKOUT WANT CLKOUT
ON IN LPSTOP? ON IN LPSTOP?

YES YES

SET STEXT = 1 SET STEXT = 0 SET STEXT = 1 SET STEXT = 0

fclkout2 = fsys fclkout2 = 0 Hz fclkout2 = fref fclkout2 = 0 Hz
feclk = ÷ fsys feclk = 0 Hz feclk = 0 Hz feclk = 0 Hz
IN LPSTOP IN LPSTOP IN LPSTOP IN LPSTOP

ENTER LPSTOP

NOTES:
1. THE SIMCLK IS USED BY THE PIT, IRQ, AND INPUT BLOCKS OF THE SIM.
2. CLKOUT CONTROL DURING LPSTOP IS OVERRIDDEN BY THE EXOFF BIT IN SIMCR. IF EXOFF = 1, THE CLKOUT
PIN IS ALWAYS IN A HIGH IMPEDANCE STATE AND STEXT HAS NO EFFECT IN LPSTOP. IF EXOFF = 0, CLKOUT
IS CONTROLLED BY STEXT IN LPSTOP.

LPSTOPFLOW

Figure 5-5 LPSTOP Flowchart

5.4 System Protection

The system protection block preserves reset status, monitors internal activity, and pro-
vides periodic interrupt generation. Figure 5-6 is a block diagram of the submodule.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-21
MODULE CONFIGURATION
AND TEST

RESET STATUS

HALT MONITOR RESET REQUEST

BUS MONITOR BERR

SPURIOUS INTERRUPT MONITOR

SOFTWARE WATCHDOG TIMER RESET REQUEST

CLOCK 29 PRESCALER

PERIODIC INTERRUPT TIMER IRQ[7:1]

SYS PROTECT BLOCK

Figure 5-6 System Protection Block

5.4.1 Reset Status

The reset status register (RSR) latches internal MCU status during reset. Refer to
5.7.10 Reset Status Register for more information.

5.4.2 Bus Monitor

The internal bus monitor checks data and size acknowledge (DSACK) or autovector
(AVEC) signal response times during normal bus cycles. The monitor asserts the inter-
nal bus error (BERR) signal when the response time is excessively long.
DSACK and AVEC response times are measured in clock cycles. Maximum allowable
response time can be selected by setting the bus monitor timing (BMT[1:0]) field in the
system protection control register (SYPCR). Table 5-8 shows the periods allowed.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-22
Table 5-8 Bus Monitor Period
BMT[1:0] Bus Monitor Time-Out Period
00 64 system clocks
01 32 system clocks
10 16 system clocks
11 8 system clocks

The monitor does not check DSACK response on the external bus unless the CPU32
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter-
nal to external bus cycles. If a system contains external bus masters, an external bus
monitor must be implemented and the internal-to-external bus monitor option must be
disabled.

When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor time-out period must be at
least twice the number of clocks that a single byte access requires.

5.4.3 Halt Monitor

The halt monitor responds to an assertion of the HALT signal on the internal bus,
caused by a double bus fault. A flag in the reset status register (RSR) indicates that
the last reset was caused by the halt monitor. Halt monitor reset can be inhibited by
the halt monitor (HME) enable bit in SYPCR. Refer to 5.6.5.2 Double Bus Faults for
more information.

5.4.4 Spurious Interrupt Monitor

During interrupt exception processing, the CPU32 normally acknowledges an interrupt
request, recognizes the highest priority source, and then either acquires a vector or
responds to a request for autovectoring. The spurious interrupt monitor asserts the
internal bus error signal (BERR) if no interrupt arbitration occurs during interrupt
exception processing. The assertion of BERR causes the CPU32 to load the spurious
interrupt exception vector into the program counter. The spurious interrupt monitor
cannot be disabled. Refer to 5.8 Interrupts for more information. For detailed infor-
mation about interrupt exception processing, refer to 4.9 Exception Processing.

5.4.5 Software Watchdog

The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
the software service register (SWSR) on a periodic basis. If servicing does not take
place, the watchdog times out and asserts the RESET signal.
Each time the service sequence is written, the software watchdog timer restarts. The
sequence to restart consists of the following steps:

1. Write $55 to SWSR.

2. Write $AA to SWSR.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-23
Both writes must occur before time-out in the order listed. Any number of instructions
can be executed between the two writes.

Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the
software watchdog timing (SWT[1:0]) field in SYPCR.

SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be
selected. The value of SWP is affected by the state of the MODCLK pin during reset,
as shown in Table 5-9. System software can change SWP value.

Table 5-9 MODCLK Pin and SWP Bit During Reset

MODCLK SWP
0 (PLL disabled) 1 (÷ 512)
1 (PLL enabled) 0 (÷ 1)

SWT[1:0] selects the divide ratio used to establish the software watchdog time-out
period. The following equation calculates the time-out period for a slow reference
frequency.

Divide Ratio Specified by SWP and SWT[1:0]-

Timeout Period = -----------------------------------------------------------------------------------------------------------------------
f ref

The following equation calculates the time-out period for an externally input clock
frequency.

Timeout Period = Divide Ratio Specified by SWP and SWT[1:0]-

-----------------------------------------------------------------------------------------------------------------------
f sys

Table 5-10 shows the divide ratio for each combination of SWP and SWT[1:0] bits.
When SWT[1:0] are modified, a watchdog service sequence must be performed
before the new time-out period can take effect.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-24
Table 5-10 Software Watchdog Ratio
SWP SWT[1:0] Divide Ratio
0 00 29
0 01 211
0 10 213
0 11 215
1 00 218
1 01 220
1 10 222
1 11 224

Figure 5-7 is a block diagram of the watchdog timer and the clock control for the peri-
odic interrupt timer.

EXTAL XTAL FREEZE MODCLK

CRYSTAL
OSCILLATOR 29 PRESCALER SWP
CLOCK SELECT CLOCK
AND DISABLE SELECT
PTP

÷4

SOFTWARE SOFTWARE WATCHDOG TIMER PERIODIC INTERRUPT TIMER

WATCHDOG (215 DIVIDER CHAIN — 4 TAPS) (8-BIT MODULUS COUNTER) PIT
RESET INTERRUPT
SWSR PICR PITR

LPSTOP

SWE

SWT1

SWT0
300 PIT WATCHDOG BLOCK

Figure 5-7 Periodic Interrupt Timer and Software Watchdog Timer

5.4.6 Periodic Interrupt Timer

The periodic interrupt timer (PIT) allows the generation of interrupts of specific priority
at predetermined intervals. This capability is often used to schedule control system
tasks that must be performed within time constraints. The timer consists of a prescaler,
a modulus counter, and registers that determine interrupt timing, priority and vector
assignment. Refer to 4.9 Exception Processing for more information.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-25
The periodic interrupt timer modulus counter is clocked by a signal (fref) derived from
the buffered crystal oscillator (EXTAL) input pin. The value of the periodic timer pres-
caler (PTP) bit in the periodic interrupt timer register (PITR) determines system clock
prescaling for the periodic interrupt timer. One of two options, either no prescaling, or
prescaling by a factor of 512, can be selected. The value of PTP is affected by the state
of the MODCLK pin during reset, as shown in Table 5-11. System software can
change PTP value.

Table 5-11 MODCLK Pin and PTP Bit at Reset

MODCLK PTP
0 (PLL disabled) 1 (÷ 512)
1 (PLL enabled) 0 (÷ 1)

Either clock signal selected by the PTP is divided by four before driving the modulus
counter. The modulus counter is initialized by writing a value to the periodic interrupt
timer modulus (PITM[7:0]) field in PITR. A zero value turns off the periodic timer. When
the modulus counter value reaches zero, an interrupt is generated. The modulus
counter is then reloaded with the value in PITM[7:0] and counting repeats. If a new
value is written to PITR, it is loaded into the modulus counter when the current count
is completed.

When a slow reference frequency is used, the PIT period can be calculated as follows:

PIT Period = (--------------------------------------------------------------------------------------------------------------------

PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 -)
f ref

When an externally input clock frequency is used, the PIT period can be calculated as
follows:

PIT Period = (--------------------------------------------------------------------------------------------------------------------

PITM[7:0] ) ( 1 if PTP = 0, 512 if PTP = 1 ) ( 4 -)
f sys

5.4.7 Interrupt Priority and Vectoring

Interrupt priority and vectoring are determined by the values of the periodic interrupt
request level (PIRQL[2:0]) and periodic interrupt vector (PIV) fields in the periodic
interrupt control register (PICR).

The PIRQL field is compared to the CPU32 interrupt priority mask to determine
whether the interrupt is recognized. Table 5-12 shows PIRQL[2:0] priority values.
Because of SIM hardware prioritization, a PIT interrupt is serviced before an external
interrupt request of the same priority. The periodic timer continues to run when the
interrupt is disabled.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-26
Table 5-12 Periodic Interrupt Priority
PIRQL[2:0] Priority Level
000 Periodic interrupt disabled
001 Interrupt priority level 1
010 Interrupt priority level 2
011 Interrupt priority level 3
100 Interrupt priority level 4
101 Interrupt priority level 5
110 Interrupt priority level 6
111 Interrupt priority level 7

The PIV field contains the periodic interrupt vector. The vector is placed on the IMB
when an interrupt request is made. The vector number is used to calculate the address
of the appropriate exception vector in the exception vector table. The reset value of the
PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.

5.4.8 Low-Power STOP Mode Operation

When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask
is stored in the clock control logic, internal clocks are disabled according to the state
of the STSIM bit in the SYNCR, and the MCU enters low-power stop mode. The bus
monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power
stop mode.

During low-power stop mode, the clock input to the software watchdog timer is dis-
abled and the timer stops. The software watchdog begins to run again on the first rising
clock edge after low-power stop mode ends. The watchdog is not reset by low-power
stop mode. A service sequence must be performed to reset the timer.

The periodic interrupt timer does not respond to the LPSTOP instruction, but continues
to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with
a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external
interrupt request, can bring the MCU out of low-power stop mode if it has a higher
priority than the interrupt mask value stored in the clock control logic when low-power
stop mode is initiated. LPSTOP can be terminated by a reset.

5.5 External Bus Interface

The external bus interface (EBI) transfers information between the internal MCU bus
and external devices. Figure 5-8 shows a basic system with external memory and
peripherals.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-27
VDD VDD VDD VDD VDD VDD

10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ

DSACK1
DSACK0 DTACK

(ASYNC BUS PERIPHERAL)

R/W R/W
CS3 CS

MC68HC681
CS4 IACK
IRQ7 IRQ

ADDR[3:0]
ADDR[17:0] RS[4:1]

DATA[15:8]
DATA[15:0] D[7:0]
VDD

10 kΩ

CSBOOT CE
OE

(FLASH 64K X 16)

ADDR[17:1]
A[16:0]
MC68336/376

DATA[15:0]
VDD VDD DQ[15:0]

10 kΩ 10 kΩ

CS0 E
G

(SRAM 32K X 8)
CS1 W MCM6206D
ADDR[15:1]
A[14:0]

DATA[15:8]
DQ[7:0]

VDD

10 kΩ E
G
(SRAM 32K X 8)
MCM6206D

CS2 W

ADDR[15:1]
A[14:0]

DATA[7:0]
DQ[7:0]

68300 SIM/SCIM BUS

Figure 5-8 MCU Basic System

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-28
The external bus has 24 address lines and 16 data lines. The EBI provides dynamic
sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word
transfers. Port width is the maximum number of bits accepted or provided during a bus
transfer. Widths of eight and sixteen bits are accessed through the use of asynchro-
nous cycles controlled by the size (SIZ1 and SIZ0) and data and size acknowledge
(DSACK1 and DSACK0) pins. Multiple bus cycles may be required for dynamically
sized transfers.

To add flexibility and minimize the necessity for external logic, MCU chip-select logic
can be synchronized with EBI transfers. Refer to 5.9 Chip-Selects for more
information.

5.5.1 Bus Control Signals

The address bus provides addressing information to external devices. The data bus
transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals,
one for the address bus and another for the data bus, indicate the validity of an
address and provide timing information for data.

Control signals indicate the beginning of each bus cycle, the address space it is to take
place in, the size of the transfer, and the type of cycle. External devices decode these
signals and respond to transfer data and terminate the bus cycle. The EBI operates in
an asynchronous mode for any port width.

5.5.1.1 Address Bus

Bus signals ADDR[23:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while AS is asserted.

5.5.1.2 Address Strobe

Address strobe (AS) is a timing signal that indicates the validity of an address on the
address bus and of many control signals. It is asserted one-half clock after the begin-
ning of a bus cycle.

5.5.1.3 Data Bus

Signals DATA[15:0] form a bidirectional, non-multiplexed parallel bus that transfers
data to or from the MCU. A read or write operation can transfer eight or sixteen bits of
data in one bus cycle. During a read cycle, the data is latched by the MCU on the last
falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus
are driven, regardless of the port width or operand size. The MCU places the data on
the data bus one-half clock cycle after AS is asserted in a write cycle.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-29
5.5.1.4 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS is asserted at the same time as AS during
a read cycle. For a write cycle, DS signals an external device that data on the bus is
valid. The MCU asserts DS one full clock cycle after the assertion of AS during a write
cycle.

5.5.1.5 Read/Write Signal

The read/write signal (R/W) determines the direction of the transfer during a bus cycle.
This signal changes state, when required, at the beginning of a bus cycle, and is valid
while AS is asserted. R/W only transitions when a write cycle is preceded by a read
cycle or vice versa. The signal may remain low for two consecutive write cycles.

5.5.1.6 Size Signals

Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during
an operand cycle. They are valid while the AS is asserted. Table 5-13 shows SIZ0 and
SIZ1 encoding.

Table 5-13 Size Signal Encoding

SIZ1 SIZ0 Transfer Size
0 1 Byte
1 0 Word
1 1 Three bytes
0 0 Long word

5.5.1.7 Function Codes

The CPU generates function code signals (FC[2:0]) to indicate the type of activity
occurring on the data or address bus. These signals can be considered address exten-
sions that can be externally decoded to determine which of eight external address
spaces is accessed during a bus cycle.

Address space 7 is designated CPU space. CPU space is used for control information
not normally associated with read or write bus cycles. Function codes are valid while
AS is asserted.
Table 5-14 shows address space encoding.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-30
Table 5-14 Address Space Encoding
FC2 FC1 FC0 Address Space
0 0 0 Reserved
0 0 1 User data space
0 1 0 User program space
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Supervisor data space
1 1 0 Supervisor program space
1 1 1 CPU space

The supervisor bit in the status register determines whether the CPU is operating in
supervisor or user mode. Addressing mode and the instruction being executed deter-
mine whether a memory access is to program or data space.

5.5.1.8 Data and Size Acknowledge Signals

During normal bus transfers, external devices assert the data and size acknowledge
signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig-
nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the
signals indicate that an external device has successfully stored data and that the cycle
can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer
to 5.9 Chip-Selects for more information.

5.5.1.9 Bus Error Signal

The bus error signal (BERR) is asserted when a bus cycle is not properly terminated
by DSACK or AVEC assertion. It can also be asserted in conjunction with DSACK to
indicate a bus error condition, provided it meets the appropriate timing requirements.
Refer to 5.6.5 Bus Exception Control Cycles for more information.

The internal bus monitor can generate the BERR signal for internal-to-internal and
internal-to-external transfers. In systems with an external bus master, the SIM bus
monitor must be disabled and external logic must be provided to drive the BERR pin,
because the internal BERR monitor has no information about transfers initiated by an
external bus master. Refer to 5.6.6 External Bus Arbitration for more information.

5.5.1.10 Halt Signal

The halt signal (HALT) can be asserted by an external device for debugging purposes
to cause single bus cycle operation or (in combination with BERR) a retry of a bus
cycle in error. The HALT signal affects external bus cycles only. As a result, a program
not requiring use of the external bus may continue executing, unaffected by the HALT
signal.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-31
When the MCU completes a bus cycle with the HALT signal asserted, DATA[15:0] is
placed in a high-impedance state and bus control signals are driven inactive; the
address, function code, size, and read/write signals remain in the same state. If HALT
is still asserted once bus mastership is returned to the MCU, the address, function
code, size, and read/write signals are again driven to their previous states. The MCU
does not service interrupt requests while it is halted. Refer to 5.6.5 Bus Exception
Control Cycles for more information.

5.5.1.11 Autovector Signal

The autovector signal (AVEC) can be used to terminate external interrupt acknowl-
edge cycles. Assertion of AVEC causes the CPU32 to generate vector numbers to
locate an interrupt handler routine. If AVEC is continuously asserted, autovectors are
generated for all external interrupt requests. AVEC is ignored during all other bus
cycles. Refer to 5.8 Interrupts for more information. AVEC for external interrupt
requests can also be supplied internally by chip-select logic. Refer to 5.9 Chip-
Selects for more information. The autovector function is disabled when there is an
external bus master. Refer to 5.6.6 External Bus Arbitration for more information.

5.5.2 Dynamic Bus Sizing

The MCU dynamically interprets the port size of an addressed device during each bus
cycle, allowing operand transfers to or from 8-bit and 16-bit ports.

During an operand transfer cycle, an external device signals its port size and indicates
completion of the bus cycle to the MCU through the use of the DSACK inputs, as
shown in Table 5-15. Chip-select logic can generate data and size acknowledge sig-
nals for an external device. Refer to 5.9 Chip-Selects for more information.

Table 5-15 Effect of DSACK Signals

DSACK1 DSACK0 Result
1 1 Insert Wait States in Current Bus Cycle
1 0 Complete Cycle — Data Bus Port Size is 8 Bits
0 1 Complete Cycle — Data Bus Port Size is 16 Bits
0 0 Reserved

If the CPU is executing an instruction that reads a long-word operand from a 16-bit
port, the MCU latches the 16 bits of valid data and then runs another bus cycle to
obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read
cycles. The addressed device uses the DSACK signals to indicate the port width. For
instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of
whether the bus cycle is a byte or word operation).

Dynamic bus sizing requires that the portion of the data bus used for a transfer to or
from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],
and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus
cycles needed to transfer data and ensures that the MCU transfers valid data.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-32
The MCU always attempts to transfer the maximum amount of data on all bus cycles.
For any bus access, it is assumed that the port is 16 bits wide when the bus cycle
begins.

Operand bytes are designated as shown in Figure 5-9. OP[0:3] represent the order of
access. For instance, OP0 is the most significant byte of a long-word operand, and is
accessed first, while OP3, the least significant byte, is accessed last. The two bytes of
a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-
length operand is OP0.

OPERAND BYTE ORDER

31 24 23 16 15 87 0

LONG WORD OP0 OP1 OP2 OP3

THREE BYTE OP0 OP1 OP2

WORD OP0 OP1

BYTE OP0

OPERAND BYTE ORDER

Figure 5-9 Operand Byte Order

5.5.3 Operand Alignment

The EBI data multiplexer establishes the necessary connections for different combina-
tions of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus
and routes them to their required positions. Positioning of bytes is determined by the
size and address outputs. SIZ1 and SIZ0 indicate the number of bytes remaining to be
transferred during the current bus cycle. The number of bytes transferred is equal to
or less than the size indicated by SIZ1 and SIZ0, depending on port width.

ADDR0 also affects the operation of the data multiplexer. During an operand transfer,
ADDR[23:1] indicate the word base address of the portion of the operand to be
accessed. ADDR0 indicates the byte offset from the base.

5.5.4 Misaligned Operands

The CPU32 uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0
= 0 (an even address), the address is on a word and byte boundary. When ADDR0 =
1 (an odd address), the address is on a byte boundary only. A byte operand is aligned
at any address; a word or long-word operand is misaligned at an odd address. The
CPU32 does not support misaligned transfers.

The largest amount of data that can be transferred by a single bus cycle is an aligned
word. If the MCU transfers a long-word operand through a 16-bit port, the most signif-
icant operand word is transferred on the first bus cycle and the least significant
operand word is transferred on a following bus cycle.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-33
5.5.5 Operand Transfer Cases
Table 5-16 is a summary of how operands are aligned for various types of transfers.
OPn entries are portions of a requested operand that are read or written during a bus
cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. The following
paragraphs discuss all the allowable transfer cases in detail.

Table 5-16 Operand Alignment

Current DATA DATA Next
Transfer Case1 SIZ1 SIZ0 ADDR0 DSACK1 DSACK0
Cycle [15:8] [7:0] Cycle
1 Byte to 8-bit port (even) 0 1 0 1 0 OP0 (OP0)2 —
2 Byte to 8-bit port (odd) 0 1 1 1 0 OP0 (OP0) —
3 Byte to 16-bit port (even) 0 1 0 0 1 OP0 (OP0) —
4 Byte to 16-bit port (odd) 0 1 1 0 1 (OP0) OP0 —
5 Word to 8-bit port 1 0 0 1 0 OP0 (OP1) 2
6 Word to 16-bit port 1 0 0 0 1 OP0 OP1 —
7 3-Byte to 8-bit port3 1 1 1 1 0 OP0 (OP0) 5
8 Long word to 8-bit port 0 0 0 1 0 OP0 (OP0) 7
9 Long word to 16-bit port 0 0 0 0 1 OP0 OP1 6
NOTES:
1. All transfers are aligned. The CPU32 does not support misaligned word or long-word transfers.
2. Operands in parentheses are ignored by the CPU32 during read cycles.
3. Three-Byte transfer cases occur only as a result of a long word to 8-bit port transfer.

5.6 Bus Operation

Internal microcontroller modules are typically accessed in two system clock cycles.
Regular external bus cycles use handshaking between the MCU and external periph-
erals to manage transfer size and data. These accesses take three system clock
cycles, with no wait states. During regular cycles, wait states can be inserted as
needed by bus control logic. Refer to 5.6.2 Regular Bus Cycles for more information.

Fast termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Chip-select logic can
also be used to insert wait states before internal generation of handshaking signals.
Refer to 5.6.3 Fast Termination Cycles and 5.9 Chip-Selects for more information.
Bus control signal timing, as well as chip-select signal timing, are specified in APPEN-
DIX A ELECTRICAL CHARACTERISTICS. Refer to the SIM Reference Manual
(SIMRM/AD) for more information about each type of bus cycle.

5.6.1 Synchronization to CLKOUT

External devices connected to the MCU bus can operate at a clock frequency different
from the frequencies of the MCU as long as the external devices satisfy the interface
signal timing constraints. Although bus cycles are classified as asynchronous, they are
interpreted relative to the MCU system clock output (CLKOUT).

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-34
Descriptions are made in terms of individual system clock states, labeled {S0, S1,
S2,..., SN}. The designation “state” refers to the logic level of the clock signal and does
not correspond to any implemented machine state. A clock cycle consists of two suc-
cessive states. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more
information.

Bus cycles terminated by DSACK assertion normally require a minimum of three CLK-
OUT cycles. To support systems that use CLKOUT to generate DSACK and other
inputs, asynchronous input setup time and asynchronous input hold times are speci-
fied. When these specifications are met, the MCU is guaranteed to recognize the
appropriate signal on a specific edge of the CLKOUT signal.

For a read cycle, when assertion of DSACK is recognized on a particular falling edge
of the clock, valid data is latched into the MCU on the next falling clock edge, provided
that the data meets the data setup time. In this case, the parameter for asynchronous
operation can be ignored.

When a system asserts DSACK for the required window around the falling edge of S2
and obeys the bus protocol by maintaining DSACK and BERR or HALT until and
throughout the clock edge that negates AS (with the appropriate asynchronous input
hold time), no wait states are inserted. The bus cycle runs at the maximum speed of
three clocks per cycle.

To ensure proper operation in a system synchronized to CLKOUT, when either BERR

or BERR and HALT is asserted after DSACK, BERR (or BERR and HALT) assertion
must satisfy the appropriate data-in setup and hold times before the falling edge of the
clock cycle after DSACK is recognized.

5.6.2 Regular Bus Cycles

The following paragraphs contain a discussion of cycles that use external bus control
logic. Refer to 5.6.3 Fast Termination Cycles for information about fast termination
cycles.

To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ
signals and ADDR0 are externally decoded to select the active portion of the data bus.
Refer to 5.5.2 Dynamic Bus Sizing. When AS, DS, and R/W are valid, a peripheral
device either places data on the bus (read cycle) or latches data from the bus (write
cycle), then asserts a DSACK[1:0] combination that indicates port size.

The DSACK[1:0] signals can be asserted before the data from a peripheral device is
valid on a read cycle. To ensure valid data is latched into the MCU, a maximum period
between DSACK assertion and DS assertion is specified.

There is no specified maximum for the period between the assertion of AS and
DSACK. Although the MCU can transfer data in a minimum of three clock cycles when
the cycle is terminated with DSACK, the MCU inserts wait cycles in clock period incre-
ments until either DSACK signal goes low.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-35
If bus termination signals remain unasserted, the MCU will continue to insert wait
states, and the bus cycle will never end. If no peripheral responds to an access, or if
an access is invalid, external logic should assert the BERR or HALT signals to abort
the bus cycle (when BERR and HALT are asserted simultaneously, the CPU32 acts
as though only BERR is asserted). When enabled, the SIM bus monitor asserts BERR
when DSACK response time exceeds a predetermined limit. The bus monitor timeout
period is determined by the BMT[1:0] field in SYPCR. The maximum bus monitor tim-
eout period is 64 system clock cycles.

5.6.2.1 Read Cycle

During a read cycle, the MCU transfers data from an external memory or peripheral
device. If the instruction specifies a long-word or word operation, the MCU attempts to
read two bytes at once. For a byte operation, the MCU reads one byte. The portion of
the data bus from which each byte is read depends on operand size, peripheral
address, and peripheral port size. Figure 5-10 is a flowchart of a word read cycle.
Refer to 5.5.2 Dynamic Bus Sizing, 5.5.4 Misaligned Operands, and the SIM Ref-
erence Manual (SIMRM/AD) for more information.

MCU PERIPHERAL

ADDRESS DEVICE (S0)

1) SET R/W TO READ

2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE

ASSERT AS AND DS (S1) PRESENT DATA (S2)

1) DECODE ADDR, R/W, SIZ[1:0], DS

DECODE DSACK (S3) 2) PLACE DATA ON DATA[15:0] OR
DATA[15:8] IF 8-BIT DATA
3) DRIVE DSACK SIGNALS

LATCH DATA (S4)

NEGATE AS AND DS (S5) TERMINATE CYCLE (S5)

1) REMOVE DATA FROM DATA BUS

START NEXT CYCLE (S0) 2) NEGATE DSACK

RD CYC FLOW

Figure 5-10 Word Read Cycle Flowchart

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-36
5.6.2.2 Write Cycle
During a write cycle, the MCU transfers data to an external memory or peripheral
device. If the instruction specifies a long-word or word operation, the MCU attempts to
write two bytes at once. For a byte operation, the MCU writes one byte. The portion of
the data bus upon which each byte is written depends on operand size, peripheral
address, and peripheral port size.

Refer to 5.5.2 Dynamic Bus Sizing and 5.5.4 Misaligned Operands for more infor-
mation. Figure 5-11 is a flowchart of a write-cycle operation for a word transfer. Refer
to the SIM Reference Manual (SIMRM/AD) for more information.

MCU PERIPHERAL

ADDRESS DEVICE (S0)

1) SET R/W TO WRITE

2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE

ASSERT AS (S1)

PLACE DATA ON DATA[15:0] (S2)

ASSERT DS AND WAIT FOR DSACK (S3) ACCEPT DATA (S2 + S3)

1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
OPTIONAL STATE (S4) 3) ASSERT DSACK SIGNALS

NO CHANGE

TERMINATE OUTPUT TRANSFER (S5)

1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS TERMINATE CYCLE

NEGATE DSACK

START NEXT CYCLE

WR CYC FLOW

Figure 5-11 Write Cycle Flowchart

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-37
5.6.3 Fast Termination Cycles
When an external device has a fast access time, the chip-select circuit fast termination
option can provide a two-cycle external bus transfer. Because the chip-select circuits
are driven from the system clock, the bus cycle termination is inherently synchronized
with the system clock.

If multiple chip-selects are to be used to provide control signals to a single device and
match conditions occur simultaneously, all MODE, STRB, and associated DSACK
fields must be programmed to the same value. This prevents a conflict on the internal
bus when the wait states are loaded into the DSACK counter shared by all chip-
selects.

Fast termination cycles use internal handshaking signals generated by the chip-select
logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals.
When AS, DS, and R/W are valid, a peripheral device either places data on the bus
(read cycle) or latches data from the bus (write cycle). At the appropriate time, chip-
select logic asserts data and size acknowledge signals.

The DSACK option fields in the chip-select option registers determine whether inter-
nally generated DSACK or externally generated DSACK is used. The external DSACK
lines are always active, regardless of the setting of the DSACK field in the chip-select
option registers. Thus, an external DSACK can always terminate a bus cycle. Holding
a DSACK line low will cause all external bus cycles to be three-cycle (zero wait states)
accesses unless the chip-select option register specifies fast accesses.

For fast termination cycles, the fast termination encoding (%1110) must be used.
Refer to 5.9.1 Chip-Select Registers for information about fast termination setup.

To use fast termination, an external device must be fast enough to have data ready
within the specified setup time (for example, by the falling edge of S4). For information
on fast terminatiion, refer to APPENDIX A ELECTRICAL CHARACTERISTICS.

When fast termination is in use, DS is asserted during read cycles but not during write
cycles. The STRB field in the chip-select option register used must be programmed
with the address strobe encoding to assert the chip-select signal for a fast termination
write.

5.6.4 CPU Space Cycles

Function code signals FC[2:0] designate which of eight external address spaces is
accessed during a bus cycle. Address space 7 is designated CPU space. CPU space
is used for control information not normally associated with read or write bus cycles.
Function codes are valid only while AS is asserted. Refer to 5.5.1.7 Function Codes
for more information on codes and encoding.

During a CPU space access, ADDR[19:16] are encoded to reflect the type of access
being made. Figure 5-12 shows the three encodings used by 68300 family microcon-
trollers. These encodings represent breakpoint acknowledge (Type $0) cycles, low
power stop broadcast (Type $3) cycles, and interrupt acknowledge (Type $F) cycles.
Refer to 5.8 Interrupts for information about interrupt acknowledge bus cycles.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-38
CPU SPACE CYCLES

FUNCTION ADDRESS BUS

CODE

2 0 23 19 16 4 2 1 0
BREAKPOINT 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0
ACKNOWLEDGE

2 0 23 19 16 0
LOW POWER 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
STOP BROADCAST

2 0 23 19 16 0
INTERRUPT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
ACKNOWLEDGE

CPU SPACE
TYPE FIELD

CPU SPACE CYC TIM

Figure 5-12 CPU Space Address Encoding

5.6.4.1 Breakpoint Acknowledge Cycle

Breakpoints stop program execution at a predefined point during system development.
Breakpoints can be used alone or in conjunction with background debug mode. In
M68300 microcontrollers, both hardware and software can initiate breakpoints.

The CPU32 BKPT instruction allows the user to insert breakpoints through software.
The CPU responds to this instruction by initiating a breakpoint acknowledge read cycle
in CPU space. It places the breakpoint acknowledge (%0000) code on ADDR[19:16],
the breakpoint number (bits [2:0] of the BKPT opcode) on ADDR[4:2], and %0 (indicat-
ing a software breakpoint) on ADDR1.
External breakpoint circuitry decodes the function code and address lines and
responds by either asserting BERR or placing an instruction word on the data bus and
asserting DSACK. If the bus cycle is terminated by DSACK, the CPU32 reads the
instruction on the data bus and inserts the instruction into the pipeline. (For 8-bit ports,
this instruction fetch may require two read cycles.)

If the bus cycle is terminated by BERR, the CPU32 then performs illegal instruction
exception processing: it acquires the number of the illegal instruction exception vector,
computes the vector address from this number, loads the content of the vector address
into the PC, and jumps to the exception handler routine at that address.

Assertion of the BKPT input initiates a hardware breakpoint. The CPU32 responds by
initiating a breakpoint acknowledge read cycle in CPU space. It places the breakpoint
acknowledge code of %0000 on ADDR[19:16], the breakpoint number value of %111
on ADDR[4:2], and ADDR1 is set to %1, indicating a hardware breakpoint.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-39
External breakpoint circuitry decodes the function code and address lines, places an
instruction word on the data bus, and asserts BERR. The CPU32 then performs hard-
ware breakpoint exception processing: it acquires the number of the hardware
breakpoint exception vector, computes the vector address from this number, loads the
content of the vector address into the PC, and jumps to the exception handler routine
at that address. If the external device asserts DSACK rather than BERR, the CPU32
ignores the breakpoint and continues processing.

When BKPT assertion is synchronized with an instruction prefetch, processing of the

breakpoint exception occurs at the end of that instruction. The prefetched instruction
is “tagged” with the breakpoint when it enters the instruction pipeline. The breakpoint
exception occurs after the instruction executes. If the pipeline is flushed before the
tagged instruction is executed, no breakpoint occurs. When BKPT assertion is syn-
chronized with an operand fetch, exception processing occurs at the end of the
instruction during which BKPT is latched.

Refer to the CPU32 Reference Manual (CPU32RM/AD) and the SIM Reference
Manual (SIMRM/AD) for additional information. Breakpoint operation flow for the
CPU32 is shown in Figure 5-13.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-40
BREAKPOINT OPERATION FLOW

CPU32 PERIPHERAL

ACKNOWLEDGE BREAKPOINT

IF BREAKPOINT INSTRUCTION EXECUTED:

1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]
5) CLEAR T-BIT (ADDR1) TO ZERO
6) SET SIZE TO WORD
7) ASSERT AS AND DS

IF BKPT PIN ASSERTED:

1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] IF BKPT INSTRUCTION EXECUTED:
4) PLACE ALL ONES ON ADDR[4:2] 1) PLACE REPLACEMENT OPCODE ON DATA BUS
5) SET T-BIT (ADDR1) TO ONE 2) ASSERT DSACK
6) SET SIZE TO WORD OR:
7) ASSERT AS AND DS 1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING

IF BKPT ASSERTED:
IF BREAKPOINT INSTRUCTION EXECUTED AND 1) ASSERT DSACK
DSACK IS ASSERTED: OR:
1) LATCH DATA 1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
2) NEGATE AS AND DS
3) GO TO (A)

IF BKPT PIN ASSERTED AND

DSACK IS ASSERTED:
1) NEGATE AS AND DS
2) GO TO (A)

IF BERR ASSERTED:
1) NEGATE AS AND DS
2) GO TO (B)
(A) (B)

IF BKPT INSTRUCTION EXECUTED: 1) NEGATE DSACK or BERR

1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
2) CONTINUE PROCESSING

IF BKPT PIN ASSERTED:

1) CONTINUE PROCESSING

IF BKPT INSTRUCTION EXECUTED:

1) INITIATE ILLEGAL INSTRUCTION PROCESSING

IF BKPT PIN ASSERTED:

1) INITIATE HARDWARE BREAKPOINT PROCESSING

BREAKPOINT OPERATION FLOW

Figure 5-13 Breakpoint Operation Flowchart

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-41
5.6.4.2 LPSTOP Broadcast Cycle
Low-power stop mode is initiated by the CPU32. Individual modules can be stopped
by setting the STOP bits in each module configuration register, or the SIM can turn off
system clocks after execution of the LPSTOP instruction. When the CPU32 executes
LPSTOP, an LPSTOP broadcast cycle is generated. The SIM brings the MCU out of
low-power stop mode when either an interrupt of higher priority than the stored mask
or a reset occurs. Refer to 5.3.4 Low-Power Operation and 4.8.2.1 Low-Power
Stop (LPSTOP) for more information.

During an LPSTOP broadcast cycle, the CPU32 performs a CPU space write to
address $3FFFE. This write puts a copy of the interrupt mask value in the clock control
logic. The mask is encoded on the data bus as shown in Figure 5-14. The LPSTOP
CPU space cycle is shown externally (if the bus is available) as an indication to exter-
nal devices that the MCU is going into low-power stop mode. The SIM provides an
internally generated DSACK response to this cycle. The timing of this bus cycle is the
same as for a fast termination write cycle. If the bus is not available (arbitrated away),
the LPSTOP broadcast cycle is not shown externally.

NOTE
BERR during the LPSTOP broadcast cycle is ignored.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 IP MASK

LPSTOP MASK LEVEL

Figure 5-14 LPSTOP Interrupt Mask Level

5.6.5 Bus Exception Control Cycles

An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus error processing
occurs when bus cycles are not terminated in the expected manner. The SIM bus mon-
itor can be used to generate BERR internally, causing a bus error exception to be
taken. Bus cycles can also be terminated by assertion of the external BERR or HALT
pins signal, or by assertion of the two signals simultaneously.

Acceptable bus cycle termination sequences are summarized as follows. The case
numbers refer to Table 5-17, which indicates the results of each type of bus cycle
termination.

• Normal Termination
— DSACK is asserted; BERR and HALT remain negated (case 1).
• Halt Termination
— HALT is asserted at the same time or before DSACK, and BERR remains
negated (case 2).

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-42
• Bus Error Termination
— BERR is asserted in lieu of, at the same time as, or before DSACK (case 3),
or after DSACK (case 4), and HALT remains negated; BERR is negated at the
same time or after DSACK.
• Retry Termination
— HALT and BERR are asserted in lieu of, at the same time as, or before DSACK
(case 5) or after DSACK (case 6); BERR is negated at the same time or after
DSACK; HALT may be negated at the same time or after BERR.
Table 5-17 shows various combinations of control signal sequences and the resulting
bus cycle terminations.

Table 5-17 DSACK, BERR, and HALT Assertion Results

Asserted on Rising
Case Edge of State
Control Signal Result
Number
N1 N+2

DSACK A2 S4
1 BERR NA3 NA Normal termination.
HALT NA X5
DSACK A S
Halt termination: normal cycle terminate and halt.
2 BERR NA NA
Continue when HALT is negated.
HALT A/S S
DSACK NA/A X
Bus error termination: terminate and take bus error
3 BERR A S
exception, possibly deferred.
HALT NA X
DSACK A X
Bus error termination: terminate and take bus error
4 BERR A S
exception, possibly deferred.
HALT NA NA
DSACK NA/A X
Retry termination: terminate and retry when HALT is
5 BERR A S
negated.
HALT A/S S
DSACK A X
Retry termination: terminate and retry when HALT is
6 BERR NA A
negated.
HALT NA A
NOTES:
1. N = The number of current even bus state (S2, S4, etc.).
2. A = Signal is asserted in this bus state.
3. NA = Signal is not asserted in this state.
4. X = Don’t care.
5. S = Signal was asserted in previous state and remains asserted in this state.

To control termination of a bus cycle for a retry or a bus error condition properly,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the
required setup time and hold time for both of them are met for the same falling edge
of the MCU clock. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for
timing requirements. External circuitry that provides these signals must be designed
with these constraints in mind, or else the internal bus monitor must be used.

DSACK, BERR, and HALT may be negated after AS is negated.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-43
WARNING
If DSACK or BERR remain asserted into S2 of the next bus cycle,
that cycle may be terminated prematurely.

5.6.5.1 Bus Errors

The CPU32 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU32 detects assertion of the IMB BERR signal (by the internal bus
monitor or an external source) while the HALT signal remains negated.

BERR assertions do not force immediate exception processing. The signal is synchro-
nized with normal bus cycles and is latched into the CPU32 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several
factors:

• Which bus cycle of an instruction is terminated by assertion of BERR.

• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
BERR is asserted.
• Whether BERR is asserted during a program space access or a data space ac-
cess.
Because of these factors, it is impossible to predict precisely how long after occur-
rence of a bus error the bus error exception is processed.

CAUTION
The external bus interface does not latch data when an external bus
cycle is terminated by a bus error. When this occurs during an
instruction prefetch, the IMB precharge state (bus pulled high, or
$FF) is latched into the CPU32 instruction register, with indetermi-
nate results.

5.6.5.2 Double Bus Faults

Exception processing for bus error exceptions follows the standard exception process-
ing sequence. Refer to 4.9 Exception Processing for more information. However, a
special case of bus error, called double bus fault, can abort exception processing.

BERR assertion is not detected until an instruction is complete. The BERR latch is
cleared by the first instruction of the BERR exception handler. Double bus fault occurs
in three ways:

1. When bus error exception processing begins and a second BERR is detected
before the first instruction of the exception handler is executed.
2. When one or more bus errors occur before the first instruction after a reset ex-
ception is executed.
3. A bus error occurs while the CPU32 is loading information from a bus error
stack frame during a return from exception (RTE) instruction.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-44
Multiple bus errors within a single instruction that can generate multiple bus cycles
cause a single bus error exception after the instruction has been executed.

Immediately after assertion of a second BERR, the MCU halts and drives the HALT
line low. Only a reset can restart a halted MCU. However, bus arbitration can still
occur. Refer to 5.6.6 External Bus Arbitration for more information. A bus error or
address error that occurs after exception processing has been completed (during the
execution of the exception handler routine, or later) does not cause a double bus fault.
The MCU continues to retry the same bus cycle as long as the external hardware
requests it.

5.6.5.3 Retry Operation

When an external device asserts BERR and HALT during a bus cycle, the MCU enters
the retry sequence. A delayed retry can also occur. The MCU terminates the bus cycle,
places the AS and DS signals in their inactive state, and does not begin another bus
cycle until the BERR and HALT signals are negated by external logic. After a synchro-
nization delay, the MCU retries the previous cycle using the same address, function
codes, data (for a write), and control signals. The BERR signal should be negated
before S2 of the read cycle to ensure correct operation of the retried cycle.

If BR, BERR, and HALT are all asserted on the same cycle, the EBI will enter the rerun
sequence but first relinquishes the bus to an external master. Once the external mas-
ter returns the bus and negates BERR and HALT, the EBI runs the previous bus cycle.
This feature allows an external device to correct the problem that caused the bus error
and then try the bus cycle again.

The MCU retries any read or write cycle of an indivisible read-modify-write operation
separately. RMC remains asserted during the entire retry sequence. The MCU will not
relinquish the bus while RMC is asserted. Any device that requires the MCU to give up
the bus and retry a bus cycle during a read-modify-write cycle must assert BERR and
BR only (HALT must remain negated). The bus error handler software should examine
the read-modify-write bit in the special status word and take the appropriate action to
resolve this type of fault when it occurs. Refer to the SIM Reference Manual (SIMRM/
AD) for additional information on read-modify-write and retry operations.

5.6.5.4 Halt Operation

When HALT is asserted while BERR is not asserted, the MCU halts external bus activ-
ity after negation of DSACK. The MCU may complete the current word transfer in
progress. For a long-word to byte transfer, this could be after S2 or S4. For a word to
byte transfer, activity ceases after S2.

Negating and reasserting HALT according to timing requirements provides single-step

(bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only,
so that a program that does not use the external bus can continue executing.

During dynamically-sized 8-bit transfers, external bus activity may not stop at the next
cycle boundary. Occurrence of a bus error while HALT is asserted causes the CPU32
to initiate a retry sequence.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-45
When the MCU completes a bus cycle while the HALT signal is asserted, the data bus
goes into a high-impedance state and the AS and DS signals are driven to their inac-
tive states. Address, function code, size, and read/write signals remain in the same
state.

The halt operation has no effect on bus arbitration. However, when external bus arbi-
tration occurs while the MCU is halted, address and control signals go into a high-
impedance state. If HALT is still asserted when the MCU regains control of the bus,
address, function code, size, and read/write signals revert to the previous driven
states. The MCU cannot service interrupt requests while halted.

5.6.6 External Bus Arbitration

The MCU bus design provides for a single bus master at any one time. Either the MCU
or an external device can be master. Bus arbitration protocols determine when an
external device can become bus master. Bus arbitration requests are recognized dur-
ing normal processing, HALT assertion, and when the CPU32 has halted due to a
double bus fault.

The bus controller in the MCU manages bus arbitration signals so that the MCU has
the lowest priority. External devices that need to obtain the bus must assert bus arbi-
tration signals in the sequences described in the following paragraphs.

Systems that include several devices that can become bus master require external cir-
cuitry to assign priorities to the devices, so that when two or more external devices
attempt to become bus master at the same time, the one having the highest priority
becomes bus master first. The protocol sequence is:

1. An external device asserts the bus request signal (BR);

2. The MCU asserts the bus grant signal (BG) to indicate that the bus is available;
3. An external device asserts the bus grant acknowledge (BGACK) signal to indi-
cate that it has assumed bus mastership.
BR can be asserted during a bus cycle or between cycles. BG is asserted in response
to BR. To guarantee operand coherency, BG is only asserted at the end of operand
transfer. Additionally, BG is not asserted until the end of an indivisible read-modify-
write operation (when RMC is negated).

If more than one external device can be bus master, required external arbitration must
begin when a requesting device receives BG. An external device must assert BGACK
when it assumes mastership, and must maintain BGACK assertion as long as it is bus
master.

Two conditions must be met for an external device to assume bus mastership. The
device must receive BG through the arbitration process, and BGACK must be inactive,
indicating that no other bus master is active. This technique allows the processing of
bus requests during data transfer cycles.

BG is negated a few clock cycles after BGACK transition. However, if bus requests are
still pending after BG is negated, the MCU asserts BG again within a few clock cycles.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-46
This additional BG assertion allows external arbitration circuitry to select the next bus
master before the current master has released the bus.

Refer to Figure 5-15, which shows bus arbitration for a single device. The flowchart
shows BR negated at the same time BGACK is asserted.

MCU REQUESTING DEVICE

REQUEST THE BUS

1) ASSERT BUS REQUEST (BR)

GRANT BUS ARBITRATION

1) ASSERT BUS GRANT (BG)

ACKNOWLEDGE BUS MASTERSHIP

1) EXTERNAL ARBITRATION DETERMINES

NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED
3) NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
TERMINATE ARBITRATION 4) BUS MASTER NEGATES BR

1) NEGATE BG (AND WAIT FOR

BGACK TO BE NEGATED)
OPERATE AS BUS MASTER

1) PERFORM DATA TRANSFERS (READ AND

WRITE CYCLES) ACCORDING TO THE SAME
RULES THE PROCESSOR USES

RELEASE BUS MASTERSHIP

1) NEGATE BGACK
RE-ARBITRATE OR RESUME PROCESSOR
OPERATION
BUS ARB FLOW

Figure 5-15 Bus Arbitration Flowchart for Single Request

5.6.6.1 Show Cycles

The MCU normally performs internal data transfers without affecting the external bus,
but it is possible to show these transfers during debugging. AS is not asserted exter-
nally during show cycles.

Show cycles are controlled by SHEN[1:0] in SIMCR. This field is set to %00 by reset.
When show cycles are disabled, the address bus, function codes, size, and read/write
signals reflect internal bus activity, but AS and DS are not asserted externally and
external data bus pins are in high-impedance state during internal accesses. Refer to
5.2.3 Show Internal Cycles and the SIM Reference Manual (SIMRM/AD) for more
information.

When show cycles are enabled, DS is asserted externally during internal cycles, and
internal data is driven out on the external data bus. Because internal cycles normally
continue to run when the external bus is granted, one SHEN encoding halts internal
bus activity while there is an external master.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-47
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion
of the data bus is valid during the cycle. During a byte write to an internal address, the
portion of the bus that represents the byte that is not written reflects internal bus con-
ditions, and is indeterminate. During a byte write to an external address, the data
multiplexer in the SIM causes the value of the byte that is written to be driven out on
both bytes of the data bus.

5.7 Reset
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.
The RESET input is synchronized to the system clock. If there is no clock when
RESET is asserted, reset does not occur until the clock starts. Resets are clocked to
allow completion of write cycles in progress at the time RESET is asserted.

Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The SIM
determines whether a reset is valid, asserts control signals, performs basic system
configuration and boot ROM selection based on hardware mode-select inputs, then
passes control to the CPU32.

5.7.1 Reset Exception Processing

The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing, and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the
exception vector table. The exception vector table consists of 256 four-byte vectors
and occupies 1024 bytes of address space. The exception vector table can be relo-
cated in memory by changing its base address in the vector base register (VBR). The
CPU32 uses vector numbers to calculate displacement into the table. Refer to 4.9
Exception Processing for more information.

Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset
occurs at the end of a bus cycle, and not at an instruction boundary. Handling resets
in this way prevents write cycles in progress at the time the reset signal is asserted
from being corrupted. However, any processing in progress is aborted by the reset
exception and cannot be restarted. Only essential reset tasks are performed during
exception processing. Other initialization tasks must be accomplished by the excep-
tion handler routine. Refer to 5.7.9 Reset Processing Summary for details on
exception processing.

5.7.2 Reset Control Logic

SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate
reset lines. Reset control logic can drive four different internal signals:

1. XTRST (external reset) drives the external reset pin.

2. CLKRST (clock reset) resets the clock module.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-48
3. MSTRST (master reset) goes to all other internal circuits.
4. SYSRST (system reset) indicates to internal circuits that the CPU32 has
executed a RESET instruction.
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchro-
nous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that
cause an asynchronous reset usually indicate a catastrophic failure. As a result, the
reset control logic responds by asserting reset to the system immediately. (A system
reset, however, caused by the CPU32 RESET instruction, is asynchronous but does
not indicate any type of catastrophic failure).

Synchronous resets are timed to occur at the end of bus cycles. The SIM bus monitor
is automatically enabled for synchronous resets. When a bus cycle does not terminate
normally, the bus monitor terminates it.

Refer to Table 5-18 for a summary of reset sources.

Table 5-18 Reset Source Summary

Reset Lines Asserted by
Type Source Timing Cause
Controller
External External Synch RESET pin MSTRST CLKRST EXTRST
Power up EBI Asynch VDD MSTRST CLKRST EXTRST
Software watchdog Monitor Asynch Time out MSTRST CLKRST EXTRST
Internal HALT assertion
HALT Monitor Asynch MSTRST CLKRST EXTRST
(e.g. double bus fault)
Loss of clock Clock Synch Loss of reference MSTRST CLKRST EXTRST
Test Test Synch Test mode MSTRST — EXTRST
System CPU32 Asynch RESET instruction — — EXTRST

Internal single byte or aligned word writes are guaranteed valid for synchronous
resets. External writes are also guaranteed to complete, provided the external config-
uration logic on the data bus is conditioned as shown in Figure 5-16.

5.7.3 Reset Mode Selection

The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint
assertions. Table 5-19 is a summary of reset mode selection options.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-49
Table 5-19 Reset Mode Selection
Default Function Alternate Function
Mode Select Pin
(Pin Left High) (Pin Pulled Low)
DATA0 CSBOOT 16-bit CSBOOT 8-bit
CS0 BR
DATA1 CS1 BG
CS2 BGACK
CS3 FC0
DATA2 CS4 FC1
CS5 FC2
DATA3 CS6 ADDR19
DATA4 CS[7:6] ADDR[20:19]
DATA5 CS[8:6] ADDR[21:19]
DATA6 CS[9:6] ADDR[22:19]
DATA7 CS[10:6] ADDR[23:19]
DSACK[1:0],
DATA8 PORTE
AVEC, DS, AS, SIZ[1:0]
IRQ[7:1]
DATA9 PORTF
MODCLK
DATA11 Normal operation1 Reserved
MODCLK VCO = System clock EXTAL = System clock
BKPT Background mode disabled Background mode enabled
NOTES:
1. The DATA11 bus must remain high during reset to ensure normal operation.

5.7.3.1 Data Bus Mode Selection

All data lines have weak internal pull-up drivers. When pins are held high by the inter-
nal drivers, the MCU uses a default operating configuration. However, specific lines
can be held low externally during reset to achieve an alternate configuration.

NOTE
External bus loading can overcome the weak internal pull-up drivers
on data bus lines and hold pins low during reset.

Use an active device to hold data bus lines low. Data bus configuration logic must
release the bus before the first bus cycle after reset to prevent conflict with external
memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is
released. If external mode selection logic causes a conflict of this type, an isolation
resistor on the driven lines may be required. Figure 5-16 shows a recommended
method for conditioning the mode select signals.

The mode configuration drivers are conditioned with R/W and DS to prevent conflicts
between external devices and the MCU when reset is asserted. If external RESET is
asserted during an external write cycle, R/W conditioning (as shown in Figure 5-16)
prevents corruption of the data during the write. Similarly, DS conditions the mode con-
figuration drivers so that external reads are not corrupted when RESET is asserted
during an external read cycle.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-50
DATA15

DATA8

DATA7

DATA0

OUT1 OUT8 OUT1 OUT8

74HC244 OE 74HC244 OE

IN1 IN8 IN1 IN8

VDD VDD VDD TIE INPUTS TIE INPUTS
HIGH OR LOW HIGH OR LOW
AS NEEDED AS NEEDED

820 Ω 10 κΩ 10 κΩ

RESET

R/W
DATA BUS SELECT CONDITIONING

Figure 5-16 Preferred Circuit for Data Bus Mode Select Conditioning

Alternate methods can be used for driving data bus pins low during reset. Figure 5-17
shows two of these options. The simplest is to connect a resistor in series with a diode
from the data bus pin to the RESET line. A bipolar transistor can be used for the same
purpose, but an additional current limiting resistor must be connected between the
base of the transistor and the RESET pin. If a MOSFET is substituted for the bipolar
transistor, only the 1 kΩ isolation resistor is required. These simpler circuits do not
offer the protection from potential memory corruption during RESET assertion as does
the circuit shown in Figure 5-16.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-51
DATA PIN DATA PIN

1 kW
1 kW
2 kW

RESET 2N3906
1N4148

RESET

ALTERNATE DATA BUS CONDITION CIRCUIT

Figure 5-17 Alternate Circuit for Data Bus Mode Select Conditioning

Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC-

TERISTICS. Do not confuse pin function with pin electrical state. Refer to 5.7.5 Pin
States During Reset for more information.

Unlike other chip-select signals, the boot ROM chip-select (CSBOOT) is active at the
release of RESET. During reset exception processing, the MCU fetches initialization
vectors beginning at address $000000 in supervisor program space. An external
memory device containing vectors located at these addresses can be enabled by
CSBOOT after a reset.

The logic level of DATA0 during reset selects boot ROM port size for dynamic bus allo-
cation. When DATA0 is held low, port size is eight bits; when DATA0 is held high,
either by the weak internal pull-up driver or by an external pull-up, port size is 16 bits.
Refer to 5.9.4 Chip-Select Reset Operation for more information.

DATA1 and DATA2 determine the functions of CS[2:0] and CS[5:3], respectively.
DATA[7:3] determine the functions of an associated chip-select and all lower-num-
bered chip-selects down through CS6. For example, if DATA5 is pulled low during
reset, CS[8:6] are assigned alternate function as ADDR[21:19], and CS[10:9] remain
chip-selects. Refer to 5.9.4 Chip-Select Reset Operation for more information.

DATA8 determines the function of the DSACK[1:0], AVEC, DS, AS, and SIZE pins. If
DATA8 is held low during reset, these pins are assigned to I/O port E.

DATA9 determines the function of interrupt request pins IRQ[7:1] and the clock mode
select pin (MODCLK). When DATA9 is held low during reset, these pins are assigned
to I/O port F.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-52
5.7.3.2 Clock Mode Selection
The state of the clock mode (MODCLK) pin during reset determines what clock source
the MCU uses. When MODCLK is held high during reset, the clock signal is generated
from a reference frequency using the clock synthesizer. When MODCLK is held low
during reset, the clock synthesizer is disabled, and an external system clock signal
must be applied. Refer to 5.3 System Clock for more information.

NOTE
The MODCLK pin can also be used as parallel I/O pin PF0. To pre-
vent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.

5.7.3.3 Breakpoint Mode Selection

Background debug mode (BDM) is enabled when the breakpoint (BKPT) pin is sam-
pled at a logic level zero at the release of RESET. Subsequent assertion of the BKPT
pin or the internal breakpoint signal (for instance, the execution of the CPU32 BKPT
instruction) will place the CPU32 in BDM.

If BKPT is sampled at a logic level one at the rising edge of RESET, BDM is disabled.
Assertion of the BKPT pin or execution of the execution of the BKPT instruction will
result in normal breakpoint exception processing.

BDM remains enabled until the next system reset. BKPT is relatched on each rising
transition of RESET. BKPT is internally synchronized and must be held low for at least
two clock cycles prior to RESET negation for BDM to be enabled. BKPT assertion logic
must be designed with special care. If BKPT assertion extends into the first bus cycle
following the release of RESET, the bus cycle could inadvertently be tagged with a
breakpoint.

Refer to 4.10.2 Background Debug Mode and the CPU32 Reference Manual
(CPU32RM/AD) for more information on background debug mode. Refer to the SIM
Reference Manual (SIMRM/AD) and APPENDIX A ELECTRICAL CHARACTERIS-
TICS for more information concerning BKPT signal timing.

5.7.4 MCU Module Pin Function During Reset

Usually, module pins default to port functions and input/output ports are set to the input
state. This is accomplished by disabling pin functions in the appropriate control regis-
ters, and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 5-20 is a summary of mod-
ule pin function out of reset.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-53
Table 5-20 Module Pin Functions During Reset
Module Pin Mnemonic Function
DSI/IFETCH DSI/IFETCH
CPU32 DSO/IPIPE DSO/IPIPE
BKPT/DSCLK BKPT/DSCLK
PGP7/IC4/OC5 Discrete input
PGP[6:3]/OC[4:1] Discrete input
PGP[2:0]/IC[3:1] Discrete input
GPT
PAI Discrete input
PCLK Discrete input
PWMA, PWMB Discrete output
PQS0/MISO Discrete input
PQS1/MOSI Discrete input
PQS2/SCK Discrete input
QSM PQS3/PCS0/SS Discrete input
PQS[6:4]/PCS[3:1] RXD
PQS7/TXD Discrete input
RXD Discrete input

5.7.5 Pin States During Reset

It is important to keep the distinction between pin function and pin electrical state clear.
Although control register values and mode select inputs determine pin function, a pin
driver can be active, inactive or in high-impedance state while reset occurs. During
power-on reset, pin state is subject to the constraints discussed in 5.7.7 Power-On
Reset.

NOTE
Pins that are not used should either be configured as outputs, or (if
configured as inputs) pulled to the appropriate inactive state. This
decreases additional IDD caused by digital inputs floating near mid-
supply level.

5.7.5.1 Reset States of SIM Pins

Generally, while RESET is asserted, SIM pins either go to an inactive high-impedance
state or are driven to their inactive states. After RESET is released, mode selection
occurs and reset exception processing begins. Pins configured as inputs must be
driven to the desired active state. Pull-up or pull-down circuitry may be necessary. Pins
configured as outputs begin to function after RESET is released. Table 5-21 is a sum-
mary of SIM pin states during reset.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-54
Table 5-21 SIM Pin Reset States
Pin State After RESET Released
Pin State
Pin(s) While RESET Default Function Alternate Function
Asserted
Pin Function Pin State Pin Function Pin State
CS10/ADDR23/ECLK 1 CS10 1 ADDR23 Unknown
CS[9:6]/ADDR[22:19]/PC[6:3] 1 CS[9:6] 1 ADDR[22:19] Unknown
ADDR[18:0] High-Z output ADDR[18:0] Unknown ADDR[18:0] Unknown
AS/PE5 —1 AS Output PE5 Input
AVEC/PE2 Inactive input AVEC Input PE2 Input
BERR Inactive input BERR Input BERR Input
CS1/BG 1 CS1 1 BG 1
CS2/BGACK 1 CS2 1 BGACK Input
CS0/BR 1 CS0 1 BR Input
CLKOUT Output CLKOUT Output CLKOUT Output
CSBOOT 1 CSBOOT 0 CSBOOT 0
DATA[15:0] Mode select DATA[15:0] Input DATA[15:0] Input
DS/PE4 —1 DS Output PE4 Input
DSACK0/PE0 Inactive input DSACK0 Input PE0 Input
DSACK1/PE1 Inactive input DSACK1 Input PE1 Input
CS[5:3]/FC[2:0]/PC[2:0] 1 CS[5:3] 1 FC[2:0] Unknown
HALT Inactive input HALT Input HALT Input
IRQ[7:1]/PF[7:1] Inactive input IRQ[7:1] Input PF[7:1] Input
MODCLK/PF0 Mode Select MODCLK Input PF0 Input
R/W High-Z output R/W Output R/W Output
RESET Asserted RESET Input RESET Input
RMC/PE3 —1 RMC Output PE3 Input
SIZ[1:0]/PE[7:6] —1 SIZ[1:0] Unknown PE[7:6] Input
TSTME/TSC Mode select TSC Input TSC Input
NOTES:
1. The state of these bus control/port E pins during reset depends on the state of DATA8. If DATA8 is high
during reset (the default), these pins are driven high during reset and come out of reset as bus control
outputs. If DATA8 is held low during reset, these pins are inactive, high-impedance inputs during reset
and come out of reset as port E inputs.

5.7.5.2 Reset States of Pins Assigned to Other MCU Modules

As a rule, module pins that are assigned to general-purpose I/O ports go into a high-
impedance state following reset. Other pin states are determined by individual module
control register settings. Refer to sections concerning modules for details. However,
during power-on reset, module port pins may be in an indeterminate state for a short
period. Refer to 5.7.7 Power-On Reset for more information.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-55
5.7.6 Reset Timing
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high-impedance state or are driven to their inactive states.

When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven to guarantee this length of reset to the entire system.

If an internal source asserts a reset signal, the reset control logic asserts the RESET
pin for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512
cycles, the control logic continues to assert the RESET pin until the internal reset sig-
nal is negated.

After 512 cycles have elapsed, the RESET pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the RESET input is tested. When
the input is at logic level one, reset exception processing begins. If, however, the
RESET input is at logic level zero, reset control logic drives the pin low for another 512
cycles. At the end of this period, the pin again goes to high-impedance state for ten
cycles, then it is tested again. The process repeats until RESET is released.

5.7.7 Power-On Reset

When the SIM clock synthesizer is used to generate system clocks, power-on reset
involves special circumstances related to application of system and clock synthesizer
power. Regardless of clock source, voltage must be applied to the clock synthesizer
power input pin VDDSYN for the MCU to operate. The following discussion assumes
that VDDSYN is applied before and during reset, which minimizes crystal start-up time.
When VDDSYN is applied at power-on, start-up time is affected by specific crystal
parameters and by oscillator circuit design. VDD ramp-up time also affects pin state
during reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage
and timing specifications.

During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The power-on reset circuit releases the internal
reset line as VDD ramps up to the minimum operating voltage, and SIM pins are initial-
ized to the values shown in Table 5-21. When VDD reaches the minimum operating
voltage, the clock synthesizer VCO begins operation. Clock frequency ramps up to
specified limp mode frequency (flimp). The external RESET line remains asserted until
the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-56
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. VDD ramp time and VCO frequency ramp time determine how long the four
cycles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.

Figure 5-18 is a timing diagram for power-on reset. It shows the relationships between
RESET, VDD, and bus signals.

CLKOUT

VCO
LOCK

VDD 1 2 3 4

RESET

BUS
CYCLES
ADDRESS AND 5 6
BUS STATE CONTROL SIGNALS
UNKNOWN THREE-STATED

NOTES:
1. TWO CLOCK CYCLE DELAY REQUIRED BY RESET CONTROL LOGIC TO SWITCH RESET PIN FROM INPUT TO OUTPUT.

2. RESET CONTROL LOGIC DRIVES THE RESET PIN LOW FOR 512 CLOCK CYCLES TO GUARANTEE THIS LENGTH OF RESET TO THE ENTIRE SYSTEM.

3. TEN CLOCK CYCLE DELAY DURING WHICH THE RESET PIN IS NO LONGER DRIVEN AND IS ALLOWED TO RISE TO A LOGIC ONE. OPERATING CONFIGURATION IS
LATCHED FROM DATA[15:0] AND BERR WHEN THIS DELAY BEGINS.

4. ADDITIONAL 180 CLOCK DELAY PROVIDED BY RESET CONTROL LOGIC TO ALLOW THE RESET PIN TO RISE TO A LOGIC ONE IF IT DID NOT DO SO DURING THE
PRIOR 10 CLOCK CYCLES.

5. INTERNAL START-UP TIME.

6. FIRST INSTRUCTION FETCHED.

SIM POR TIM

Figure 5-18 Power-On Reset

5.7.8 Use of the Three-State Control Pin

Asserting the three-state control (TSC) input causes the MCU to put all output drivers
in a disabled, high-impedance state. The signal must remain asserted for approxi-
mately ten clock cycles in order for drivers to change state.

When the internal clock synthesizer is used (MODCLK held high during reset), synthe-
sizer ramp-up time affects how long the ten cycles take. Worst case is approximately
20 milliseconds from TSC assertion.

When an external clock signal is applied (MODCLK held low during reset), pins go to
high-impedance state as soon after TSC assertion as approximately ten clock pulses
have been applied to the EXTAL pin.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-57
NOTE
When TSC assertion takes effect, internal signals are forced to val-
ues that can cause inadvertent mode selection. Once the output
drivers change state, the MCU must be powered down and restarted
before normal operation can resume.

5.7.9 Reset Processing Summary

To prevent write cycles in progress from being corrupted, a reset is recognized at the
end of a bus cycle instead of at an instruction boundary. Any processing in progress
at the time a reset occurs is aborted. After SIM reset control logic has synchronized an
internal or external reset request, the MSTRST signal is asserted.

The following events take place when MSTRST is asserted:

1. Instruction execution is aborted.

2. The status register is initialized.

a. The T0 and T1 bits are cleared to disable tracing.

b. The S bit is set to establish supervisor privilege level.

c. The interrupt priority mask is set to $7, disabling all interrupts below
priority 7.
3. The vector base register is initialized to $000000.
The following events take place when MSTRST is negated after assertion.

1. The CPU32 samples the BKPT input.

2. The CPU32 fetches the reset vector:

a. The first long word of the vector is loaded into the interrupt stack pointer.

b. The second long word of the vector is loaded into the program counter.

c. Vectors can be fetched from external ROM enabled by the CSBOOT

signal.
3. The CPU32 fetches and begins decoding the first instruction to be executed.

5.7.10 Reset Status Register

The reset status register (RSR) contains a bit for each reset source in the MCU. When
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of
reset occur at the same time, only one bit in RSR may be set. The reset status register
is updated by the reset control logic when the RESET signal is released. Refer to
APPENDIX D REGISTER SUMMARY for more information.

5.8 Interrupts
Interrupt recognition and servicing involve complex interaction between the SIM, the
CPU32, and a device or module requesting interrupt service.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-58
The following paragraphs provide an overview of the entire interrupt process. Chip-
select logic can also be used to terminate the IACK cycle with either AVEC or DSACK.
Refer to 5.9 Chip-Selects for more information.

5.8.1 Interrupt Exception Processing

The CPU32 processes interrupts as a type of asynchronous exception. An exception
is an event that preempts normal processing. Each exception has an assigned vector
in an exception vector table that points to an associated handler routine. The CPU32
uses vector numbers to calculate displacement into the table. During exception pro-
cessing, the CPU fetches the appropriate vector and executes the exception handler
routine to which the vector points.

At the release of reset, the exception vector table is located beginning at address
$000000. This value can be changed by programming the vector base register (VBR)
with a new value. Multiple vector tables can be used. Refer to 4.9 Exception Pro-
cessing for more information.

5.8.2 Interrupt Priority and Recognition

The CPU32 provides seven levels of interrupt priority (1-7), seven automatic interrupt
vectors, and 200 assignable interrupt vectors. All interrupts with priorities less than
seven can be masked by the interrupt priority (IP) field in status register.

NOTE
Exceptions such as “address error” are not interrupts and have no
“level” associated. Exceptions cannot ever be masked.

There are seven interrupt request signals (IRQ[7:1]). These signals are used internally
on the IMB, and have corresponding pins for external interrupt service requests. The
CPU32 treats all interrupt requests as though they come from internal modules; exter-
nal interrupt requests are treated as interrupt service requests from the SIM. Each of
the interrupt request signals corresponds to an interrupt priority. IRQ1 has the lowest
priority and IRQ7 the highest.

Interrupt recognition is determined by interrupt priority level and interrupt priority (IP)
mask value. The interrupt priority mask consists of three bits in the CPU32 status reg-
ister. Binary values %000 to %111 provide eight priority masks. Masks prevent an
interrupt request of a priority less than or equal to the mask value from being recog-
nized and processed. IRQ7, however, is always recognized, even if the mask value is
%111.

IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted
until an interrupt acknowledge cycle corresponding to that level is detected.

IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected

unless a falling edge transition is detected on the IRQ7 line. This prevents redundant
servicing and stack overflow. A non-maskable interrupt is generated each time IRQ7
is asserted as well as each time the priority mask is written while IRQ7 is asserted. If

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-59
IRQ7 is asserted and the IP mask is written to any new value (including %111), IRQ7
will be recognized as a new IRQ7.

Interrupt requests are sampled on consecutive falling edges of the system clock. Inter-
rupt request input circuitry has hysteresis. To be valid, a request signal must be
asserted for at least two consecutive clock periods. Valid requests do not cause imme-
diate exception processing, but are left pending. Pending requests are processed at
instruction boundaries or when exception processing of higher-priority interrupts is
complete.

The CPU32 does not latch the priority of a pending interrupt request. If an interrupt
source of higher priority makes a service request while a lower priority request is pend-
ing, the higher priority request is serviced. If an interrupt request with a priority equal
to or lower than the current IP mask value is made, the CPU32 does not recognize the
occurrence of the request. If simultaneous interrupt requests of different priorities are
made, and both have a priority greater than the mask value, the CPU32 recognizes
the higher-level request.

5.8.3 Interrupt Acknowledge and Arbitration

When the CPU32 detects one or more interrupt requests of a priority higher than the
interrupt priority mask value, it places the interrupt request level on the address bus
and initiates a CPU space read cycle. The request level serves two purposes: it is
decoded by modules or external devices that have requested interrupt service, to
determine whether the current interrupt acknowledge cycle pertains to them, and it is
latched into the interrupt priority mask field in the CPU32 status register to preclude
further interrupts of lower priority during interrupt service.

Modules or external devices that have requested interrupt service must decode the IP
mask value placed on the address bus during the interrupt acknowledge cycle and
respond if the priority of the service request corresponds to the mask value. However,
before modules or external devices respond, interrupt arbitration takes place.

Arbitration is performed by means of serial contention between values stored in indi-

vidual module interrupt arbitration (IARB) fields. Each module that can make an
interrupt service request, including the SIM, has an IARB field in its configuration reg-
ister. IARB fields can be assigned values from %0000 to %1111. In order to implement
an arbitration scheme, each module that can request interrupt service must be
assigned a unique, non-zero IARB field value during system initialization. Arbitration
priorities range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an
interrupt service request from a source that has an IARB field value of %0000, a spu-
rious interrupt exception is processed.

WARNING
Do not assign the same arbitration priority to more than one module.
When two or more IARB fields have the same nonzero value, the
CPU32 interprets multiple vector numbers at the same time, with
unpredictable consequences.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-60
Because the EBI manages external interrupt requests, the SIM IARB value is used for
arbitration between internal and external interrupt requests. The reset value of IARB
for the SIM is %1111, and the reset IARB value for all other modules is %0000.

Although arbitration is intended to deal with simultaneous requests of the same

interrupt level, it always takes place, even when a single source is requesting service.
This is important for two reasons: the EBI does not transfer the interrupt acknowledge
read cycle to the external bus unless the SIM wins contention, and failure to contend
causes the interrupt acknowledge bus cycle to be terminated early by a bus error.

When arbitration is complete, the module with both the highest asserted interrupt level
and the highest arbitration priority must terminate the bus cycle. Internal modules
place an interrupt vector number on the data bus and generate appropriate internal
cycle termination signals. In the case of an external interrupt request, after the interrupt
acknowledge cycle is transferred to the external bus, the appropriate external device
must respond with a vector number, then generate data and size acknowledge
(DSACK) termination signals, or it must assert the autovector (AVEC) request signal.
If the device does not respond in time, the SIM bus monitor, if enabled, asserts the bus
error signal (BERR), and a spurious interrupt exception is taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in
response to interrupt requests from external devices. Refer to 5.9.3 Using Chip-
Select Signals for Interrupt Acknowledge for more information. Chip-select address
match logic functions only after the EBI transfers an interrupt acknowledge cycle to the
external bus following IARB contention. If an internal module makes an interrupt
request of a certain priority, and the appropriate chip-select registers are programmed
to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle
for that priority level, chip-select logic does not respond to the interrupt acknowledge
cycle, and the internal module supplies a vector number and generates internal cycle
termination signals.

For periodic timer interrupts, the PIRQ[2:0] field in the periodic interrupt control register
(PICR) determines PIT priority level. A PIRQ[2:0] value of %000 means that PIT inter-
rupts are inactive. By hardware convention, when the CPU32 receives simultaneous
interrupt requests of the same level from more than one SIM source (including external
devices), the periodic interrupt timer is given the highest priority, followed by the IRQ
pins.

5.8.4 Interrupt Processing Summary

A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.

1. The CPU32 finishes higher priority exception processing or reaches an instruc-

tion boundary.
2. The processor state is stacked. The S bit in the status register is set, establish-
ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.
3. The interrupt acknowledge cycle begins:

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-61
a. FC[2:0] are driven to %111 (CPU space) encoding.

b. The address bus is driven as follows: ADDR[23:20] = %1111;

ADDR[19:16] = %1111, which indicates that the cycle is an interrupt
acknowledge CPU space cycle; ADDR[15:4] = %111111111111;
ADDR[3:1] = the priority of the interrupt request being acknowledged; and
ADDR0 = %1.

c. The request level is latched from the address bus into the IP mask field in
the status register.
4. Modules that have requested interrupt service decode the priority value on
ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration
by IARB contention takes place.
5. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
lowing ways:

a. When there is no contention (IARB = %0000), the spurious interrupt

monitor asserts BERR, and the CPU32 generates the spurious interrupt
vector number.

b. The dominant interrupt source (external or internal) supplies a vector

number and DSACK signals appropriate to the access. The CPU32
acquires the vector number.

c. The AVEC signal is asserted (the signal can be asserted by the dominant
external interrupt source or the pin can be tied low), and the CPU32
generates an autovector number corresponding to interrupt priority.

d. The bus monitor asserts BERR and the CPU32 generates the spurious
interrupt vector number.
6. The vector number is converted to a vector address.
7. The content of the vector address is loaded into the PC and the processor
transfers control to the exception handler routine.

5.8.5 Interrupt Acknowledge Bus Cycles

Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during
exception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL
CHARACTERISTICS and the SIM Reference Manual (SIMRM/AD).

5.9 Chip-Selects
Typical microcontrollers require additional hardware to provide external chip-select
and address decode signals. The MCU includes 12 programmable chip-select circuits
that can provide 2 to 16 clock-cycle access to external memory and peripherals.
Address block sizes of 2 Kbytes to 1 Mbyte can be selected. Figure 5-19 is a diagram
of a basic system that uses chip-selects.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-62
VDD VDD VDD VDD VDD VDD

10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ

DSACK1
DSACK0 DTACK

(ASYNC BUS PERIPHERAL)

R/W R/W
CS3 CS

MC68HC681
CS4 IACK
IRQ7 IRQ
ADDR[3:0]
ADDR[17:0] RS[4:1]

DATA[15:8]
DATA[15:0] D[7:0]
VDD

10 kΩ

CSBOOT CE
OE

(FLASH 64K X 16)

WE
ADDR[17:1]
A[16:0]
MC68336/376

DATA[15:0]
VDD VDD DQ[15:0]

10 kΩ 10 kΩ

CS0 E
G

(SRAM 32K X 8)
CS1 W MCM6206D
ADDR[15:1]
A[14:0]

DATA[15:8]
DQ[7:0]

VDD

10 kΩ E
G
(SRAM 32K X 8)
MCM6206D

CS2 W
ADDR[15:1]
A[14:0]

DATA[7:0]
DQ[7:0]

68300 SIM/SCIM BUS

Figure 5-19 Basic MCU System

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-63
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip-select logic can also
generate DSACK and AVEC signals internally. A single DSACK generator is shared
by all chip-selects. Each signal can also be synchronized with the ECLK signal avail-
able on ADDR23.

When a memory access occurs, chip-select logic compares address space type,
address, type of access, transfer size, and interrupt priority (in the case of interrupt
acknowledge) to parameters stored in chip-select registers. If all parameters match,
the appropriate chip-select signal is asserted. Select signals are active low.

If a chip-select function is given the same address as a microcontroller module or an

internal memory array, an access to that address goes to the module or array, and the
chip-select signal is not asserted. The external address and data buses do not reflect
the internal access.

All chip-select circuits are configured for operation out of reset. However, all chip-
select signals except CSBOOT are disabled, and cannot be asserted until the
BYTE[1:0] field in the corresponding option register is programmed to a non-zero
value to select a transfer size. The chip-select option register must not be written until
a base address has been written to a proper base address register. Alternate functions
for chip-select pins are enabled if appropriate data bus pins are held low at the release
of RESET. Refer to 5.7.3.1 Data Bus Mode Selection for more information. Figure
5-20 is a functional diagram of a single chip-select circuit.

INTERNAL
SIGNALS BASE ADDRESS REGISTER

ADDRESS ADDRESS COMPARATOR TIMING

AND PIN
CONTROL
BUS CONTROL OPTION COMPARE

OPTION REGISTER

AVEC DSACK PIN PIN

AVEC GENERATOR GENERATOR ASSIGNMENT DATA
REGISTER REGISTER
DSACK
CHIP SEL BLOCK

Figure 5-20 Chip-Select Circuit Block Diagram

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-64
5.9.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Chip-select pin assignment reg-
isters CSPAR[0:1] determine functions of the pins. Pin assignment registers also
determine port size (8- or 16-bit) for dynamic bus allocation. A pin data register
(PORTC) latches data for chip-select pins that are used for discrete output.

Blocks of addresses are assigned to each chip-select function. Block sizes of two
Kbytes to one Mbyte can be selected by writing values to the appropriate base address
register (CSBAR[0:10] and CSBARBT). Multiple chip-selects assigned to the same
block of addresses must have the same number of wait states. The base address reg-
ister for a chip-select line should be written to a value that is an exact integer multiple
of both the block size and the size of the memory device being selected.

Chip-select option registers (CSORBT and CSOR[0:10]) determine timing of and con-
ditions for assertion of chip-select signals. Eight parameters, including operating
mode, access size, synchronization, and wait state insertion can be specified.

Initialization software usually resides in a peripheral memory device controlled by the

chip-select circuits. A set of special chip-select functions and registers (CSORBT and
CSBARBT) is provided to support bootstrap operation.

Comprehensive address maps and register diagrams are provided in APPENDIX D

5.9.1.1 Chip-Select Pin Assignment Registers

The pin assignment registers contain twelve 2-bit fields that determine the functions of
the chip-select pins. Each pin has two or three possible functions, as shown in Table
5-22.

Table 5-22 Chip-Select Pin Functions

Alternate Discrete
Chip-Select
Function Output
CSBOOT CSBOOT —
CS0 BR —
CS1 BG —
CS2 BGACK —
CS3 FC0 PC0
CS4 FC1 PC1
CS5 FC2 PC2
CS6 ADDR19 PC3
CS7 ADDR20 PC4
CS8 ADDR21 PC5
CS9 ADDR22 PC6
CS10 ADDR23 ECLK

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-65
Table 5-23 shows pin assignment field encoding. Pins that have no discrete output
function must not use the %00 encoding as this will cause the alternate function to be
selected. For instance, %00 for CS0/BR will cause the pin to perform the BR function.

Table 5-23 Pin Assignment Field Encoding

CSxPA[1:0] Description
00 Discrete output
01 Alternate function
10 Chip-select (8-bit port)
11 Chip-select (16-bit port)

Port size determines the way in which bus transfers to an external address are allo-
cated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as
a chip-select. Port size and transfer size affect how the chip-select signal is asserted.
Refer to 5.9.1.3 Chip-Select Option Registers for more information.
Out of reset, chip-select pin function is determined by the logic level on a correspond-
ing data bus pin. The data bus pins have weak internal pull-up drivers, but can be held
low by external devices. Refer to 5.7.3.1 Data Bus Mode Selection for more infor-
mation. Either 16-bit chip-select function (%11) or alternate function (%01) can be
selected during reset. All pins except the boot ROM select pin (CSBOOT) are disabled
out of reset. There are twelve chip-select functions and only eight associated data bus
pins. There is not a one-to-one correspondence. Refer to 5.9.4 Chip-Select Reset
Operation for more detailed information.

The CSBOOT signal is enabled out of reset. The state of the DATA0 line during reset
determines what port width CSBOOT uses. If DATA0 is held high (either by the weak
internal pull-up driver or by an external pull-up device), 16-bit port size is selected. If
DATA0 is held low, 8-bit port size is selected.

A pin programmed as a discrete output drives an external signal to the value specified
in the port C register. No discrete output function is available on pins CSBOOT, BR,
BG, or BGACK. ADDR23 provides the ECLK output rather than a discrete output
signal.

When a pin is programmed for discrete output or alternate function, internal chip-select
logic still functions and can be used to generate DSACK or AVEC internally on an
address and control signal match.

5.9.1.2 Chip-Select Base Address Registers

Each chip-select has an associated base address register. A base address is the low-
est address in the block of addresses enabled by a chip-select. Block size is the extent
of the address block above the base address. Block size is determined by the value
contained in BLKSZ[2:0]. Multiple chip-selects assigned to the same block of
addresses must have the same number of wait states.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-66
BLKSZ[2:0] determines which bits in the base address field are compared to corre-
sponding bits on the address bus during an access. Provided other constraints
determined by option register fields are also satisfied, when a match occurs, the asso-
ciated chip-select signal is asserted. Table 5-24 shows BLKSZ[2:0] encoding.

Table 5-24 Block Size Encoding

BLKSZ[2:0] Block Size Address Lines Compared
000 2 Kbytes ADDR[23:11]
001 8 Kbytes ADDR[23:13]
010 16 Kbytes ADDR[23:14]
011 64 Kbytes ADDR[23:16]
100 128 Kbytes ADDR[23:17]
101 256 Kbytes ADDR[23:18]
110 512 Kbytes ADDR[23:19]
111 1 Mbyte ADDR[23:20]

The chip-select address compare logic uses only the most significant bits to match an
address within a block. The value of the base address must be an integer multiple of
the block size.

After reset, the MCU fetches the initialization routine from the address contained in the
reset vector, located beginning at address $000000 of program space. To support
bootstrap operation from reset, the base address field in the boot chip-select base
address register (CSBARBT) has a reset value of $000, which corresponds to a base
address of $000000 and a block size of one Mbyte. A memory device containing the
reset vector and initialization routine can be automatically enabled by CSBOOT after
a reset. Refer to 5.9.4 Chip-Select Reset Operation for more information.

5.9.1.3 Chip-Select Option Registers

Option register fields determine timing of and conditions for assertion of chip-select
signals. To assert a chip-select signal, and to provide DSACK or autovector support,
other constraints set by fields in the option register and in the base address register
must also be satisfied. The following paragraphs summarize option register functions.
Refer to APPENDIX D REGISTER SUMMARY for register and bit field information.

The MODE bit determines whether chip-select assertion simulates an asynchronous

bus cycle, or is synchronized to the M6800-type bus clock signal ECLK available on
ADDR23. Refer to 5.3 System Clock for more information on ECLK.

BYTE[1:0] controls bus allocation for chip-select transfers. Port size, set when a chip-
select is enabled by a pin assignment register, affects signal assertion. When an 8-bit
port is assigned, any BYTE field value other than %00 enables the chip-select signal.
When a 16-bit port is assigned, however, BYTE field value determines when the chip-
select is enabled. The BYTE fields for CS[10:0] are cleared during reset. However,
both bits in the boot ROM chip-select option register (CSORBT) BYTE field are set
(%11) when the RESET signal is released.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-67
R/W[1:0] causes a chip-select signal to be asserted only for a read, only for a write, or
for both read and write. Use this field in conjunction with the STRB bit to generate
asynchronous control signals for external devices.

The STRB bit controls the timing of a chip-select assertion in asynchronous mode.
Selecting address strobe causes a chip-select signal to be asserted synchronized with
the address strobe. Selecting data strobe causes a chip-select signal to be asserted
synchronized with the data strobe. This bit has no effect in synchronous mode.

DSACK[3:0] specifies the source of DSACK in asynchronous mode. It also allows the
user to optimize bus speed in a particular application by controlling the number of wait
states that are inserted.

NOTE
The external DSACK pins are always active.

SPACE[1:0] determines the address space in which a chip-select is asserted. An

access must have the space type represented by the SPACE[1:0] encoding in order
for a chip-select signal to be asserted.

IPL[2:0] contains an interrupt priority mask that is used when chip-select logic is set to
trigger on external interrupt acknowledge cycles. When SPACE[1:0] is set to %00
(CPU space), interrupt priority (ADDR[3:1]) is compared to the IPL field. If the values
are the same, and other option register constraints are satisfied, a chip-select signal
is asserted. This field only affects the response of chip-selects and does not affect
interrupt recognition by the CPU. Encoding %000 in the IPL field causes a chip-select
signal to be asserted regardless of interrupt acknowledge cycle priority, provided all
other constraints are met.

The AVEC bit is used to make a chip-select respond to an interrupt acknowledge

cycle. If the AVEC bit is set, an autovector will be selected for the particular external
interrupt being serviced. If AVEC is zero, the interrupt acknowledge cycle will be ter-
minated with DSACK, and an external vector number must be supplied by an external
device.

5.9.1.4 Port C Data Register

The port C data register latches data for PORTC pins programmed as discrete out-
puts. When a pin is assigned as a discrete output, the value in this register appears at
the output. PC[6:0] correspond to CS[9:3]. Bit 7 is not used. Writing to this bit has no
effect, and it always reads zero.

5.9.2 Chip-Select Operation

When the MCU makes an access, enabled chip-select circuits compare the following
items:

• Function codes to SPACE fields, and to the IPL field if the SPACE field encoding
is not for CPU space.
• Appropriate address bus bits to base address fields.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-68
• Read/write status to R/W fields.
• ADDR0 and/or SIZ[1:0] bits to BYTE fields (16-bit ports only).
• Priority of the interrupt being acknowledged (ADDR[3:1]) to IPL fields (when the
access is an interrupt acknowledge cycle).
When a match occurs, the chip-select signal is asserted. Assertion occurs at the same
time as AS or DS assertion in asynchronous mode. Assertion is synchronized with
ECLK in synchronous mode. In asynchronous mode, the value of the DSACK field
determines whether DSACK is generated internally. DSACK[3:0] also determines the
number of wait states inserted before internal DSACK assertion.

The speed of an external device determines whether internal wait states are needed.
Normally, wait states are inserted into the bus cycle during S3 until a peripheral
asserts DSACK. If a peripheral does not generate DSACK, internal DSACK generation
must be selected and a predetermined number of wait states can be programmed into
the chip-select option register. Refer to the SIM Reference Manual (SIMRM/AD) for
further information.

5.9.3 Using Chip-Select Signals for Interrupt Acknowledge

Ordinary bus cycles use supervisor or user space access, but interrupt acknowledge
bus cycles use CPU space access. Refer to 5.6.4 CPU Space Cycles and 5.8 Inter-
rupts for more information. There are no differences in flow for chip-selects in each
type of space, but base and option registers must be properly programmed for each
type of external bus cycle.

During a CPU space cycle, bits [15:3] of the appropriate base register must be config-
ured to match ADDR[23:11], as the address is compared to an address generated by
the CPU.

Figure 5-21 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]
are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority,
and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge
code. The rest of the address lines are set to one.

FUNCTION ADDRESS BUS

CODE

2 0 23 19 16 0
INTERRUPT
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
ACKNOWLEDGE

CPU SPACE
TYPE FIELD

CPU SPACE IACK TIM

Figure 5-21 CPU Space Encoding for Interrupt Acknowledge

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-69
Because address match logic functions only after the EBI transfers an interrupt
acknowledge cycle to the external address bus following IARB contention, chip-select
logic generates AVEC or DSACK signals only in response to interrupt requests from
external IRQ pins. If an internal module makes an interrupt request of a certain priority,
and the chip-select base address and option registers are programmed to generate
AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority
level, chip-select logic does not respond to the interrupt acknowledge cycle, and the
internal module supplies a vector number and generates an internal DSACK signal to
terminate the cycle.

Perform the following operations before using a chip-select to generate an interrupt

acknowledge signal:

1. Program the base address field to all ones.

2. Program block size to no more than 64 Kbytes, so that the address comparator
checks ADDR[19:16] against the corresponding bits in the base address regis-
ter. (The CPU32 places the CPU space bus cycle type on ADDR[19:16].)
3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as
a read cycle.
4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector
for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte
when using an 8-bit port.

If an interrupting device does not provide a vector number, an autovector acknowl-

edge must be generated, either by asserting the AVEC pin or by generating AVEC
internally using the chip-select option register. This terminates the bus cycle.

5.9.4 Chip-Select Reset Operation

The least significant bit of each of the 2-bit chip-select pin assignment fields in
CSPAR0 and CSPAR1 each have a reset value of one. The reset values of the most
significant bits of each field are determined by the states of DATA[7:1] during reset.
There are weak internal pull-up drivers for each of the data lines so that chip-select
operation is selected by default out of reset. However, the internal pull-up drivers can
be overcome by bus loading effects.

To ensure a particular configuration out of reset, use an active device to put the data
lines in a known state during reset. The base address fields in chip-select base
address registers CSBAR[0:10] and chip-select option registers CSOR[0:10] have the
reset values shown in Table 5-25. The BYTE fields of CSOR[0:10] have a reset value
of “disable”, so that a chip-select signal cannot be asserted until the base and option
registers are initialized.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-70
Table 5-25 Chip-Select Base and Option Register Reset Values
Fields Reset Values
Base address $000000
Block size 2 Kbyte
Async/sync mode Asynchronous mode
Upper/lower byte Disabled
Read/write Disabled
AS/DS AS
DSACK No wait states
Address space CPU space
IPL Any level
Autovector External interrupt vector

Following reset, the MCU fetches the initial stack pointer and program counter values
from the exception vector table, beginning at $000000 in supervisor program space.
The CSBOOT chip-select signal is used to select an external boot device mapped to
a base address of $000000.

The MSB of the CSBTPA field in CSPAR0 has a reset value of one, so that chip-select
function is selected by default out of reset. The BYTE field in chip-select option register
CSORBT has a reset value of “both bytes” so that the select signal is enabled out of
reset. The LSB of the CSBOOT field, determined by the logic level of DATA0 during
reset, selects the boot ROM port size. When DATA0 is held low during reset, port size
is eight bits. When DATA0 is held high during reset, port size is 16 bits. DATA0 has a
weak internal pull-up driver, so that a 16-bit port is selected by default out of reset.
However, the internal pull-up driver can be overcome by bus loading effects. To
ensure a particular configuration out of reset, use an active device to put DATA0 in a
known state during reset.

The base address field in the boot chip-select base address register CSBARBT has a
reset value of all zeros, so that when the initial access to address $000000 is made,
an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of 1 Mbyte. Table 5-26 shows CSBOOT reset values.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-71
Table 5-26 CSBOOT Base and Option Register Reset Values
Fields Reset Values
Base address $000000
Block size 1 Mbyte
Async/sync mode Asynchronous mode
Upper/lower byte Both bytes
Read/write Read/write
AS/DS AS
DSACK 13 wait states
Address space Supervisor/user space
IPL1 Any level
Autovector Interrupt vector externally
NOTES:
1. These fields are not used unless “Address space” is set to CPU space.

5.10 Parallel Input/Output Ports

Sixteen SIM pins can be configured for general-purpose discrete input and output.
Although these pins are organized into two ports, port E and port F, function assign-
ment is by individual pin. Pin assignment registers, data direction registers, and data
registers are used to implement discrete I/O.

5.10.1 Pin Assignment Registers

Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the
functions of the pins on each port. Any bit set to one defines the corresponding pin as
a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O
pin.

5.10.2 Data Direction Registers

Bits in the port E and port F data direction registers (DDRE and DDRF) control the
direction of the pin drivers when the pins are configured as I/O. Any bit in a register set
to one configures the corresponding pin as an output. Any bit in a register cleared to
zero configures the corresponding pin as an input. These registers can be read or
written at any time.

5.10.3 Data Registers

A write to the port E and port F data registers (PORTE[0:1] and PORTF[0:1]) is stored
in an internal data latch, and if any pin in the corresponding port is configured as an
output, the value stored for that bit is driven out on the pin. A read of a data register
returns the value at the pin only if the pin is configured as a discrete input. Otherwise,
the value read is the value stored in the port data register. Both data registers can be
accessed in two locations and can be read or written at any time.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-72
5.11 Factory Test
The test submodule supports scan-based testing of the various MCU modules. It is
integrated into the SIM to support production test. Test submodule registers are
intended for Motorola use only. Register names and addresses are provided in
APPENDIX D REGISTER SUMMARY to show the user that these addresses are
occupied. The QUOT pin is also used for factory test.

MC68332 SYSTEM INTEGRATION MODULE MOTOROLA

USER’S MANUAL Rev. 15 Oct 2000 5-73
MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 5-74

Atmega32A DataSheet Complete DS40002072A 3
No ratings yet
Atmega32A DataSheet Complete DS40002072A 3
15 pages
Lec3 Timers
No ratings yet
Lec3 Timers
51 pages
EE447 Week7 2023-24
No ratings yet
EE447 Week7 2023-24
81 pages
Unlock-Doc2466 2
No ratings yet
Unlock-Doc2466 2
10 pages
MCU Power & Clock Techniques
No ratings yet
MCU Power & Clock Techniques
12 pages
C 2 Nomen
No ratings yet
C 2 Nomen
4 pages
3.4.5 Boot Modes: Chapter 3: Getting It Working
No ratings yet
3.4.5 Boot Modes: Chapter 3: Getting It Working
11 pages
MC68B50 PDF
No ratings yet
MC68B50 PDF
12 pages
Unit Iii Esd
No ratings yet
Unit Iii Esd
38 pages
DS12C887
No ratings yet
DS12C887
20 pages
Embedded System Architecture Slides
100% (2)
Embedded System Architecture Slides
40 pages
Uart 8250a
No ratings yet
Uart 8250a
19 pages
Design, Modeling and Simulation Methodology For Source Synchronous DDR Memory Subsystems
No ratings yet
Design, Modeling and Simulation Methodology For Source Synchronous DDR Memory Subsystems
5 pages
PD6125A, 6126A: Mos Integrated Circuit
No ratings yet
PD6125A, 6126A: Mos Integrated Circuit
40 pages
PDF ICT114-Sem5
No ratings yet
PDF ICT114-Sem5
52 pages
MODCOMP II Computer Reference Manual
No ratings yet
MODCOMP II Computer Reference Manual
156 pages
Emb MCQ
No ratings yet
Emb MCQ
11 pages
Clock and Fuses: Prof. Prabhat Ranjan Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar
No ratings yet
Clock and Fuses: Prof. Prabhat Ranjan Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar
39 pages
PD 6124 A
No ratings yet
PD 6124 A
36 pages
Clarification To The Serial I/O Control Register Description For The DSP1620/27/28/29 Devices
No ratings yet
Clarification To The Serial I/O Control Register Description For The DSP1620/27/28/29 Devices
115 pages
Icm 7170
No ratings yet
Icm 7170
3 pages
8085 Data Sheet
No ratings yet
8085 Data Sheet
20 pages
Pin No. Pin Name Description Alternate Function
No ratings yet
Pin No. Pin Name Description Alternate Function
6 pages
MPC860 Board Design Checklist
No ratings yet
MPC860 Board Design Checklist
8 pages
(Inf) Sda3302 Serie
No ratings yet
(Inf) Sda3302 Serie
28 pages
¡ Semiconductor: MSM80C85AHRS/GS/JS
No ratings yet
¡ Semiconductor: MSM80C85AHRS/GS/JS
29 pages
Interfacing of MSP430
No ratings yet
Interfacing of MSP430
15 pages
Datasheet 80C85 (Oki)
No ratings yet
Datasheet 80C85 (Oki)
29 pages
System Timer
No ratings yet
System Timer
14 pages
MSP430FG4618 Dev Guide
No ratings yet
MSP430FG4618 Dev Guide
77 pages
SY6502 Microprocessor Datasheet
No ratings yet
SY6502 Microprocessor Datasheet
37 pages
Embedded Firmware
No ratings yet
Embedded Firmware
7 pages
Microprocessor ch8 1
No ratings yet
Microprocessor ch8 1
14 pages
Mastering STM32F407VGT6 - Clock Control System
No ratings yet
Mastering STM32F407VGT6 - Clock Control System
10 pages
Embedded Systems Course Guide
No ratings yet
Embedded Systems Course Guide
21 pages
AT91RM9200 Microcontroller Schematic Check List: At91Sam ARM-based Embedded MPU Application Note
No ratings yet
AT91RM9200 Microcontroller Schematic Check List: At91Sam ARM-based Embedded MPU Application Note
17 pages
PC16552D - Dual Universal AsynchronousReceiver-Transmitter With FIFO
No ratings yet
PC16552D - Dual Universal AsynchronousReceiver-Transmitter With FIFO
21 pages
8085 Pin Diagram
No ratings yet
8085 Pin Diagram
4 pages
Cortex-M0+ Interrupt & Clock Guide
No ratings yet
Cortex-M0+ Interrupt & Clock Guide
45 pages
HT48RA3 8-Bit Remote Type OTP MCU: Features
No ratings yet
HT48RA3 8-Bit Remote Type OTP MCU: Features
37 pages
Microprocessor Based System Communication
No ratings yet
Microprocessor Based System Communication
39 pages
CSDVCXVFDXGBVFDGFDFSDFGFDGFCGGCF Gjhghfgjjmgxjgdjpin No. Pin Name Description Alternate Function
No ratings yet
CSDVCXVFDXGBVFDGFDFSDFGFDGFCGGCF Gjhghfgjjmgxjgdjpin No. Pin Name Description Alternate Function
8 pages
Real Clock Time
No ratings yet
Real Clock Time
2 pages
Microprocessor-and-Microcontroller Notes To Print
No ratings yet
Microprocessor-and-Microcontroller Notes To Print
118 pages
DS12887
No ratings yet
DS12887
30 pages
Inter-Processor Communication: Application Note
No ratings yet
Inter-Processor Communication: Application Note
9 pages
Unit3 Esd
No ratings yet
Unit3 Esd
25 pages
Peripherai Interface Microprocessor 68000
No ratings yet
Peripherai Interface Microprocessor 68000
40 pages
DIY Digital Clock with 8051
No ratings yet
DIY Digital Clock with 8051
18 pages
11 Interrupts
No ratings yet
11 Interrupts
26 pages
Pic Microcontroller 2.1 Pic It Is A Family of Modified Harvard Architecture Microcontrollers Made
100% (1)
Pic Microcontroller 2.1 Pic It Is A Family of Modified Harvard Architecture Microcontrollers Made
16 pages
CH32V003DS0
No ratings yet
CH32V003DS0
33 pages
8-Bit CMOS Microcontroller: User's Manual 04.98
No ratings yet
8-Bit CMOS Microcontroller: User's Manual 04.98
160 pages
Infineon SAFC515LN Datasheet PDF
No ratings yet
Infineon SAFC515LN Datasheet PDF
160 pages
MC68332 Microcontroller Guide
No ratings yet
MC68332 Microcontroller Guide
56 pages
Tpupn 05
No ratings yet
Tpupn 05
33 pages
Tpupn 03
No ratings yet
Tpupn 03
17 pages
Tpupn 02
No ratings yet
Tpupn 02
21 pages
State of New York
No ratings yet
State of New York
2 pages
M 332 CVR
No ratings yet
M 332 CVR
2 pages
State of New York
No ratings yet
State of New York
2 pages
Ua 9638
No ratings yet
Ua 9638
18 pages
(2010) (Modern Communications Receiver Design and Technology)
No ratings yet
(2010) (Modern Communications Receiver Design and Technology)
487 pages
MX300 Maint Manual-Complete 2-09
100% (2)
MX300 Maint Manual-Complete 2-09
148 pages
Fully Integrated Frequency Synthesizers
No ratings yet
Fully Integrated Frequency Synthesizers
37 pages
Phase Locked Loop
0% (1)
Phase Locked Loop
30 pages
RDA Microelectronics RDA5807MS - C167246
No ratings yet
RDA Microelectronics RDA5807MS - C167246
21 pages
BK4815N Datasheet v1.0.1
No ratings yet
BK4815N Datasheet v1.0.1
47 pages
FCC Certification Tests For The VHF-920 Communications Transceiver
No ratings yet
FCC Certification Tests For The VHF-920 Communications Transceiver
7 pages
Miniature Multimode Deep Ground Penetrating Radar: Chun-Lin Huang, Shi-Ping Zhu, Ming Lu
No ratings yet
Miniature Multimode Deep Ground Penetrating Radar: Chun-Lin Huang, Shi-Ping Zhu, Ming Lu
5 pages
Design and Implementation of Voltage Controlled Ring Oscillator Using 90nm CMOS Technology
No ratings yet
Design and Implementation of Voltage Controlled Ring Oscillator Using 90nm CMOS Technology
6 pages
Service Manual: NX-220 K, E3 NX-220 K2, E2 NX-220 K3, E
No ratings yet
Service Manual: NX-220 K, E3 NX-220 K2, E2 NX-220 K3, E
92 pages
Drake Docs 01
No ratings yet
Drake Docs 01
156 pages
PLL & Applications
100% (1)
PLL & Applications
7 pages
Phase-Locked Loop (PLL) Guide
100% (1)
Phase-Locked Loop (PLL) Guide
40 pages
802.11ac Frequency Synthesizer Design
No ratings yet
802.11ac Frequency Synthesizer Design
3 pages
RF Ic Design Model - Set
No ratings yet
RF Ic Design Model - Set
3 pages
A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS
No ratings yet
A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS
13 pages
Analog - PLL Performance, Simulation, and Design 4th
No ratings yet
Analog - PLL Performance, Simulation, and Design 4th
339 pages
1GHz PLL Clock Multipliers in Digital Systems
100% (1)
1GHz PLL Clock Multipliers in Digital Systems
3 pages
EV-ADF4355-2SD1Z User Guide: Evaluating The Fractional-N/Integer-N PLL Frequency Synthesizer
No ratings yet
EV-ADF4355-2SD1Z User Guide: Evaluating The Fractional-N/Integer-N PLL Frequency Synthesizer
18 pages
GATE 2016 EC (Set-1)
No ratings yet
GATE 2016 EC (Set-1)
42 pages
The CB PLL Data Book
No ratings yet
The CB PLL Data Book
114 pages
A Low Power Single Phase Clock Distribution Using VLSI Technology
100% (1)
A Low Power Single Phase Clock Distribution Using VLSI Technology
5 pages
University of Mumbai Online Examination 2020
No ratings yet
University of Mumbai Online Examination 2020
17 pages
M506 Service Manual
100% (1)
M506 Service Manual
47 pages
Frequency Synthesizer
No ratings yet
Frequency Synthesizer
3 pages
Low-Power Wireless Communication Circuits and Systems 60GHz and Beyond - Kaixue Ma and Kiat Seng Yeo
100% (3)
Low-Power Wireless Communication Circuits and Systems 60GHz and Beyond - Kaixue Ma and Kiat Seng Yeo
359 pages
VL4292
No ratings yet
VL4292
15 pages
FM Modulation Lab Guide
No ratings yet
FM Modulation Lab Guide
12 pages
ADF4002
No ratings yet
ADF4002
20 pages
MC145151 2
No ratings yet
MC145151 2
24 pages