VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY – UNIVERSITY OF TECHNOLOGY

FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING

DEPARTMENT OF ELECTRONICS
--oOo—

INTRODUCTION TO COMPUTING
LABORATORY MANUAL
 Appendix 2: Sample lab.

LAB 4: IMPLEMENTATION OF BASIC

COMBINATIONAL AND SEQUENTIAL
LOGIC CIRCUITS ON FPGA
Họ và tên: GROUP 02 Lớp TN: TT04
MSSV: Ngày:

A. PRELAB
PREPARATION 1
Objectives: Describe Full Adder circuit using SystemVerilog.
Read the following program.
module FA_ex1(
input A,
input B,
input Ci,
output S,
output Co);

assign S = A ^ B ^ Ci;
assign Co=(A&B)|(A&Ci)|(B&Ci);
Figure 4.1: Full Adder
endmodule
➢ Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform.
 Appendix 2: Sample lab.

PREPARATION 2
Objective: Describe 4-bit adder/subtractor using SystemVerilog.
Design 4-bit adder/subtractor which has 2 inputs A and B respectively, 1 output S and the flags
Ci and Co. Its operation depends on the input sel:
o sel=0: S = A + B
o sel=1: S = A - B

Students write the SystemVerilog code that performs the operation of the combinational circuit
in two methods:
- Method 1: Instantiate Full Adder module (using preparatory lesson 1).

Hint:
wire wire0,wire1,wire2
FA_ex1 u0(.Ci(0),.A(A[0]),.B(B[0]),.S(S[0]),.Co(wire0));
FA_ex1 u1(.Ci(wire1),.A([1]),.B([1]),.S(S[1]),.Co(wire1));
…

- Method 2: Write SystemVerilog code using data flow model.

Hint:
always@(*) assign S=(sel)?A+B:A-B;
if (sel)
…
else
…

➢ Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform.
 Appendix 2: Sample lab.

PREPARATION 3
Objective: Design the combinational circuit that decodes BCD numbers to common anode 7-
segment LED codes.
Complete the truth table of the decoder circuit:
I3 I2 I1 I0 g f e d c b a
0 0 0 0 1 0 0 0 0 0 0
0 0 0 1 1 1 1 1 0 0 1
0 0 1 0 0 1 0 0 1 0 0
0 0 1 1 0 1 1 0 0 0 0
0 1 0 0 0 0 1 1 0 0 1
0 1 0 1 0 0 1 0 0 1 0
0 1 1 0 0 0 0 0 0 1 0
0 1 1 1 1 1 1 1 0 0 0
1 0 0 0 0 0 0 0 0 0 0 Figure 4.2 Common anode 7-segment
1 0 0 1 0 0 1 0 0 0 0 LED
1 0 1 0 0 0 0 0 0 1 1 (source: internet)

1 0 1 1 1 0 0 0 1 1 0
1 1 0 0 0 1 0 0 0 0 1
1 1 0 1 0 0 0 0 1 1 0
1 1 1 0 0 0 0 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1
Table 4.1

➢ Write SystemVerilog code that describe the decoder.

Hint: Use case statement….

input [3:0]I;
always@(*) begin
case(I)
4’b0000: out <= 7’b1000000;
4’b0001: out <= …
…
endcase;
 Appendix 2: Sample lab.

end
➢ Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform.

PREPARATION 4
Objective: Design a circuit that converts a pulse of frequency 50 MHz to a pulse of frequency 1
Hz.
Gợi ý:
- A pulse of frequency 50MHz will make 50 000 000 oscillations in 1s. (1 oscillation consists
of 1 high-level and 1 low-level).
- A pulse with a frequency of 1Hz will make 1 oscillation in 1s.
- Applying the principle of the counter circuit, the circuit receives an input pulse of 50MHz,
when the input pulse counts 25 000 000, that will reverse the state of the output pulse.

Hint:
integer i=0;
 Appendix 2: Sample lab.

reg temp=0;
always_ff@(posedge clk)
begin
i = i + 1;
if (i == 25 000 000) begin
out = ~ out;
i = 0;
end
end

➢ Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform.

PREPARATION 5
Objective: Describe a state machine using systemverilog.
➢ Draw a state machine for the requirement in experiment 5 of Lab 4. Students explain the
meaning of states and encode the state into a bit string.
➢ Students design the state machine above using systemverilog language. (Refer to the
program below.) Assume the state machine have :
o Input: X (1 bits)
o Output: Y (1 bits)

There are 4 states: S0 (00), S1 (01), S2 (10), S3(11)

 Appendix 2: Sample lab.

FSM code:

input X; // Input declaration

input clk; // Clock declaration
output reg [1:0]Y; // Output declaration
parameter S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11; //State definition
reg [1:0]pre_state, next_state; //State register
// Synchronous State-Transition always@(posedge Clock) block
always@(posedge clk) begin
if (rst) begin
pre_state <= S0;
end
else
pre_state <= next_state;
end
// Conditional State Transition always@(pre_state or X) block
always@(pre_state or X) begin
case(pre_state)
S0: if (X) next_state <= S1;
else next_state <= S0;
S1: if (!X) next_state <= S2;
else next_state <= S0;
S2: if (!X) next_state <= S3;
else next_state <= S2;
S3: if (!X) next_state <= S0;
else next_state <= S3;
endcase;
end
// Output Logic depending on the state
 Appendix 2: Sample lab.

always@(*) begin
case (pre_state)
S0: Y <= 2'b00;
S1: Y <= 2'b10;
S2: Y <= 2'b11;
S3: Y <= 2'b01;
endcase;
end

➢ Compile the above program. Then, students simulate the output waveform in all cases
of the input. Capture the output waveform.

➢
 Appendix 2: Sample lab.

B. LAB MANUAL

I. OBJECTIVES

- Understand how to use FPGA kits, programming software.

- Understand how to design a basic combinational and sequential logic circuits on FPGA.
- Understand the process of describing hardware on FPGAs.

II. PREPARATION:

- To prepare well for the test, students MUST read Appendix 1 first and complete the steps
of Sample lab in Appendix 2, and submit it with Prelab 4 before entering class.
- Students must complete and submit Prelab 4 before entering class.
- Students read the appendix and the Kit DE2 Manual to understand how to use the DE2
Kit, wiring, peripherals, and how to use Quartus software to simulate and synthesize
circuits. Students refer to the documentation to understand how to write hardware
designs in the SystemVerilog language.

III. LAB INSTRUCTIONS

EXPERIMENT 1
Objective: Design the combinational circuit that calculates the absolute value of a 4-bit number
(the input is A, the output is S).
➢ Students draw the logic gate diagram of the circuit to be designed

➢ Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:
 Appendix 2: Sample lab.

o Pins A[3:0] assigned to SW[3:0]

o Pins S[3:0] assigned to LEDR[3:0].

➢ Students compile the above program. Then, students simulate the output waveform in all
cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)

➢ Students view the results (Tool → Netlist Viewer → RTL Viewer) of the circuit.
 Appendix 2: Sample lab.

➢ Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
 Appendix 2: Sample lab.

EXPERIMENT 2
Objective: Design the combinational circuit that implements the ALU
The ALU calculates two 4-bit numbers (the two inputs are A and B respectively, the output is
S, the flags are Ci and Co) through the 2-bit input: Sel.

- If Sel=00: S=A+B

- If Sel=01: S=A-B

- If Sel=10: S=A AND B

- If Sel=11: S=A OR B

➢ Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Pins A[3:0] assigned to SW[3:0]

o Pins B[3:0] assigned to SW[7:4]

o Pins Ci assigned to SW[8]

o Pins S[3:0] assigned to LEDR[3:0]

o Pins Co assigned to LEDR[4]

➢ Students compile the above program. Then, students simulate the output waveform in all
cases of the input. Capture the output waveform.
 Appendix 2: Sample lab.

(Insert a photo demonstrating that the student has simulated the circuit).

➢ Students view the results (Tool → Netlist Viewer → RTL Viewer) of the circuit..

➢ Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
 Appendix 2: Sample lab.

EXPERIMENT 3
Objective: Design a 3-bit down counter circuit.
The count value changes every 1s. The output is connected to a common anode 7-segment LED.
In addition, the counter has an RST pin (active high) used to reset the counter state to 0.

Hint:

- The clock signal is generated from the frequency divider from 50MHz to 1Hz.

- Students use the 7-segment LED decoder module in PRELAB, connecting the output of
the counter to the input of the module.

➢ Students draw the logic gate diagram of the circuit to be designed

 Appendix 2: Sample lab.

➢ Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o 7-segment LED ouput assigned to HEX[0]

o Pins RST assigned to SW[0]

➢ Students compile the above program. Then, students simulate the output waveform in all
cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)
 Appendix 2: Sample lab.

➢ Students view the results (Tool → Netlist Viewer → RTL Viewer) of the circuit.

➢ Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
 Appendix 2: Sample lab.

EXPERIMENT 4
Objective: Design a 4-bit up counter circuit from 5 to 14.
The count value changes every 1s. The output is connected to a common anode 7-segment LED.
In addition, the counter has an RST pin (active high) used to reset the counter state to 0.

Hint:

- The clock signal is generated from the frequency divider from 50MHz to 1Hz.

- Students use the 7-segment LED decoder module in PRELAB, connecting the output
of the counter to the input of the module.

- Students need to write a 4-bit binary to BCD converter module.

➢ Students draw the logic gate diagram of the circuit to be designed

 Appendix 2: Sample lab.

➢ Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Two 7-segment LED outputs assigned to HEX [1], HEX[0]

o Pins RST assigned to SW[0]

➢ Students compile the above program. Then, students simulate the output waveform in all
cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)
 Appendix 2: Sample lab.

➢ Students view the results (Tool → Netlist Viewer → RTL Viewer) of the circuit.

➢ Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
 Appendix 2: Sample lab.

EXPERIMENT 5
Objective: Design a sequential circuit has 1 input (X) and 1 output (Z). Output Z = 1 if the total
number of bit 1 received is divisible by 3 (0, 3, 6, 9, … are numbers divisible by 3 ) and the total
number of 0 bits received is an even number (greater than 0).
Note:

- Students design a sequential circuit according to Mealy or Moore type state machines.

- The clock signal is generated from the frequency divider from 50MHz to 1Hz.

➢ Students draw the logic gate diagram of the circuit to be designed

➢ Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Input X assigned SW[0]

 Appendix 2: Sample lab.

o Output Z assigned to LEDR[0]

➢ Students compile the above program. Then, students simulate the output waveform in all
cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)

➢ Students view the results (Tool → Netlist Viewer → RTL Viewer) of the circuit.
 Appendix 2: Sample lab.

➢ Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)

EXPERIMENT 6
Objective: Describe FSM using SystemVerilog.
An automatic pet food and water supply system with 2 inputs are 2 push buttons RED, BLUE;
and 2 outputs are FOOD, WATER signals to activate the food and water
 Appendix 2: Sample lab.

• RED button (R signal, pressing R=1, otherwise R=0): when the animal needs to eat,
press the RED button 3 times. Then signal F (FOOD) = 1 to activate the food supply
machine.
• BLUE button (signal B; pressing B=1, otherwise B=0): when the animal wants to
drink, press the BLUE button 2 times. Then signal W (WATER) = 1 to activate the
water supply machine.

Note:

- Students design a sequential circuit according to Mealy or Moore type state machines.

- The clock signal is generated from the frequency divider from 50MHz to 1Hz

- When the signal F or W is equal to 1, if any button is pressed, the system will return to
the reset state.

- At each time, there is only 1 button pressed.

- Buttons need to be operated consecutively, if there is 1 button in the wrong sequence,

the state machine will return to the original state. (e.g. when the buttons are pressed in
sequence (RED, RED, BLUE), the state machine returns to the reset state).

➢ Students draw block diagram (state machines)

 Appendix 2: Sample lab.

➢ Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Input RED and BLUE assigned SW[1:0]

o Output FOOD and WATER assigned to LEDR[1:0]

➢ Students compile the above program. Then, students simulate the output waveform in all
cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)
 Appendix 2: Sample lab.

➢ Students view the results (Tool → Netlist Viewer → RTL Viewer) of the circuit.

➢ Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)