Verilog HDL Basics
▪ Verilog was adopted as an official standard as IEEE Standard 1364-1995 in 1995.
▪ An enhanced version, called Verilog-2001, was adopted in 2001 as IEEE Standard
1364-2001.
▪ Originally intended for simulation, today Verilog is designed to facilitate describe
digital hardware for both simulation and synthesis.
▪ Verilog is a great low level language.
▪ The syntax is regular and easy to remember. It is the fastest HDL language to learn
and use.
▪ Verilog has also been extended for implementation and verification called System
Verilog.
Verilog Design Unit
▪ A digital circuit or system in Verilog is known as a module.
▪ A module has two parts:
◗ module declaration
• specifies input and output connections (ports) to the module
◗ behaviour statements (or module items)
• defines behaviour of the hardware entity
Verilog Design Unit – cont.
module module_name(ports);
{parameter declarations}
input <port list>; // input/output declarations
output <port list>;
wire <list>; // nets
reg (or integer) <list>; // variables
{assign continuous statement;} // behaviour statements
{initial blocks;}
{always blocks;}
{gate instantiations;}
{module instantiations;}
endmodule
Verilog Design Unit – cont.
▪ A port in Verilog may be input, output, or inout
◗ module ports can connect to ports of other modules
▪ Keyword wire used to declare nets
▪ All port declarations inherently declared as wire
◗ a port is automatically declared as wire if it is defined as input, output,
or inout
▪ Keyword reg used to declare variables
◗ similar to variables in software languages
◗ reg declaration has nothing to do with hardware register
Verilog Design Unit – cont.
▪ Each line of Verilog text terminated with semicolon, except for
endmodule keyword.
▪ Verilog is case-sensitive.
▪ Names (or identifiers) used for modules, parameters, ports,
variables, and instances of modules, must begin with letters.
▪ Keywords cannot be used for names.
Verilog Design Unit – cont.
▪ Ports Cin, x, and y are scalar (1-bit)
inputs.
module circuitA(Cin, x, y, X, Y, Cout, s, Bus, S);
▪ Ports X and Y are 4-bit vectored input Cin, x, y;
inputs. input[3:0] X, Y;
output Cout, s;
▪ Cout and s are 1-bit outputs. output[3:0] S;
inout[7:0] Bus;
▪ S is 4-bit vectored output.
▪ Bus is an 8-bit bidirectional port. wire d;
reg e;
▪ d is internal signal. ...
endmodule
▪ e is a variable.
Verilog Constructs
Verilog 1995 Verilog 2001
module circuitA1995 ( a, b, c, x, y, z ); module circuitA2001 (
input a, b, c; input a, b, c,
output x,y, z; output x, y,
reg z; //z is an output of a register output reg z);
… …
endmodule endmodule
4
Representation of Numbers
▪ 4-value logic – 0, 1, Z, X
◗ 0 for logic 0 or Gnd
◗ 1 for logic 1
◗ Z for float
◗ X for uninitialized, undefined, or unknown
▪ Numbers can be binary (b), octal (o), hex (h), or decimal (d).
▪ Number sizes can be fixed or unspecified.
▪ For sized numbers, format is:
<size-in-bits>’<radix-identifier><significant-digits>
◗ decimal 2217 can be represented using 12 bits
• binary - 12’b100010101001
• hex - 12’h8A9
• decimal - 12’d2217
Representation of Numbers – cont.
▪ Unsigned numbers are given without specifying size
◗ ‘b100010110 or ‘h116 or 278 represent decimal 278
• for decimal, radix identifier is not necessary
▪ Negative number representation example
◗ -5 is specified as -4’b101
• interpreted as 4-bit 2’s complement of 5, which is 1011
▪ 12’b100010101001 may be written as 12’b1000_1010_1001 to improve read-ability.
▪ 8’hx denotes unknown 8-bit number.
Representation of Numbers – cont.
-6
Operators in Verilog
Operator type Operator symbol Operation
Bitwise ~, &, ~&, |, not, and, nand, or, xor, xnor
^, ~^
Logical !, &&, || logical negation, logical and, logical or
Arithmetic +, -, *, /, add, sub, mult, divide, modulus, power
%, **
Relational >, <, >=, <= Gt, Lt, Gt or eq, Lt or eq
Equality ==, !=, ===, !== Logical equality, logical inequality, case equality, case
inequality
Logical Shift >>, << Logical right shift, Logical left shift
Arithmetic >>>, <<< Arithmetic right shift, Arithmetic left shift
Shift
Concatenation { , }
Conditional ?:
Operators in Verilog – cont.
▪ Bitwise operator produce same number of bits as operands
◗ A = a1a0, B = b1b0, C = c1c0
• C = A | B results in c1 = a1 | b1 and c0 = a0 | b0
▪ Logical operator generates one-bit result – used in conditional
statements
◗ A || B results in 1 unless both A and B are zeros
◗ A && B produce 1 if both A and B are nonzeros
◗ !A gives 1 if all bits are 0, otherwise 1
▪ Relational operator outputs 1 or 0 based on comparison of A
and B
▪ A and B must be declared as wire or reg for design to be
synthesizable
Operators in Verilog – cont.
▪ Shift operators perform logical 1-bit shifts to the right or left
◗ zeros shifted into LSB for left shift
◗ zeros into MSB for right shift
▪ Conditional operation A ? B : C produce result equal to B if A evaluates to 1,
otherwise result is C.
▪ Precedence of Verilog operators similar to that found in arithmetic and Boolean
algebra.
Verilog Modelling
Styles
▪ Different circuit complexities
(e.g., simple modules to
complete systems) require
different kinds of
specification or levels of
abstraction.
▪ Three modelling styles in HDL-
based design of digital systems
◗ Structural modelling
◗ Dataflow modelling
◗ Behavioral modelling
Verilog Modelling Styles – cont.
is a top level design that is synthesized by instantiating lower level modules
(or submodules) and primitives (built in or user defined) into a larger
Structural
structural module. This modelling applies the hierarchical modular design
modelling approach in design. It also used to describe a schematic.
output signals are specified in terms of input signal transformation based on
Dataflow Boolean equations. This modelling is used to design combinational logic
modelling circuits only. It described using continuous assignment statements.
describes the operation or expected behaviour of the design module in an
Behavioral algorithmic manner. There is no regard to the structural realization of the
modelling design. This style is the closest to a natural language description of the
circuit functionality. The behaviour of the design is described using
sequential assignment statement
Dataflow Modelling
# Verilog-1995
module func2 (x1, x2, x3, f) ;
func2 input x1, x2, x3;
output f ;
x1
Logic assign f = ( ~x1 & ~x2 & x3)
x2 f
Function | (x1 & ~x2 & ~x3)
x3 | (x1 & ~x2 & x3)
| (x1 & x2 & ~x3) ;
endmodule
Dataflow Modelling – cont. a b
HA
▪ HA description using continuous s = a + b
assignment statements c = a . b
◗ also called simply as continuous statements
◗ also known as concurrent statements
◗ statements executed concurrently whenever s c
any value on RHS changes
▪ Another type of statements are called
procedural assignment statements # Verilog-1995
◗ also called simply as procedural statements module HA (a, b, s, c) ;
◗ also known as sequential statements input a, b;
output s, c ;
◗ statements executed sequentially in order in
which they appear in code
assign s = a ^ b ;
◗ must be contained in always block
assign c = a & b ;
endmodule
Dataflow Modelling – cont.
▪ FA description using continuous assignment statements
1 module fulladder (Cin, x, y, S, Cout) ;
Continuous
input Cin, x, y;
assignment 2
statements 3 output S, Cout ;
4
5 assign S = ( x ^ y ^ Cin ) ;
6 assign Cout = (x & y) | (Cin & x) | (Cin & y);
7 endmodule
Notes on Concurrent/ Continuous signal
assignment statements
▪ In Verilog, concurrent assignment statements are called continuous assignment
statements.
▪ They are executed concurrently, and the line order is not important.
▪ Differing from concurrent statements, sequential statements are evaluated in the
order in which they appear in the code.
▪ Verilog syntax require them to be in an always block.
Structural Modelling
cin
FA
HA HA
module FA (cin, a, b, sum, cout) ;
a. sum
s1 input cin, a, b;
a a sum
u1 u2 sum output sum, cout ;
b b. cout s2 b cout
s3 wire s1, s2, s3;
HA u1 (a, b, s1, s2);
HA u2 (s1, cin, sum, s3);
cout or (cout, s2, s3);
endmodule
▪ HA modules are connected using positional port connection.
▪ Here, positional port connection applied, where each signal in the
instantiation statement is mapped by position to the corresponding
signal in the module.
Structural Modelling
cin
FA
HA HA
module FA (cin, a, b, sum, cout) ;
a. sum
s1 input cin, a, b;
a a sum
u1 u2 sum output sum, cout ;
b b. cout s2 b cout
s3 wire s1, s2, s3;
Instantiate Instance
d module name
HA u1 (a, b, s1, s2);
HA u2 (s1, cin, sum, s3);
cout or (cout, s2, s3);
endmodule
▪ In Verilog structural modelling, module instantiation is used.
▪ The instantiation statement associates the signals in the instantiated
module (HA, in this case) with the ports of the design unit (FA in this
case).
Structural Modelling
▪ Alternatively, we may use named port connection
◗ This explicit declaration style is preferable!
• Specify which signal is to be connected to which port using the .port name expression
module FA (cin, a, b, sum, cout) ;
input cin, a, b;
output sum, cout ;
wire s1, s2, s3;
Port a of HA Port A of FA
subcircuit circuit
HA u1 ( .a(a), .s(s1), .b(b), .c(s2) );
HA u2 ( .s(Sum), .c(s3), .a(s1), .b(Cin) );
assign cout = s2 | s3;
endmodule
1 module RCA4 (Cin, x, y, Cout, Sum) ;
2 input Cin; input [3:0] x, y;
3 output [3:0] Sum; output Cout ;
4 wire c1, c2, c3;
5
6 FA u0(.Cin(Cin), .A(x[0]), .B(y[0]), .Sum(Sum[0]), Cout(c1));
7 FA u1(.Cin(C1), .A(x[1]), .B(y[1]), .Sum(Sum[1]), Cout(c2));
8 FA u2(.Cin(C2), .A(x[2]), .B(y[2]), .Sum(Sum[2]), Cout(c3));
9 FA u3(.Cin(C3), .A(x[3]), .B(y[3]), .Sum(Sum[3]), Cout(Cout));
10 endmodule
Behavioural Modelling
▪ At higher levels of design abstraction, function or operation of
module is described in algorithmic manner.
▪ Behavioural modelling in Verilog uses constructs similar to C.
▪ HDL code accommodates statements that are executed
sequentially:
◗ order of procedural statements is important
◗ may affect semantics of code
▪ Procedural statements be contained inside a construct called an
always block. It is written as always @ (sensitivity list).
▪ Always block is the main construct.
◗ Can contain a single statement or more statements.
◗ If more than one statement, they must be bracketed by begin and end
keywords.
Behavioural Modelling – cont.
◼ Procedural statements in always block execute
sequentially
@ symbol – event control operator
after @ operator
o event control expression
o also called sensitivity list
◼ always block is sensitive to input variables in sensitivity
list
when event occurs on any variable, block is evaluated
RHS expression assigned to output variable on LHS
output variable holds its value until next event
26
Behavioural Modelling – cont.
◼ Any signal assigned value inside always block must be
reg variable
z must be reg
◼ Since z depends on A and B, they are included in
sensitivity list.
◼ Two statements using blocking assignments (denoted
by “=” symbol), are used
assignment completes and updates its LHS before next statement is
evaluated
the other kind is the non-blocking assignment, denoted by <= symbol
Behavioural Modelling of Comparator
# Verilog-1995 Verilog2001
module comp_2bit (LT, GT, EQ, A, B) ; • always @ (A, B)
output LT, GT, EQ; • always @ (*)
input [1:0] A, B; for combinational
reg LT, GT, EQ; logic
always @ (A or B)
begin
LT = 0; GT = 0; EQ = 0;
if (A == B)
EQ = 1;
else if (A > B)
GT = 1;
else
LT = 1;
end
endmodule
Behavioural Modelling of Multiplexer
# Verilog-1995
module mux2to1 (a, b, s, y) ;
output y;
input a, b, s;
reg y;
always @ (a or b or s)
if (s == 1)
y = a;
else
y = b;
endmodule
Behavioural Modelling – cont.
▪ Verilog syntax requires any signal assigned a value inside an
always block has to be a variable of type reg ; hence z is declared
as reg.
▪ Since z depends on A and B, these signals are included in the
sensitivity list.
▪ Blocking assignments, denoted by “=” symbol is used.
▪ The assignment completes and updates its LHS before the next
statement is evaluated.
▪ We will cover non-blocking assignment, denoted by <= symbol
later on.
Verilog-2001 Enhancements
Verilog-2001 Enhancements – cont.
Verilog-2001 Enhancements – cont.
❻
❶
❸ ❷
❹
❼
❺
Testbench Device-under-test tb dut interaction
module tb; stimuli
module HA (a, b, s, c) ;
reg a, b; // stimuli
tb
input a, b;
wire c, s; // output
output s, c ;
dut
HA dut (a, b, s, c); outputs
xor(s, a, b);
initial begin and(c, a, b);
endmodule A B C S
$dumpvars(1);
a = 0; 0 0 0 0
b = 0; 0 1 0 1
Half-adder
#50
b = 1; 1 0 0 1
Truth table
#50
1 1 1 0
a = 1;
b = 0;
#50
b = 1;
#50 $finish;
end
endmodule
https://www.edaplayground.com/x/ZdFa
Same Testbench Different implementations
module tb;
reg a, b; // stimuli // gate-level // dataflow 1
wire c, s; // output module HA (a, b, s, c); module HA (a, b, s, c);
input a, b; input a, b;
Test-Driven HA dut (a, b, s, c); output s, c ; output s, c ;
Design initial begin xor(s, a, b); assign s = a ^ b ;
$dumpvars(1); and(c, a, b); assign c = a & b;
a = 0; endmodule endmodule
Write the b = 0;
testbench first #50
b = 1;
#50 // dataflow 2 // behavioral 2
a = 1; module HA (a, b, s, c); module HA (a, b, s, c);
b = 0; input a, b; input a, b;
#50 output s, c ; output reg s, c ;
b = 1;
#50 $finish; assign {c,s} = a + b; always @ *
end endmodule {c,s} = a + b;
endmodule
endmodule
Exercise
module tb;
reg a, b, s; // stimuli
▪ Write code for 2-to-1 MUX using
wire f; // output each modelling style
◗ Structural: 4 gates
mux21 dut (a, b, s, f);
◗ Dataflow: Boolean
initial begin
◗ Behavioural: if-then-else
$dumpvars(1);
a = 0; b = 0; s = 0;
#80 $finish;
end a
b
always #10 a = ~a;
s
always #20 b = ~b;
always #40 s = ~s; tb dut
endmodule f
