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Dpco Unit 1

This document is a multiple-choice question test for the third semester of the B.E./B.Tech. program in Artificial Intelligence and Data Science at Christ the King Engineering College. It covers topics related to digital principles and computer organization, with a total of 10 questions, each carrying 1 mark. The test is regulated under the 2021 curriculum and includes questions on logic gates, K-maps, and combinational circuits.

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Uma Devi C
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108 views5 pages

Dpco Unit 1

This document is a multiple-choice question test for the third semester of the B.E./B.Tech. program in Artificial Intelligence and Data Science at Christ the King Engineering College. It covers topics related to digital principles and computer organization, with a total of 10 questions, each carrying 1 mark. The test is regulated under the 2021 curriculum and includes questions on logic gates, K-maps, and combinational circuits.

Uploaded by

Uma Devi C
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CHRIST THE KING ENGINEERING COLLEGE

Affiliated to Anna University, Chennai and Approved by AICTE, New Delhi


Karamadai, Coimbatore – 641104

B.E./B.Tech. – ARTIFICIAL INTELLIGENCE AND DATA SCIENCE


THIRD SEMESTER
CS3351 - DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
MCQ TEST – 1
(REGULATION 2021)

Answer All the Questions Date:


Each Question Carries 1 Marks of Total 10 Marks

Name of the Marks Awarded


:
Student
:
Reg. No.
:
Year Signature of the
:
Semester Faculty

1. Which of the following combinations of logic gates can decode binary 1101?

a.
b. One 4-input AND c. One 4-input AND d. One 4-input NAND
gate, one inverter gate, one OR gate gate, one inverter

EX-OR
gate
and
NOR
gate
b.
EX-OR
gate
and
OR
gate
c.
EX-OR
gate
and
AND
gate
d.
EX-
NOR
gate
and
AND
gate
a.
EX-OR
gate
and
NOR
gate
b.
EX-OR
gate
and
OR
gate
c.
EX-OR
gate
and
AND
gate
d.
EX-
NOR
gate
and
AND
gate
a. One 4-input AND
gate
For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is
LOW. What is the status of the Y’ outputs?

2.

c. All but Y0 are d. All but Y0 are


a. All are HIGH b. All are LOW
LOW HIGH
3. 3 bits full adder contains ________
c. 6 d. 8
a. 3 combinational b. 4 combinational
combinational combinational
inputs inputs
inputs inputs
4. The carry propagation can be expressed as ________
c. All but Y0 are d. All but Y0 are
a. Cp = AB b. Cp = A + B
LOW HIGH
A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a matrix of
5.
squares.
a. Venn d. Triangular
b. Cycle Diagram c. Block diagram
Diagramb. Diagram
6. There are ______ cells in a 4-variable K-map.
a. 12 b. 16 c. 18 d. 8
Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible
7.
product term of the given ___________
a. Function b. Value c. Set d. Word
8. Using the transformation method you can realize any POS realization of OR-AND with only.
a. XOR b. NAND c. AND d. NOR
9. Entries known as _______________ mapping.
a. Diagonal b. Straight c. K d. Boolean
These logic gates are widely used in _______________ design and therefore are available in IC
10.
form.
a. Sampling b. Digital c. Analog d. Systems
Prepared By Verified by Approved by
Mrs. S. V. Kiruthika HoD/ ECE Principal
AP/ECE

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