TPS56C215

SLVSD05H – MARCH 2016 – REVISED JUNE 2025

TPS56C215 3.8V to 17V Input, 12A, Synchronous, Step-Down SWIFT™ Converter

1 Features 2 Applications
• Integrated 7.8mΩ and 3.2mΩ MOSFETs • Server, cloud-computing, storage
• Supports 12A continuous IOUT • Telecom and networking, point-of-load (POL)
• 4.5V start-up without external 5.0V bias • IPCs, factory automation, PLC, test measurement
• 0.6V ±-1% reference voltage across full • High-end DTV
temperature range
• 0.6V to 5.5V output voltage range 3 Description
• Supports ceramic output capacitors The TPS56C215 is a small monolithic 12A
• D-CAP3™ control mode for fast transient response synchronous buck converter with an adaptive on-
• Selectable forced continuous conduction mode time D-CAP3 control mode. The device integrates
(FCCM) for tight output voltage ripple or auto- low RDS(on) power MOSFETs that enable high
skipping Eco-mode for high light-load efficiency efficiency and offers ease-of-use with minimum
• Selectable FSW of 400kHz, 800kHz, and 1.2MHz external component count for space-conscious
• Monotonic start-up into prebiased outputs power systems. Competitive features include a
• Two adjustable current limit settings with hiccup very accurate reference voltage, fast load transient
re-start response, auto-skip mode operation for light load
• Optional external 5V bias for enhanced efficiency efficiency, adjustable current limit and no requirement
• Adjustable soft start with a default 1ms soft-start for external compensation. A forced continuous
time conduction mode helps meet tight voltage regulation
• –40°C to 150°C operating junction temperature accuracy requirements for performance DSPs and
• Small 3.5mm × 3.5mm HotRod™ QFN package FPGAs. The TPS56C215 is available in a thermally
• Pin-to-pin compatible with 8A TPS568215 enhanced, 18-pin, HotRod QFN package and is
• Create a custom design using TPS56C215 with designed to operate from –40°C to 150°C junction
the WEBENCH® Power Designer temperature.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS56C215 RNN (VQFN-HR, 18) 3.5mm × 3.5mm

(1) For more information, see Section 10.

(2) The package size (length × width) is a nominal value and
includes pins, where applicable.

100
VREG5 95
RM_H
VIN MODE
VREG5
90
VIN
RM_L
CIN PGOOD
85
PGOOD TPS56C215 BOOT
Efficiency (%)

LOUT
80
SW VOUT
EN
COUT 75
RUPPER
SS
FB 70
CSS
AGND PGND RLOWER 65
60 VIN=12V, V OUT=1.2V, 400kHz
Typical Application 55 VIN=12V, V OUT=3.3V, 400kHz
VIN=12V, V OUT=5V, 400kHz
50
0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A)
Efficiency vs Output Current

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................. 21
2 Applications..................................................................... 1 7.1 Application Information............................................. 21
3 Description.......................................................................1 7.2 Typical Application.................................................... 21
4 Pin Configuration and Functions...................................3 7.3 Power Supply Recommendations.............................25
5 Specifications.................................................................. 4 7.4 Layout....................................................................... 25
5.1 Absolute Maximum Ratings........................................ 4 8 Device and Documentation Support............................29
5.2 ESD Ratings............................................................... 4 8.1 Device Support......................................................... 29
5.3 Recommended Operating Conditions.........................4 8.2 Receiving Notification of Documentation Updates....30
5.4 Thermal Information....................................................5 8.3 Support Resources................................................... 30
5.5 Electrical Characteristics.............................................5 8.4 Trademarks............................................................... 30
5.6 Timing Requirements.................................................. 6 8.5 Electrostatic Discharge Caution................................30
5.7 Typical Characteristics................................................ 7 8.6 Glossary....................................................................30
6 Detailed Description......................................................13 9 Revision History............................................................ 31
6.1 Overview................................................................... 13 10 Mechanical, Packaging, and Orderable
6.2 Functional Block Diagram......................................... 14 Information.................................................................... 32
6.3 Feature Description...................................................14 10.1 Package Marking.................................................... 32
6.4 Device Functional Modes..........................................20

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4 Pin Configuration and Functions

BOTTOM VIEW TOP VIEW

16 PGOOD

16 PGOOD
17 VREG5

17 VREG5
18 MODE

18 MODE
14 SS

14 SS
15 EN

15 EN
13 FB

13 FB
AGND 12 1 BOOT BOOT 1 12 AGND

VIN 11 2 VIN VIN 2 11 VIN

PGND 10 3 PGND PGND 3 10 PGND

PGND 9 4 PGND PGND 4 9 PGND

PGND 8 5 PGND PGND 5 8 PGND

7 6 6 7
SW SW

Figure 4-1. RNN Package, 18-Pin VQFN

Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor
BOOT 1 I
between BOOT and SW.
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between
VIN 2,11 P
VIN and PGND.
3, 4, 5, Power GND terminal for the controller circuit and the internal circuitry. Connect to AGND with a short
PGND G
8, 9, 10 trace.
SW 6, 7 O Switch node terminal. Connect the output inductor to this pin.
AGND 12 G Ground of internal analog circuitry. Connect AGND to PGND plane with a short trace.
Converter feedback input. Connect to the center tap of the resistor divider between output voltage
FB 13 I
and AGND.
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no
SS 14 O
external capacitor is connected, the converter starts up in 1 ms.
Enable input control, leaving this pin floating enables the converter. This pin can also be used to
EN 15 I
adjust the input UVLO by connecting to the center tap of the resistor divider between VIN and EN.
Open-drain power good indicator, this pin asserted low if output voltage is out of PGOOD threshold,
PGOOD 16 O
overvoltage, or if the device is under thermal shutdown, EN shutdown or during soft start.
4.7-V internal LDO output which can also be driven externally with a 5-V input. This pin supplies
VREG5 17 I/O
voltage to the internal circuitry and gate driver. Bypass this pin with a 4.7-µF capacitor.
Switching frequency, current limit selection and light load operation mode selection pin. Connect this
MODE 18 I
pin to a resistor divider from VREG5 and AGND for different MODE options shown in Table 6-3.

(1) I = input, P = power, G = ground, O = output

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 20
SW –2 19
SW (10-ns transient) –5 25
VIN-SW 22

VIN-SW (10-ns transient) 25

Input voltage EN –0.3 6.5 V
BOOT –SW –0.3 6.5
BOOT –SW (10 ns transient) –0.3 7.5
BOOT –0.3 25.5
SS, MODE, FB –0.3 6.5
VREG5 –0.3 6
Output voltage PGOOD –0.3 6.5 V
Output current(2) IOUT 14 A
Operating
junction TJ –40 150 °C
temperature
Storage
Tstg –55 150 °C
temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) to be consistent with the TI reliability requirement of 100k Power-On-Hours at 105°C junction temperature, the output current must not
exceed 14A continuously under 100% duty operation as to prevent electromigration failure in the solder. Higher junction temperature or
longer power-on hours are achievable at lower than 14A continuous output current.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±500
C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN 3.8 17 V
SW –1.8 17 V
Input voltage
BOOT –0.1 23.5 V
VREG5 –0.1 5.2 V
Output current ILOAD 0 12 A
Operating junction
TJ -40 150 °C
temperature

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5.4 Thermal Information

RNN (VQFN-HR)
THERMAL METRIC(1) UNIT
18 PINS
RθJA Junction-to-ambient thermal resistance 29.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.0 °C/W
RθJB Junction-to-board thermal resistance 8.6 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 8.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

5.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 12V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IIN VIN supply current TJ = 25°C, VEN = 5 V, non switching 146 µA

IVINSDN VIN shutdown current TJ = 25°C, VEN = 0 V 9.3 µA

LOGIC THRESHOLD
VENH EN H-level threshold voltage 1.175 1.225 1.3 V
VENL EN L-level threshold voltage 1.025 1.104 1.15 V
VENHYS 0.121 V
IENp1 VEN = 1.0 V 0.35 1.91 2.95 µA
EN pullup current
IENp2 VEN = 1.3 V 3 4.197 5.5 µA
FEEDBACK VOLTAGE
TJ = 25°C 598 600 602 mV
VFB FB voltage TJ = 0°C to 85°C 597.5 600 602.5 mV
TJ = –40°C to 85°C 594 600 602.5 mV
TJ = –40°C to 150°C 594 600 606 mV
LDO VOLTAGE
VREG5 LDO output voltage TJ = –40°C to 150°C 4.58 4.7 4.83 V
ILIM5 LDO output current limit TJ = –40°C to 150°C 100 150 200 mA
MOSFET
RDS(on)H High side switch resistance TJ = 25°C, VVREG5 = 4.7 V 7.8 mΩ
RDS(on)L Low side switch resistance TJ = 25°C, VVREG5 = 4.7 V 3.2 mΩ
SOFT START
Iss Soft-start charge current TJ = –40°C to 150°C 4.9 6 7.1 µA
CURRENT LIMIT
ILIM-1 option, valley current 9.775 11.5 13.225 A
IOCL Current Limit (Low side sourcing)
ILIM option, valley current 11.73 13.8 15.87 A
Current limit (low side negative) Valley current 4 A
POWER GOOD
VFB falling (fault) 84%
VFB rising (good) 93%
VPGOODTH PGOOD threshold
VFB rising (fault) 116%
VFB falling (good) 108%

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5.5 Electrical Characteristics (continued)

TJ = –40°C to 150°C, VIN = 12V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
121% ×
VOVP Output OVP threshold OVP detect
VFB
70% ×
VUVP Output UVP threshold Hiccup detect
VFB
THERMAL SHUTDOWN
Shutdown temperature 160 °C
TSDN Thermal shutdown threshold
Hysteresis 15 °C
UVLO
VREG5 rising voltage 4.25 V
UVLO UVLO threshold VREG5 falling voltage 3.52 V
VREG5 hysteresis 730 mV
VIN rising voltage, VREG5 = 4.7V 3.32 V
UVLO,
VREG5 = UVLO threshold, VREG5 = 4.7V VIN falling voltage, VREG5 = 4.7V 3.24 V
4.7V
VIN hysteresis, VREG5 = 4.7V 80 mV

5.6 Timing Requirements

PARAMETER CONDITIONS MIN TYP MAX UNIT
ON-TIME TIMER CONTROL
tON SW on time(1) VIN = 12 V, VOUT = 3.3 V, FSW = 800 kHz 310 340 380 ns
tON min SW Minimum on time VIN = 17 V, VOUT = 0.6 V, FSW= 1200 kHz 60 ns
tOFF SW Minimum off time 25°C, VFB = 0.5 V 310 ns
SOFT START
tSS Soft-start time Internal soft-start time 1.2 ms
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tUVPDEL Output hiccup delay relative to SS time UVP detect 1 cycle
Output hiccup enable delay relative to SS
tUVPEN UVP detect 14 cycle
time

(1) Specified by design

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5.7 Typical Characteristics

1000 20
Non-Switching Operating Quiscent Current - µA

900 18
16

Shutdown Current(µA)
800
14
700 12
600 10

500 8
6
400
4
300 2 VIN =12V
VIN =12V
200 0
-50 0 50 100 150 ±50 0 50 100 150
TJ - Junction Temperature(ƒC) C002 TJ - Junction Temperature(ƒC) C003

Figure 5-1. Quiescent Current vs Temperature Figure 5-2. Shutdown Current vs Temperature
0.606 8

Soft-Start Charge Current(µA)

0.604
VFB - Feedback Voltage(V)

7
0.602

0.6 6

0.598
5
0.596
VIN =12V
VIN =12V
0.594 4
-50 0 50 100 150 ±50 0 50 100 150
TJ - Junction Temperature(ƒC) C004 TJ - Junction Temperature(ƒC) C008

Figure 5-3. Feedback Voltage vs Temperature Figure 5-4. Soft-Start Charge Current vs Temperature
3 6
Enable Pin Pull-Up Current(µA)
Enable Pin Pull-Up Current(uA)

5.5
2.5
5

2 4.5

4
1.5
3.5

VIN =12V VIN =12V

1 3
±50 0 50 100 150 ±50 0 50 100 150
TJ - Junction Temperature(ƒC) C009 TJ - Junction Temperature(ƒC) C010

Figure 5-5. Enable Pullup Current, VEN = 1.0 V Figure 5-6. Enable Pullup Current, VEN = 1.3 V

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5.7 Typical Characteristics (continued)

120 18
ILIM option

Low Side Valley Current Limit(A)

115 17
ILIM-1 option
PGOOD Threshold(%)

110 16

105 15
VFB rising
100 VFB falling 14
VFB rising
95 VFB falling 13

90 12

85 11

80 10
1 2 3 4 5 6 7 8 9 10 ±50 0 50 100 150
TJ - Junction Temperature(ƒC) C011 TJ - Junction Temperature(ƒC) C012

Figure 5-7. PGOOD Threshold vs Temperature Figure 5-8. Current Limit vs Temperature
100 100

90 95
90
80
85
Efficiency (%)

70 Efficiency (%) 80
60 75

50 70
65
40
60
30 VIN=5V, V OUT=1.2V, 400kHz 55 VIN=5V, V OUT=1.2V, 400kHz
VIN=12V, V OUT=1.2V, 400kHz VIN=12V, V OUT=1.2V, 400kHz
20 50
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-9. Efficiency, DCM Mode, fSW = 400 kHz Figure 5-10. Efficiency, FCCM Mode, fSW = 400 kHz
100 100

90 95
90
80
85
Efficiency (%)

Efficiency (%)

70 80
60 75

50 70
65
40
60
30 VIN=5V, V OUT=1.2V, 800kHz 55 VIN=5V, V OUT=1.2V, 800kHz
VIN=12V, V OUT=1.2V, 800kHz VIN=12V, V OUT=1.2V, 800kHz
20 50
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-11. Efficiency, DCM Mode, fSW = 800 kHz Figure 5-12. Efficiency, FCCM Mode, fSW = 800 kHz

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5.7 Typical Characteristics (continued)

100 100

90 95
90
80
85
Efficiency (%)

Efficiency (%)
70 80
60 75

50 70
65
40
60
30 VIN=5V, V OUT=1.2V, 1200kHz 55 VIN=5V, V OUT=1.2V, 1200kHz
VIN=12V, V OUT=1.2V, 1200kHz VIN=12V, V OUT=1.2V, 1200kHz
20 50
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-13. Efficiency, DCM Mode, fSW = 1200 kHz Figure 5-14. Efficiency, FCCM Mode, fSW = 1200 kHz
100 100

90 95
90
80
85
Efficiency (%)

Efficiency (%)
70 80
60 75

50 70
65
40
VIN=12V, V OUT=1.2V, 400kHz 60 VIN=12V, V OUT=1.2V, 400kHz
30 VIN=12V, V OUT=3.3V, 400kHz 55 VIN=12V, V OUT=3.3V, 400kHz
VIN=12V, V OUT=5V, 400kHz VIN=12V, V OUT=5V, 400kHz
20 50
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-15. Efficiency, DCM Mode, fSW = 400 kHz Figure 5-16. Efficiency, FCCM Mode, fSW = 400 kHz
100 100

90 95
90
80
85
Efficiency (%)

Efficiency (%)

70 80
60 75

50 70
65
40
VIN=12V, V OUT=1.2V, 800kHz 60 VIN=12V, V OUT=1.2V, 800kHz
30 VIN=12V, V OUT=3.3V, 800kHz 55 VIN=12V, V OUT=3.3V, 800kHz
VIN=12V, V OUT=5V, 800kHz VIN=12V, V OUT=5V, 800kHz
20 50
0.001 0.01 0.05 0.2 0.5 1 2 3 45 7 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-17. Efficiency, DCM Mode, fSW = 800 kHz Figure 5-18. Efficiency, FCCM Mode, fSW = 800 kHz

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5.7 Typical Characteristics (continued)

100 100

90 95
90
80
85
Efficiency (%)

Efficiency (%)
70 80
60 75

50 70
65
40
VIN=12V, V OUT=1.2V, 1200kHz 60 VIN=12V, V OUT=1.2V, 1200kHz
30 VIN=12V, V OUT=3.3V, 1200kHz 55 VIN=12V, V OUT=3.3V, 1200kHz
VIN=12V, V OUT=5V, 1200kHz VIN=12V, V OUT=5V, 1200kHz
20 50
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-19. Efficiency, DCM Mode, fSW = 1200 kHz Figure 5-20. Efficiency, FCCM Mode, fSW = 1200 kHz
100 1.208

90
1.206
80
Output Voltage (V)
70 1.204
Efficiency (%)

60
1.202
50

40 1.2

30 Ext-5VCC, VIN=5V, V OUT=1.2V, 800kHz

Ext-5VCC, VIN=12V, V OUT=1.2V, 800kHz 1.198
20 Internal 5VCC, VIN=5V, V OUT=1.2V, 800kHz VIN=5V, V OUT=1.2V
Internal 5VCC, VIN=12V, V OUT=1.2V, 800kHz VIN=12V, V OUT=1.2V
10 1.196
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-21. Efficiency, Ext-VCC vs Internal-VCC, DCM Mode, Figure 5-22. Load Regulation, FSW = 800 kHz
fSW = 800 kHz
450 900
VIN=5V, V OUT=1.2V VIN=5V, V OUT=1.2V
400 VIN=12V, V OUT=1.2V 800 VIN=12V, V OUT=1.2V
350 700
Frequency (kHz)

Frequency (kHz)

300 600

250 500

200 400

150 300

100 200

50 100

0 0
0.001 0.01 0.1 1 10 20 0.001 0.01 0.1 1 10 20
Output Current (A) Output Current (A)
Figure 5-23. FSW Load Regulation, Mode = DCM, FSW = 400 kHz Figure 5-24. FSW Load Regulation, Mode = DCM, FSW = 800 kHz

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5.7 Typical Characteristics (continued)

1200 600
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
1000 550
Frequency (kHz)

Frequency (kHz)
800 500

600 450

400 400

200 350
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
0 300
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-25. FSW Load Regulation, Mode = DCM, FSW = 1200 kHz Figure 5-26. FSW Load Regulation, Mode =FCCM, FSW = 400 kHz
900 1200

850 1150
1100
800
1050
Frequency (kHz)

Frequency (kHz)
750 1000
700 950

650 900
850
600
800
550 VIN=5V, V OUT=1.2V 750 VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V VIN=12V, V OUT=1.2V
500 700
0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-27. FSW Load Regulation, Mode = FCCM, FSW = 800 kHz Figure 5-28. FSW Load Regulation, Mode = FCCM, FSW = 1200
kHz
600 900

550 850

500 800
Frequency (kHz)

Frequency (kHz)

450 750

400 700

350 650

300 600
VIN=12V, V OUT=1.2V VIN=12V, V OUT=1.2V
250 VIN=12V, V OUT=3.3V 550 VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V VIN=12V, V OUT=5V
200 500
0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)
Figure 5-29. FSW Load Regulation, Mode = FCCM, FSW = 400 kHz Figure 5-30. FSW Load Regulation, Mode = FCCM, FSW = 800 kHz

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5.7 Typical Characteristics (continued)

1300 500
VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V
1200 VIN=12V, V OUT=5V
400
Frequency (kHz)

Frequency (kHz)
1100
300
1000
200
900

VIN=12V, V OUT=1.2V 100

800
VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V
700 0
0 1 2 3 4 5 6 7 8 9 10 11 12 0.001 0.01 0.1 1 10 20
Output Current (A) Output Current (A)
Figure 5-31. FSW Load Regulation, Mode = FCCM, FSW = 1200 Figure 5-32. FSW Load Regulation, Mode = DCM, FSW = 400 kHz
kHz
1000 1400
VIN=12V, V OUT=1.2V VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V VIN=12V, V OUT=3.3V
1200
800 VIN=12V, V OUT=5V VIN=12V, V OUT=5V

1000
Frequency (kHz)

Frequency (kHz)

600
800

600
400

400
200
200

0 0
0.001 0.01 0.1 1 10 20 0.001 0.01 0.1 1 10 20
Output Current (A) Output Current (A)
Figure 5-33. FSW Load Regulation, Mode = DCM, FSW = 800 kHz Figure 5-34. FSW Load Regulation, Mode = DCM, FSW = 1200 kHz

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6 Detailed Description
6.1 Overview
The TPS56C215 is a high-density, synchronous, step-down buck converter which can operate from 3.8-V to
17-V input voltage (VIN). The device has 7.8-mΩ and 3.2-mΩ integrated MOSFETs that enable high efficiency
up to 12 A. The device employs D-CAP3 control mode that provides fast transient response with no external
compensation components and an accurate feedback voltage. The control topology provides seamless transition
between FCCM operating mode at higher load condition and DCM/Eco-mode operation at lighter load condition.
DCM/Eco-mode allows the TPS56C215 to maintain high efficiency at light load. The TPS56C215 is able to adapt
to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low
ESR ceramic capacitors.
The TPS56C215 has three selectable switching frequencies (FSW) (400 kHz, 800 kHz, and 1200 kHz), which
gives the flexibility to optimize the design for higher efficiency or smaller size. There are two selectable current
limits. All these options are configured by choosing the right voltage on the MODE pin.
The TPS56C215 has a 4.7-V internal LDO that creates bias for all internal circuitry. There is a feature to
overdrive this internal LDO with an external voltage on the VREG5 pin which improves the efficiency of the
converter. The undervoltage lockout (UVLO) circuit monitors the VREG5 pin voltage to protect the internal
circuitry from low input voltages. The device has an internal pullup current source on the EN pin which can
enable the device even with the pin floating.
Soft-start time can be selected by connecting a capacitor to the SS pin. The device is protected from output
short, undervoltage, and overtemperature conditions.

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6.2 Functional Block Diagram

PG rising threshold
TPS56C215
+
PGOOD

PGOOD Logic
UV UV
threshold +
+
Delay
VREG5
UVP / OVP Logic
+ PG falling threshold
OV threshold
OV LDO
VIN

UVLO
Internal Ramp
+

BOOT
t BOOT
VREF t
+
Error Amp
+ Control Logic
+

FB t
x On Time SW SW
x Min On Time/Off Time
x FCCM/SKIP XCON
Internal SS x Soft-Start
One shot x Power Good
x Internal/External VREG5 VREG5
SS x UVP/TSD

PGND

MODE Light Load Operation/

Current Limit/Switching TSD 160C/171C
Frequency
SW

OCL
Ip1 Ip2 +

EN +

ZC
Enable Threshold +

NOCL
+

6.3 Feature Description

6.3.1 PWM Operation and D-CAP3™ Control Mode
The TPS56C215 operates using the adaptive on-time PWM control with a proprietary D-CAP3 control mode
which enables low external component count with a fast load transient response while maintaining a good output
voltage accuracy. At the beginning of each switching cycle, the high-side MOSFET is turned on for an on-time
set by an internal one shot timer. This on-time is set based on the input voltage of the converter, output voltage
of the converter, and the pseudo-fixed frequency, hence this type of control topology is called an adaptive
on-time control. The one-shot timer resets and turns on again after the feedback voltage (VFB) falls below the
internal reference voltage (VREF). An internal ramp is generated which is fed to the FB pin to simulate the output
voltage ripple. This enables the use of very low-ESR output capacitors such as multi-layered ceramic caps
(MLCC). No external current sense network or loop compensation is required for DCAP3 control topology.

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The TPS56C215 includes an error amplifier that makes the output voltage very accurate. This error amplifier is
absent in other flavors of D-CAP3. For any control topology that is compensated internally, there is a range of
the output filter the control topology can support. The output filter used with the TPS56C215 is a low-pass L-C
circuit. This L-C filter has double pole that is described in Equation 1.

1
¦P =
2 ´ p ´ LOUT ´ COUT (1)

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS56C215. The low frequency L-C double pole has a 180 degree in-phase. At the output filter
frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40-dB to –20-dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high frequency zero is changed according to the switching frequency selected as shown in Table 6-1. The
inductor and capacitor selected for the output filter must be such that the double pole is located close enough to
the high-frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase
margin for the stability requirement. The crossover frequency of the overall system must usually be targeted to
be less than one-fifth of the switching frequency (FSW).
Table 6-1. Ripple Injection Zero
SWITCHING FREQUENCY (kHz) ZERO LOCATION (kHz)
400 17.8
800 27.1
1200 29.8

Table 6-2 lists the inductor values and part numbers that are used to plot the efficiency curves in Section 5.7.
Table 6-2. Inductor Values
WÜRTH PART
VOUT(V) FSW(kHz) LOUT(μH)
NUMBER(1)
400 1.2 744325120
1.2 800 0.68 744311068
1200 0.47 744314047
400 2.4 744325240
3.3 800 1.5 7443552150
1200 1.2 744325120
400 3.3 744325330
5.5 800 2.4 744325240
1200 1.5 7443552150

(1) See Third-Party Products disclaimer.

6.3.2 Eco-mode Control

The TPS56C215 is designed with Eco-mode control to increase efficiency at light loads. This option can be
chosen using the MODE pin as shown in Table 6-3. As the output current decreases from heavy load condition,
the inductor current is also reduced. If the output current is reduced enough, the valley of the inductor current
reaches the zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The low-side MOSFET is turned off when a zero inductor current is detected. As the load current further
decreases the converter runs into discontinuous conduction mode. The on-time is kept approximately the same
as in continuous conduction mode. The off-time increases as discharging the output with a smaller load current
takes more time. The light load current where the transition to Eco-mode operation happens (IOUT(LL)) can be
calculated from Equation 2.

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1 (V -V ) × VOUT
IOUT(LL) = × IN OUT
2 × LOUT × FSW VIN (2)

After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(ma×) (peak current in the application).
Sizing the inductor properly so that the valley current does not hit the negative low-side current limit is important.
6.3.3 4.7-V LDO
The VREG5 pin is the output of the internal 4.7-V linear regulator that creates the bias for all the internal circuitry
and MOSFET gate drivers. The VREG5 pin needs to be bypassed with a 4.7-µF capacitor. An external voltage
that is above the internal output voltage of the LDO can override the internal LDO, switching the internal LDO
to the external rail after a higher voltage is detected. This enhances the efficiency of the converter because the
quiescent current now runs off this external rail instead of the input power supply. The UVLO circuit monitors
the VREG5 pin voltage and disables the output when VREG5 falls below the UVLO threshold. When using an
external bias on the VREG5 rail, any power-up and power-down sequencing can be applied but understanding
that if there is a discharge path on the VREG5 rail that can pull a current higher than the internal current
limit of the LDO (ILIM5) from the VREG5, then the VREG5 LDO turns off thereby shutting down the output of
TPS56C215 is important. If such condition does not exist and if the external VREG5 rail is turned off, the VREG5
voltage switches over to the internal LDO voltage which is 4.7 V typically in a few nanoseconds. Figure 6-1
shows this transition of the VREG5 voltage from an external bias of 5.5 V to the internal LDO output of 4.7 V
when the external bias to VREG5 is disabled while the output of TPS56C215 remains unchanged.

VREG5

VOUT

Figure 6-1. VREG5 Transition

6.3.4 MODE Selection

The TPS56C215 has a MODE pin that can offer 12 different states of operation as a combination of current
limit, switching frequency, and light load operation. The device can operate at two different current limits ILIM-1
and ILIM to support an output continuous current of 10 A and 12 A, respectively. The TPS56C215 is designed
to compare the valley current of the inductor against the current limit thresholds so understand that the output
current is half the ripple current higher than the valley current. For example, with the ILIM current limit selection,

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the OCL threshold is 11.73-A minimum, which means that a pk-pk inductor ripple current of 0.54-A minimum is
needed to be able to draw 12 A out of the converter without entering an overcurrent condition. The TPS56C215
can operate at three different frequencies of 400 kHz, 800 kHz, and 1200 kHz and also can choose between
Eco-mode and FCCM mode. The device reads the voltage on the MODE pin during start-up and latches onto
one of the MODE options listed in Table 6-3. The voltage on the MODE pin can be set by connecting this pin to
the center tap of a resistor divider connected between VREG5 and AGND. A guideline for the top resistor (RM_H)
and the bottom resistor (RM_L) in 1% resistors is shown in Table 6-3. Make sure that the voltage for the MODE
pin is derived from the VREG5 rail only because internally this voltage is referenced to detect the MODE option.
The MODE pin setting can be reset only by a VIN power cycling.
Table 6-3. MODE Pin Resistor Settings
LIGHT LOAD FREQUENCY
RM_L (kΩ) RM_H (kΩ) CURRENT LIMIT
OPERATION (kHz)
5.1 300 FCCM ILIM-1 400
10 200 FCCM ILIM 400
20 160 FCCM ILIM-1 800
20 120 FCCM ILIM 800
51 200 FCCM ILIM-1 1200
51 180 FCCM ILIM 1200
51 150 DCM ILIM-1 400
51 120 DCM ILIM 400
51 91 DCM ILIM-1 800
51 82 DCM ILIM 800
51 62 DCM ILIM-1 1200
51 51 DCM ILIM 1200

Figure 6-2 shows the typical start-up sequence of the device after the EN pin voltage crosses the EN turn-on
threshold. After the voltage on VREG5 pin crosses the rising UVLO threshold, reading the first MODE setting
takes 100 μs and approximately 100 μs from there to finish the last MODE setting. The output voltage starts
ramping after the MODE setting reading is completed.

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EN threshold
1.2 V
EN

VREG5 UVLO
4.3 V

VREG5
MODE16

MODE1
MODE

200 µs 100 µs tss(1ms)

SS

Figure 6-2. Power-Up Sequence

6.3.5 Soft Start and Prebiased Soft Start

The TPS56C215 has an adjustable soft start time that can be set by connecting a capacitor on SS pin. When the
EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in Equation 3:

CSS × VREF
TSS(S) =
ISS (3)

where
• VREF is 0.6 V and ISS is 6 µA
If the output capacitor is prebiased at start-up, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme makes sure that the
converters ramp up smoothly into regulation point.
6.3.6 Enable and Adjustable UVLO
The EN pin controls the turn-on and turnoff of the device. When EN pin voltage is above the turn-on threshold
which is around 1.2 V, the device starts switching, and when the EN pin voltage falls below the turn-off threshold,
which is around 1.1 V, the device stops switching. If the user application requires a different turn-on (VSTART) and
turnoff thresholds (VSTOP) respectively, the EN pin can be configured as shown in Figure 6-3 by connecting a
resistor divider between VIN and EN. The EN pin has a pullup current Ip1 that sets the default state of the pin
when floating. This current increases to Ip2 when the EN pin voltage crosses the turn-on threshold. The UVLO
thresholds can be set by using Equation 4 and Equation 5.

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TPS56C215

VIN Ip1 Ih
R1

R2 EN

Figure 6-3. Adjustable VIN Undervoltage Lockout

æV ö
VSTART ç ENFALLING ÷ - VSTOP
R1 = è VENRISING ø
æ V ö
Ip1 ç1 - ENFALLING ÷ + Ih
è VENRISING ø
(4)

R1´ VENFALLING
R2 =
VSTOP - VENFALLING + R1 Ip2 (5)

where
• Ip2 = 4.197 μA
• Ip1 = 1.91 μA
• Ih = 2.287 μA
• VENRISING = 1.225 V
• VENFALLING = 1.104 V
6.3.7 Power Good
The Power Good (PGOOD) pin is an open-drain output. After the FB pin voltage is between 93% and 107%
of the internal reference voltage (VREF), the PGOOD is deasserted and floats after a 200-µs deglitch time. TI
recommends a pullup resistor of 10 kΩ to pull up to VREG5. The PGOOD pin is pulled low when the FB pin
voltage is lower than VUVP or greater than VOVP threshold, in an event of thermal shutdown, or during the
soft-start period.
6.3.8 Overcurrent Protection and Undervoltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. During the on-time of the high-side FET switch, the switch current increases at
a linear rate determined by input voltage, output voltage, the on-time, and the output inductor value. During the
on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the
load current IOUT. If the measured drain-to-source voltage of the low-side FET is above the voltage proportional
to current limit, the low-side FET stays on until the current level becomes lower than the OCL level which
reduces the output current available. When the current is limited the output voltage tends to drop because the
load demand is higher than what the converter can support. When the output voltage falls below 68% of the
target voltage, the UVP comparator detects the fall and shuts down the device after a wait time of 1 × tSS. The
device re-starts after a hiccup time of 14 × tSS. In this type of valley detect control, the load current is higher
than the OCL threshold by one half of the peak-to-peak inductor ripple current. When the overcurrent condition is
removed, the output voltage returns to the regulated value. If an OCL condition happens during start-up, then the
device enters hiccup-mode immediately without a wait time of 1 soft-start cycle.

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6.3.9 Transient Response Enhancement

The PSM deglitch feature activates whenever the device transitions from a heavy load in Continuous Conduction
Mode (CCM) to a light load in Discontinuous Conduction Mode (DCM). During this transition, the system enters
Forced Continuous Conduction Mode (FCCM) for 16 cycles before switching to DCM. This feature is designed to
provide fast recovery in load transients during DCM operation.
Figure 6-4 shows 16-cycle and 32-cycle FCCM operation during load release and dynamic COMP pin
positioning. Figure 6-5 shows steady-state Auto-skip mode operation with the dynamic COMP pin clamp.

Start the 16-Cycle

Auto Skip Mode FCC Mode FB
Counter to AutoSkip
FB DC
1VREF

IPEAK(min)
CSP-CSN
ILOAD
COMP Ripple = 46 mV (max)
IL
CSP–CSN
VCOMP COMP 1.949 V
VREF
COMP CLAMP

Time UDG-12132

V_IPEAK(min) Large COMP Clamp

Figure 6-5. Auto-skip Mode Transient Response

Small COMP Clamp

UDG-12131

Figure 6-4. FCCM Transient Response

6.3.10 UVLO Protection

Undervoltage lockout protection (UVLO) monitors the internal VREG5 regulator voltage. When the VREG5
voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
6.3.11 Thermal Shutdown
The device monitors the internal die temperature. If this temperature exceeds the thermal shutdown threshold
value (TSDN typically 160°C), the device shuts off. This protection is a non-latch protection. During start-up, if
the device temperature is higher than 160°C, the device does not start switching and does not load the MODE
settings. If the device temp goes higher than TSDN threshold after start-up, the device stops switching with SS
reset to ground and an internal discharge switch turns on to quickly discharge the output voltage. The device
re-starts switching when the temperature goes below the thermal shutdown threshold but the MODE settings are
not re-loaded again.
6.3.12 Output Voltage Discharge
The device has a 500-Ω discharge switch that discharges the output VOUT through SW node during any event of
fault like output overvoltage, output undervoltage, TSD, if VREG5 voltage below the UVLO and when the EN pin
voltage (VEN) is below the turn-on threshold.
6.4 Device Functional Modes
6.4.1 Light Load Operation
When the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conduction
mode (FCCM) during light-load conditions. During FCCM, the switching frequency (FSW) is maintained at an
almost constant level over the entire load range which is designed for applications requiring tight control of the
switching frequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is
selected to operate in DCM/Eco-mode, the device enters pulse skip mode after the valley of the inductor ripple
current crosses zero. The Eco-mode maintains higher efficiency at light load with a lower switching frequency.
6.4.2 Standby Operation
The TPS56C215 can be placed in standby mode by pulling the EN pin low. The device operates with a
shut-down current of 7 μA when in standby condition.

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

The schematic of Figure 7-1 shows a typical application for TPS56C215. This design converts an input voltage
range of 4.5 V to 17 V down to 1.2 V with a maximum output current of 12 A.
7.2 Typical Application
VIN = 4.5 V - 17 V
VIN U1
TPS56C215
C1 C2 C3 C4 C5 C6 LOUT
0.1µF 0.1µF 22µF 22µF 22µF 22µF C9 VOUT = 1.2 V, 12 A
2 1
VIN BOOT VOUT
11 470nH
VIN
6 0.1µF
SW
7 C11 C12 C13 C14
SW R4 10.0k
14 13 47µF 47µF 47µF 47µF
SS FB
C7 15 3 C10
0.047µF EN EN PGND
4
R1 PGOOD PGND
16 5
PGOOD PGND
10.0k 8 56pF
PGND
17 9
VREG5 PGND
10 R5
PGND
R2 18 10.0k
MODE
52.3k C8 12
AGND
4.7µF R3
49.9k

Figure 7-1. Application Schematic

7.2.1 Design Requirements

Table 7-1. Design Parameters
PARAMETER CONDITIONS MIN TYP MAX UNIT
VOUT Output voltage 1.2 V
IOUT Output current 12 A
ΔVOUT Transient response 9-A load step 40 mV
VIN Input voltage 4.5 12 17 V
VOUT(ripple) Output voltage ripple 20 mV(P-P)
Internal
Start input voltage Input voltage rising V
UVLO
Internal
Stop input voltage Input voltage falling V
UVLO
FSW Switching frequency 1.2 MHz
Operating mode DCM
TA Ambient temperature 25 °C

7.2.2 Detailed Design Procedure

7.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS56C215 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

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3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability. In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
7.2.2.2 External Component Selection
7.2.2.2.1 Output Voltage Set Point
To change the output voltage of the application, changing the value of the upper feedback resistor is necessary.
By changing this resistor the user can change the output voltage above 0.6 V. See Equation 6.

æ R ö
VOUT = 0.6 ´ ç 1 + UPPER ÷
è RLOWER ø (6)
7.2.2.2.2 Switching Frequency and MODE Selection
Switching Frequency, current limit, and switching mode (DCM or FCCM) are set by a voltage divider from
VREG5 to GND connected to the MODE pin. See Table 6-3 for possible MODE pin configurations. Switching
frequency selection is a tradeoff between higher efficiency and smaller system design size. Lower switching
frequency yields higher overall efficiency but relatively bigger external components. Higher switching frequencies
cause additional switching losses which impact efficiency and thermal performance. For this design, 1.2 MHz is
chosen as the switching frequency, the switching mode is DCM and the output current is 12 A.
7.2.2.2.3 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the
output capacitor must have a ripple current rating higher than the inductor ripple current. See Table 7-2 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 7 and Equation 8. MAke sure
that the inductor is rated to handle these currents.

æ 2ö
ç 1 æ VOUT × (VIN(max) - VOUT )ö ÷
IL(rms)= ç I OUT + × ç
2 ÷
ç 12 ç VIN(max) × LOUT × FSW ÷ ÷÷
è è ø ø (7)

IOUT(ripple)
IL(peak) = IOUT +
2 (8)

During transient, short circuit conditions, the inductor current can increase up to the current limit of the device so
choosing an inductor with a saturation current higher than the peak current under current limit condition is safe.
7.2.2.2.4 Output Capacitor Selection
After selecting the inductor, the output capacitor needs to be optimized. In DCAP3, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in Table 7-2
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor must be less than
VOUT(ripple)/IOUT(ripple).

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Table 7-2. Recommended Component Values

VOUT (V) RLOWER (kΩ) RUPPER (kΩ) FSW (kHz) LOUT (µH) COUT(min) (µF) COUT(max) (µF) CFF (pF)
400 0.68 300 500 –
0.6 10 0 800 0.47 100 500 –
1200 0.33 88 500 –
400 1.2 100 500 –
1.2 10 800 0.68 88 500 –
1200 0.47 88 500 –
400 2.4 88 500 100–220
3.3 45.3 800 1.5 88 500 100–220
1200 1.2 88 500 100–220
400 3.3 88 500 100–220
5.5 82.5 800 2.4 88 500 100–220
1200 1.5 88 700 100–220

7.2.2.2.5 Input Capacitor Selection

The minimum input capacitance required is given in Equation 9.

IOUT ×VOUT
CIN(min) =
VINripple ×VIN ×FSW (9)

TI recommends using a high quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by Equation 10:

VOUT (VIN(min)-VOUT )
ICIN(rms) = IOUT × ×
VIN(min) VIN(min) (10)

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7.2.3 Application Curves

Figure 7-2 through Figure 7-8 apply to the circuit of Figure 7-1 . VIN = 12 V, fSW = 800 kHz, Ta = 25°C unless
otherwise specified.

100 1.206

90 1.205
1.204
80
1.203

Output Voltage (V)

Efficiency (%)

70 1.202
60 1.201

50 1.2
1.199
40
1.198
30 1.197
20 1.196
0.001 0.01 0.1 1 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) Output Current (A)

Figure 7-2. Efficiency Figure 7-3. Load Regulation

Figure 7-4. Output Voltage Ripple, IOUT = 10 mA, Figure 7-5. Output Voltage Ripple, IOUT = 12 A,
Time = 80 μS/div Time = 1 μS/div

Figure 7-6. Start-Up Relative to EN Rising, Time = 2 Figure 7-7. Shutdown Relative to EN Falling, Time
ms/div = 200 μS/div

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Figure 7-8. Transient Response, Load Step = 3 A – 9 A – 3 A, Slew Rate Setting = 2.5 A/μS, Time = 100
uS/div

7.3 Power Supply Recommendations

The TPS56C215 is intended to be powered by a well regulated dc voltage. The input voltage range is 3.8 to 17
V. TPS56C215 is a buck converter. The input supply voltage must be greater than the desired output voltage
for proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS56215 circuit, some additional input bulk capacitance is recommended. Typical
values are 100 µF to 470 µF.
7.4 Layout
7.4.1 Layout Guidelines
• Recommend a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3"
× 3", four-layer PCB with 2-oz. copper used as example.
• Recommend having equal caps on each side of the IC. Place them right across VIN as close as possible.
• Inner layer 1 is ground with the PGND to AGND net tie
• Inner layer2 has VIN copper pour that has vias to the top layer VIN. Place multiple vias under the device near
VIN and PGND and near input capacitors to reduce parasitic inductance and improve thermal performance
• Bottom later is GND with the BOOT trace routing.
• Reference feedback to the quite AGND and routed away from the switch node.
• Make VIN trace wide to reduce the trace impedance.
7.4.2 Layout Example
Figure 7-9 shows the recommended top side layout. Component reference designators are the same as the
circuit shown in Figure 7-1. Resistor divider for EN is not used in the circuit of Figure 7-1, but are shown in the
layout for reference.

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PGOOD
OUTPUT

REN2
R1

R2

R5
REN1

C10
R3

R4
C8

C7
MODE

PGOOD
VREG5

EN

SS

FB
C9
BOOT AGND

VIN VIN

C1 PGND PGND
C2

SW

SW
C3 C4 C5 C6
PGND PGND

PGND PGND

L1

C11 C12 C13 C14

Figure 7-9. Top Side Layout

26 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

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 TPS56C215
www.ti.com SLVSD05H – MARCH 2016 – REVISED JUNE 2025

Figure 7-10 shows the recommended layout for the first internal layer. The figure is comprised of a large PGND
plane and a smaller ANGD island. AGND and PGND are connected at a single point to reduce circulating
currents.

AGND

SINGLE POINT
AGND TO PGND
CONNECTION

PGND PLANE

Figure 7-10. Mid Layer 1 Layout

Figure 7-11 shows the recommended layout for the second internal layer. The figure is comprised of a large
PGND plane, a smaller copper fill area to connect the two top side VIN copper areas and a second VOUT copper
fill area.

VIN

PGND PLANE

VOUT

Figure 7-11. Mid Layer 2 Layout

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: TPS56C215
TPS56C215
SLVSD05H – MARCH 2016 – REVISED JUNE 2025 www.ti.com

Figure 7-12 shows the recommended layout for the bottom layer. The figure is comprised of a large PGND plane
and a trace to connect the BOOT capacitor to the SW node.

PGND PLANE

Figure 7-12. Bottom Layer Layout

28 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TPS56C215

 TPS56C215
www.ti.com SLVSD05H – MARCH 2016 – REVISED JUNE 2025

8 Device and Documentation Support

8.1 Device Support
8.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
8.1.2 Development Support
The evaluation module for system validation in shown in Figure 8-1.

Figure 8-1. System Validation EVM Board

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: TPS56C215
TPS56C215
SLVSD05H – MARCH 2016 – REVISED JUNE 2025 www.ti.com

8.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS56C215 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability. In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
SWIFT™, D-CAP3™, HotRod™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

30 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

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 TPS56C215
www.ti.com SLVSD05H – MARCH 2016 – REVISED JUNE 2025

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (August 2024) to Revision H (June 2025) Page
• Changed MOSFET values from 13.5mΩ and 4.5mΩ to 7.8mΩ and 3.2mΩ.......................................................1
• Added WEBENCH link in the Features ............................................................................................................. 1
• Updated Efficiency vs Output Current figure to include the most recent data for the device............................. 1
• Updated RDS(on)H from 13.5 mΩ to 7.8 mΩ , RDS(on)L from 4.5 mΩ to 3.2 mΩ and tUVPEN hiccup time from 7
cycles to 14 cycles..............................................................................................................................................5
• Changed IIN typ value from 600µA to 146µA and deleted IIN max value............................................................5
• Changed IVINSDN typ value from 7µA to 9.3µA................................................................................................... 5
• Changed VPGOODTH VFB falling (good) value from 107% to 108%....................................................................5
• Changed VUVP value from 68% to 70%..............................................................................................................5
• Changed UVLO VREG5 rising voltage value from 4.3V to 4.25V...................................................................... 5
• Changed UVLO VREG5 falling voltage value from 3.57V to 3.52......................................................................5
• Changed UVLO, VREG5 = 4.7V VIN falling voltage, VREG5 = 4.7V value from 3.26V to 3.24V...................... 5
• Changed UVLO, VREG5 = 4.7V VIN hysteresis, VREG5 = 4.7V value from 60mV to 80mV............................ 5
• Changed tON min value from 54ns to 60ns.........................................................................................................6
• Changed tSS value from 1.045ms to 1.2ms........................................................................................................ 6
• Updated Figure 5-9 to Figure 5-34 to include the most recent data for the device............................................ 7
• Deleted High-side RDS(on) vs Temperature and Low-side RDS(on) vs Temperature figures........................... 7
• Changes MOSFET values from 13.5-mΩ to 7.8-mΩ and 4.5-mΩ to 3.2-mΩ................................................... 13
• Changed "Zero Location" values in Table 6-1 from 7.1 to 17.8, from 14.3 to 27.1, from 21.4 to 29.8..............14
• Changed wait time from 1 ms to 1 × tSS and hiccup time from 7ms to 14 × tSS .............................................. 19
• Added the Transient Response Enhancement section.....................................................................................20
• Added Custom Design With WEBENCH® Tools section..................................................................................21
• Updated Application Curves to include the most recent data for the device.................................................... 24
• Added Custom Design With WEBENCH® Tools section..................................................................................30

Changes from Revision F (August 2023) to Revision G (August 2024) Page

• Changed description "TI's smallest" to "a small" with updated products portfolio. ............................................ 1
• Deleted TSDN VREG5 spec....................................................................................................................................5
• Added note "Specified by design" for the SW On Time parameter.................................................................... 6
• Removed Out-of-Bounds Operation section.....................................................................................................14
• Updated Thermal Shutdown section................................................................................................................ 20

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31

Product Folder Links: TPS56C215
TPS56C215
SLVSD05H – MARCH 2016 – REVISED JUNE 2025 www.ti.com

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10.1 Package Marking

TI = TI Letters
YM = Year Month Date Code
S = Assembly Site Code
LLLL = Assembly Lot Code
56C215
TI YMS
LLLL Y : Year Code (1, 2, 3, 4, 5, 6, 7, 8, 9, 0)
M : Month Code (1, 2, 3, 4, 5, 6, 7, 8, 9, 0, A, B, C)

Figure 10-1. Symbolization

32 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TPS56C215

 PACKAGE OPTION ADDENDUM

www.ti.com 2-Aug-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TPS56C215RNNR Active Production VQFN-HR (RNN) | 18 3000 | LARGE T&R Yes Call TI | Sn Level-2-260C-1 YEAR -40 to 125 56C215
TPS56C215RNNR.A Active Production VQFN-HR (RNN) | 18 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 56C215
TPS56C215RNNR.B Active Production VQFN-HR (RNN) | 18 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 56C215
TPS56C215RNNT Active Production VQFN-HR (RNN) | 18 250 | SMALL T&R Yes Call TI | Sn Level-2-260C-1 YEAR -40 to 125 56C215
TPS56C215RNNT.A Active Production VQFN-HR (RNN) | 18 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 125 56C215

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Mar-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS56C215RNNR VQFN- RNN 18 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
HR
TPS56C215RNNT VQFN- RNN 18 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
HR
TPS56C215RNNT VQFN- RNN 18 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
HR

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Mar-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS56C215RNNR VQFN-HR RNN 18 3000 367.0 367.0 35.0
TPS56C215RNNT VQFN-HR RNN 18 250 210.0 185.0 35.0
TPS56C215RNNT VQFN-HR RNN 18 250 213.0 191.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RNN0018A SCALE 3.200
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.6
B A
3.4

PIN 1 INDEX AREA

3.6
3.4

ALTERNATE PIN 1 ID SHAPE

30.000

1.0 C
0.8

SEATING PLANE
0.05
0.00 0.08 C

0.6
1.0
0.35 8X
2X 0.9
0.25 (0.2) TYP
6 7

5 8
4X 0.55
0.3
6X
0.2
2X 0.65 2.5
2X
2.3
PKG

2X
0.925
12 0.45
1 2X
0.35
2X 0.575

SEE ALTERNATE
PIN 1 ID DETAIL
18 13
SYMM 0.3
0.45 8X
7X 0.2
0.35 0.1 C B A
0.45 5X 0.5
0.05 C ALL PADS
0.35
2.5
4222688/E 03/2021
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RNN0018A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.5)

2X (1.65)
5X (0.5)
SYMM
18 13

8X (0.6) (1.65)

8X (0.25)
1 (R0.05) TYP
EXPOSED METAL
2X (0.925) TYP 12
2X (0.4)

2X (0.35) 11
2
PKG 0.000

2X (0.3) 2X
(2.6)

(0.65)
2X (0.85)

2X (1.4) 8
5

6X (0.25)
8X (1.15)

6 7
2X (0.3)
2X (0.3) 8X (1.375)

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
EXPOSED METAL SHOWN 0.05 MIN
0.05 MAX
SCALE:25X ALL AROUND
ALL AROUND
METAL EDGE METAL UNDER
SOLDER MASK

EXPOSED SOLDER MASK EXPOSED

METAL OPENING METAL SOLDER MASK
OPENING

NON SOLDER MASK SOLDER MASK DEFINED

DEFINED
(PREFERRED) SOLDER MASK DETAILS
4222688/E 03/2021
NOTES: (continued)

3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
RNN0018A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.5)
(1.65)
5X (0.5) SYMM
18 13

8X (0.6) (1.65)

8X (0.25)
1
EXPOSED
2X (0.925) METAL, TYP 12
6X (0.3)

2X (0.36)

2 11
2X (0.35)
(0.2825)

PKG 0.000

6X
2X (0.3) (0.733)

(0.651)

2X (0.85)

2X (1.4) 8

5 (1.585)
6X (0.25)
8X (1.15)
EXPOSED METAL
TYP
EXPOSED METAL 6 7
TYP
(R0.05) TYP 8X (1.375)
(0.3) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 6 & 7: 83% - PADS 2 & 11: 90%
SCALE:30X

4222688/E 03/2021

NOTES: (continued)

5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.

www.ti.com
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