tiodel 455

Constant Fraction Timing

Single Channel Analyzer
Operating~ and Service Manual

This manual applies to instruments marked

“Rev 13 (on rear panel)

PrinUd in “.S.A.
 OkTEC435 COl?STANT
FUACTIONTIMI~ SIlQLB%~Eti AI?&YBm
RFIV455-14
October 28, 1-976
Oo l cbemetlc 45$-0101-61, change the valuer of the follouinp pert@8
ChengeDS from type lN754A to 219827A.
Chanse R27 from 1969 to 2050.
C@4ngeR28 from 17M~to 10M.
ch4u* 8185 fror~l780 to 109.~
A 22-pl eepeeiter,nq ;&e connected fros 1%~7 to gtouad if tequllred
in qu&lLty a+tol ,&@irrg checbout.
 STANDARD WARRANTY FOR ORTEC INSTRUMENTS

ORTEC warrants that the items will be delivered free from defects in material or workmansjtip. ORTEC makes no other
warranties, express or implied, and specifically NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE.

ORTEC’s exclusive Liability is limited to repairing or replacing at ORTEC’s option, items found by ORTEC t0 be defective in
workmanship or materials within one year from the date of delivery. ORTEC’s liability on any claim of any kind, including
negligence, loss or damages arising out of, connected with, or from the performance or breach thereof, or from the
manufacture, sale, delivery, resale, repair, or ure of an+ ~item or services covered by this egreem&nt bra purchase order, shall in
no case exceed the price allocable to the item or service furnished or any pert thereof that gives rim to the claim. In the event
ORTEC fails to manufacture or deliver items called for in this agreement or purchase order, ORTEC’! bXCIUSiVe liability and
buyer’s exclusive remedy shall be release of the buyer from the obligation to pay the purchase price. In no event shall ORTEC
be liable for special or consequential damages.

QUALITY CONTROL

Before being approved for shipment, each ORTEC instrument must pass a stringent set bf~quelity control tests designed to
expose any flaws in materials or workmanship. Permanent records of these tests are maintained for use in warranty repair and
es a source of statistical information for design improvements.

REPAIR SERVICE

If it becomes necessary to return this instrument for repair, it is essential that Customei Servi be contacted in advance of
its return so that a Return Authorization Number can be assigned to the unit. Also, ORTE 2+must be informed, either in
writing or b$ telephone [(615) 482-441 t] , Of the nature of the fault of the instrument pei+tS retqr.ryd and of the model,
serial, and revision (“Rev” on rear panel) numbers. Failure to do so inay cause unnaces~ary dp!dps,i,n getting the unit repaired..
The ORTEC standard procedure requires that instruments returned for repair pass the sam?;&iility control tests that are used
for new-production instruments. Instruments that are returned should be packed so that they will withstand normal transit
handling and must be shipped PREPAID via Air Parcel Post or United Parcel Service to the nearest ORTEC repair center. The
address label and the package should include the Return Authorization Number assigned. Instruments being returned that are
damaged in transit due to inadequate packing will be repaired et the sender’s expense. and it will be the sender’s responsibility
to make claim with the shipper. Instruments not in warranty will be repaired et the standard charge unless they have been
grossly misused or mishandled, in which case the user will be notified prior to the repair being done.,A quotation will be sent
with the notification.

DAMAGE IN TRANSIT

Shipments should be examined immediately upon receipt for evidence of external or concealed damage. The carrier making
delivery should be notified immediately of any such damage, since the carrier is norm& liable for damage in shipment.
Packing materials, waybills, and other such documentation should be preserved in order to establish claims. After such
notification to the carrier, please notify ORTEC of the circumstances so that assistance can be provided in making damage
claims and in providing replacement equipment if necessary.
 iii

TABLE OF CONTENTS

WARRANTY ii

PHOTOGRAPHS iv

1. DESCRIPTION 1

2. SPECIFICATIONS 2

3. INSTALLATION
3.1 General
3.2 Connection to Power
3.3 Connection to a Linear Amplifier
3.4 Linear Output Signal Connections and Terminating Impedance Considerations

4. OPERATING INSTRUCTIONS 5
4.1 Introduction to Fast Timing with Linear Signals 5
4.2 TYpical Operating Conditions 5
4.3 Front-Panel Control Functions 5
4.4 Rear-Panel Control Functions 6
4.5 Connector Data 6

5. CIRCUIT DESCRIPTION 7
5.1 Input Circuit
5.2 Single Channel Analyzer
5.3 Reference Levels
5.4 Internal Timing Signal
5.5 Single Channel Output
5.6 External Strobe Operation

6. MAINTENANCE 9
6.1 Testing Performance 9
6.2 Calibration Adjustments 9
6.3 Testing the 455 Timing Walk 10
6.4 Procedure for Adjusting Walk 10
6.5 Factory Repair 11

BLOCK DIAGRAM AND SCHEMATIC 455.0101.81 455.0101.Sl

LIST OF FIGURES

Page

Fig. 1.1. Time Resolution as a Function of Dynamic Range 1

Fig. 4.1. Principle of Constant Fraction Timing Signal Derivation 5
Fig. 6.1. Basic Interconnections for Level Calibrationr 9
Fig. 6.2. System Interconnections for 455 Walk Test 10
Fig. 6.3. Waveforms for Propar Adjustment 10
Fig. 6.4. Waveforms for Improper Adjustment 10
I”

/I OUTPUT 1;
I

-INPUT ;

I
 1

ORTEC 455 CONSTANT FRACTION TIMING SCA

1. DESCRIPTION

The ORTEC 455 Constant Fraction Timing Single Channel main amplifier output. It allows optimization of time
Analyzer provides both pulse-height and timing analysis for resolution and extension of dynamic range for neutron-
unipolar and bipolar signals. The Constant Fraction Timing gamma discrimination.
technique providesunexcelled timing on unipolar pulsesand
a unique crossover discriminator shows results better than The 455 can Bccuratelv analyze the o”tput pulses of any
heretofore possible with conventional leading edge or cross- shaping amplifier because the discriminator levels are ex-
wer discriminators. tremely sharp and stable. A front-panel control selects four
SCA modes: integral, 100%. 20%. and normal. These modes
Actual timing results obtained with the 455 and fast of operation are described in the specifications that follow.
plastic scintillators are shown in Figure l-1. The advantage
of the constant fraction timing technique is readily apparent. With all of its versatility, ease of operation is an intrinsic
With SCA’s which utilize leading edge timing, the risetime quality of the 455. ln:all operating modes and with input
of the input pulses causes degradation of time resolution pulse shaping from 0.1 to 10 wc, no risetime compensation
because the pulses have varying amplitudes. Constant or other adjustments are necessary for proper operation.
Fraction timing compensates for varying amplitudes and
essentially eliminates this timing shift, giving consistently The dc-coupled input ‘of the 455 makes it possible to take
better timing results. For a 10% fraction, the output occurs full advantage of the baseline restoration of the main
soon after the peak of the input to facilitate gating and amplifier. For amplifiers with ac-coupled outputs. two
accumulation of dataatvery high input rates. This technique ranges of dc restoration are available. These features ensure
also minimizes timing shift and dead time when used with stable discrimination levels for widely varying input count-
sodium iodide, silicon, and germanium detectors, thereby ing rates, and hence better energy discrimination.
allowing better system time resolution and higher counting
rates. Timing results paralleling those in Figure l-l are also The continuously adjustable output delay (two ranges
possible with these detectors. The Constant Fraction covering 0.1 to 11 ~sec) makes it possible to align output
technique makes it possible to realize significant improve- signals which have actual time differences without a need
ments in most applications where analysis is made of the for additional delay devices or modules.

-
1.
1 to 100

Figure l-l. Time Resolution as a Function of Dynamic Range

 2

2; SPECIFICATIONS

PEflFOR,MANCE FRACTION A front panel switch selects the fraction of

0.1, 0.2, 0.3, 0.4, and 0.5 for Constant Fraction timing
Time shift VI pulse height (walk) with unipolar or bipolar inputs, or Ei for zero crossing
timing with bipolar inputs.
Constant Fraction Timing M&a
Walk Ins& Dynamic SCA MODES Front panel switch selects the following
System A System 8 Range
modes:
<*1.5 Gil.5 1O:l
Qf3.7 <i8 EdI:1 INTEGRAL Timing outputs ocwr for all signals with
Gf4.5 <*lo 1OO:l
amplitudes abwe thelower-level discriminator setting.
System A: Using ORTEC 410 Amplifier,
single delay line, mode. integrate NORMAL Timing outputs o&r for signals with ampli-
GO.1 wag: with delay lines of 0.2 to tudes between the lower-level and upper-level settings.
z/J= The MO controls are independently adju$table.
System 6. Using ORTEC 4w or 451 .:$
Amplifier unipolar output with 0.5 20% WINDOW Timing outputs occu&!r signals with
waec shaping time and 0.4 fraction. amplitudes between the lower level and the sum of
the lower-level and 0.2X upper level. The spa” (1000
Bi Mode -divisions) of the upper-level control (window) is 2 V.
Walk Dynamic
Insed Range 100% WINDOW Timing outputs occur for signals with
amplitudes between the lower level and the sum of
<*1 1O:l
the lower level and the upper level. The span (1000
< f 2.5 50:1 .
1OO:l divisions) of the upper-level control (window) is 0 to
<f3
1ov.
Using ORTEC 410 Amplifier, double
delay line mode, integrate < 0.1, @ec
with delay lines of 0.2 to 2 /Jsec. RESTORER A 5position rear-panel switch to allow input
dc-coupling. or a high or low baseline restoration rate.

Pulse pair resolution O.B!.~sec plus the delay time.

EXT. STROBE/INT/EXT BASELINE A rear-panel switch
Nonlinearity Lower level 6 f 0.25%. upper level C; f 0.25%. selects internal strobe and baseline, external baseline
(Nonlinearity, specifications are limited by the lo-turn r@fennce, or external strobe. In the external baseline
potentiometer.) mode’ue lo&r level is set by the external reference.
5 In the exte&i&strobe mdde the timing outputs occur
Temperature stability in coincidence with thestiobepulse..
upper level: <f O.O05%PC “. ,,
Lower level : < f 0.005%/Y WALK ADJUST Front panel screwdriver adjust&nt’f3i
Delay: < f O.Ol%pC precise setting of walk compensation.

CONTROLS CONNECTORS All signal connectors are BNC connectors

(UG-1094/U).
LOWER LEVEL lo-turn control sets the lower level from
100 mV to 10 V (1MH) divisions = 10 V). INPUTS

UPPER LEVEL IO-turn control sets the upper level from Analog Input
100mVto10V(1000divisions=lOV).
Amplitude range 0 to 10 V
DELAY RANGE Rear-panel switch selects range of 0.1 to
1 .l or 1 .O to 11 pet delay. Pulse width range 0.2 to 20 ~.tsec at half amplitude

DELAY 10.turn control for continuously adjusting output Polarity Positive (unipolar) or positive portion leading
delay over selected delay range. In the external strobe (bipolar)
mode the delay control adjusts the automatic reset time
from - 5 to 50 mc. Input impedance 1000 ohms dc-coupled
 3

External Input -Strobe/Baseline Diroriminator Outputs Thesignal occurs promptly when the
input exceeds the discriminator threshold.
Input impedance Greaterthan 1000 ohms dc-coupled
UL Positive5 V,risetime <20 nsec, width 0.5 /.wc, Z. =
Strobe input +2 V niin, +12 V max. 75 nsec min < 10 ohms (rear panel).
width
LL Positive 5 V. risetime < 20 nsec, width 0.5 &wc, Z, =
Baseline amplitude 0 to -10 V < 10 ohms (rear panel).

OUTPUTS

Timing Outputs. In the Constant Fraction mode the

timing outputs occur when the input pulse has fallen
from its peak by the selected fraction (plus the delay ORDERING INFORMATION
time). In the Eii (bipolar) mode the timing outputs
occur when the input pulse crosses the baseline Power Required +24 V 70 mA +12 V 150 mA
(plus the delay time). -24V59mA -12VlOOmA
1
NE&the current output produces 0.7 V minimum into Weight (Shipping) 3 lb 6 oz (1.5 kg)
5O‘;ghms with r&time < 5 nsec and width < 20 nsec
(front panel). Weight (Net) 2 lb 7 02 (1.1 kg)

POS Positive 5 V risetime less than 20 “sec. width Dimensions Standard single width module per TID-20693
O.~/.WC. &, =< 10 ohms (front panel). mev.)

?i
 4

3. INSTALLATION

3.1 General 0 to 10 V, delivered into it. It is permissible to parallel

several loads on a single output while preserving the 0- to
The ORTEC 455 is designed for installation in an ORTEC 10-V signal span.
401A/402A Bin and Power Supply, which is intended for
rack mounting. Any vacuum tube equipment operated Short lengths of interconnecting cable (up to approxi-
in thesame rack must be cooled by circulating air to prevent mately 4 ft) need not be terminated. If, however, a linear
any localized heating of the all-transistor circuitry used signal is to pass through more than approximately 4 ft
throughout the 455. The temperature of equipment of cable, it should be terminated in a resistive load equal to
mounted in racks can easily exceed the recommended the cable impedance. Since the output impedance is not
maximum of 120°F (50°C) unless precautions are taken. purely resistive and is slightly different for each individual
module, coaxial cable of more than 4 ft not terminated
3.2 Connection to Power in the characteristic cable impedance will generally cau?e
oscillations. These oscillations can be suppressed for any
The 455 contains no internal power supply and so must length of cable by terminating the cable properly. either in
obtain power from a Nuclear Standard Bin and Power series at the sending end or in shunt at the receiving end of
Supply such as the ORTEC 401A/402A. Turn off the Bin the line.
power supply before inserting or removing modules. The
ORTEC 400 Series modules are designed so that it is not To terminate a cable properly at the receiving end, it may
possible to overload the Bin power supply with a full be necessary to choose an additional parallel resistance
complement of modules in the Bin. Since this may not be to the input resistance of the driven circuit to make the
true, however, when the Bin contains modules other than combination produce the desired termination resistance.
those of ORTEC design, check the power supply voltages Series terminating the cable at the sending end may be
after inserting modules. The 401A/402A has test points on preferable when receiving-end terminating is not possible
the power supply control panel to monitor the dc voltages. or desirable. Many ORTEC linear instruments include an
alternate output connector for an output impedance of
3.3 Connection to a Linear Amplifier 93 ohms, and this connector may be used when 93.ohm
cable is used for the int&onnection: the impedance
The input to the 455 is a front-panel BNC connector. It match will then be complete without any compensation
may be used to accept outputs from all linear amplifiers at the high-impedance receiving end. When series terminat-
capable of producing 10-V unipolar or bipolar (positive ing at the sending end, full signal span (amplitude) is
lobe leading) signals. onto a 1000.ohm load. The input obtained at the receiving end, only when it is essentially
operating range is from 100 mV to 10 V. If the amplifier unloaded or is loaded with an impedance many times that of
output is attenuated so that it cannot exceed 10 V, the 455 the cable. Since the input impedance of the 455 is 1000
may be used with vacuum tube amplifiers which are capable ohms, a series termination at the sending end of the cable
of dutput signals to 100 V. Simple resisitve attenuators will normally provide satisfactory results.
installed in the vacuum tube amplifiers will make them
compatible with related transistor equipment. BNC tee connectors and connectors with internal resistive
terminators are available from a number of manufacturers
3.4 Linear Output Signal Connections and Terminating in nominal values of 50, 100, and 1000 ohms to facilitate
Impedance Considerations shunt termination at the receiving end of a cable. ORTEC
stocks in limited quantity the following connector ac-
The source impedance of the 0. to 10-V standard linear cessories for this application:
outputs of most ORTEC 400 Series modules is approxi-
mately 1 ohm. Interconnection of linear signals is thus ORTEC C-27 loo-ohm Resistive Terminator
not critical since the input impedance of the 455 is high and O,RTEC C-28 50.ohm Resistive Terminator
is’not important in determining the actual signal span, ORTEC C-29 BNC Tee Connector
 5

4. OPERATING INSTRUCTIONS

4.1 introduction to Fast Timing with Linear Signals

The precise determination of the time of a nuclear event,

simultaneous with the mea~uramant of its energy, hasbeen
restricted in the past to two timing techniques - zero
crossing and level discrimination. In the zero-crossing
method the timing SCA simply detects the time at which
a bipolar linear signal crosses the baseline. For a double-
delay-line shaped signal the zero-crossing phase point con-
tains the same information as the 50% charge collection
time on the leading edge of the signal. For some signals the Figure 41. Principle of Constant Fraction
zero-crossing point provides excellent time resolution. Timing Signal Derivation

There are two rather savera limitations to~the zero-crossing

technique. First, the amplitude n&e of a bipolar signal is
normally worse than a similarly shaped unipolar signal.
Consequently, the edges of the energy window set by the given signal shape can be obtained, in addition to the
SCA are not as precise as they would be for a unipolar signal. systematic walk being eliminated. Bipolar inputs can be
The second limitation of the zero-crossing technique is accepted but era not required. By selecting smaller
that the time information cannot be obtained until the fractions, the timing signal is derived very near the input
signal crosses the baseline. The added time delay before signal peak to minimize the added~delay before the signal
getting the time information is not a savera limitation in arrives at the output.
DDL applications, but for simulated Gaussian-shaped signals
the added delay may be several microseconds. 4.2 Typical Operating Conditions

A simple level discriminator is used to obtain time infor- Each application of the 455 involves a specific datector-to-
mation by the second technique. The usual mode of amplifier configuration with unique pulse shape character-
operation allows the level discriminator to trigger on the istics. inspection of the details of the pulse will aid in
leading edge of the signal and to then reset when the signal Selection of the timing fraction that will provide the best
falls below the discrimi,nator level. Either of these trigger accuracy. The Constant Fraction is selected at a point along
points can be used for the timing information. If the the decay of the input pulse and measured as a portion
leadingedge trigger point is used, it must be delayed beyond of the drop from peak amplitude toward the baseline. The
the peak of the input signal for the single-channel ampli- optimum point along the decay is one with maximum
tude decision to bemade. The basic limitation of this system slope and minimum noise; this will rasult in the largest
is that it introduces a time walk due to changing signal slope-to-noise ratio. When two or more points offer~about
amplitudes, and the magnitude of the walk is usuallyequal equal qualifications, the smaller fraction provides the
to approximately the rise time of the signal. For different earlier timing output.
types of signals this walk will range from tens of nano-
seconds to microseconds. Note that the fraction selected refers to the fraction of
amplitude decay toward the baseline as measured from
The 455Constant Fraction Timing Single Channel Analyzer the input pulse peak. The settings are from 10% through
introduces a new timing technique that has been applied 50%. plus Bipolar which is equivalent to a 100% fraction
successfully in many fast timing applications. The CFPHT selection. The resulting stretched signal level is shown to be
(Constant Fraction of Pulse Height Trigger) provides a greater than the lower-level discriminator in Figure 4-1, but
degree of freedom from the major limitations imposed by this condition is not required; in fact, the smaller amplitude
the two techniques previously used. This feature can be input signals which are just large enough to trigger the
understood best by observing the basic wave shapes in lower-level discriminator will normally provide a stretched
Figure 4-1. The linear signal is stretched and attenuated signal level below the lower level. See Sections 5.3 and 5.4
by an amount set by the fraction switch, F. The timing for further information.
discriminator is triggered when the signal exceeds the lower-
level discriminator. The timing discriminator is then rasat 4.3 Front-Panel Control Functions
when the signal becomes less than the stretched attenuated
signal, as shown in Figure 4-1. For a signal with a different Mode Selector. This four-position switch ?elects the integral
amplitude the stretched signal remains a cowsent fraction mode or one of three circuits for the differential modefor
of the signal amplitude and the re%et of the lower-level the single-channel analyzer. For the integral mode the
discriminator remains timeinvariant. By selecting the lower-level discriminator or an external baseline will
fraction judiciously, en optimum time rasolution for a determine response, and no upper-level discriminator is
 6

involved. For NORM, both discriminators are effective control is disconnected and the lower-level reference must
and their control ranges are completely independent; the be furnished by a 0- to negative 10-V bias through the ad-
Upper Level control must select a level greater than the jacent BNC; internal strobe must be used. since there is no
glower Level control or external baseline input. or no provision for an external strobe input.
output can be generated. For the 20% WIN position, the
Upper Level control selects the amount by which the DELAY. This slide switch selects either of the two
Upper-level discriminator reference exceeds the lower- Bffective ranges for the Delay front-panel control. The
level reference. and the control range is 0 to 2 V. For the ranges are 0.1 through 1.1 p and 1.0 through 11 /IS.
100% WIN position the same type of window circuit is
effective, and the Upper Level control range is increased to BLR. This 3.position slide switch selects the input circuit
the full O-to 10-V dynamic range. appropriate to each specific application. The DC position
his a dc-coupled input and may be used when there is no
FRACTION. This six-position contrc+is concentric with the baseline offset furnished from the input pulse source. LO
mode selector. It permits selection of lo%, 20%. 30%. and HI positions refer to the average .input pulse rate; the
40%. or 50% Fraction for timing or Bi, which is the con- LO position selects a passive r&oration circuit, while the
ventional zero-crossing timing mode. See Sections 4.2,5.3. HI position selects an active baseline restorer.
and 5.4 for suuggestions on the use of this switch.
4.5 Connector Data
UPPER LEVEL. This IO-turn precision potentiometer
selects the upper-level reference. Its range is 0 to 10 V, read INPUT. A BNC connector accepts the analog input signals
directly by the 1000 divisions of the duo-dial. Whtin the 455 into input impedance of 1,000 ohms. The input circuit
operates in its 20% Window mode, the effective range of will be either dc- or ‘ac-coupled; depending upon the
the Upper Level control is 0 to 2 V. selection of the rear-panel BLR switch. Either positive
unipolar pulses or bipolar pulses with positive leading
LOWER LEVEL. This IO-turn precision potentiometer portion may be furnished within the O- to +10-V linear
selects the lower-level reference, except when a rear-panel range.
switch selects External Baseline. Its range is 0.1 to 10 V.
read directly on the control. NEG. OUT. A standard ORTEC land NlMl fast negative
logic signal is available through this BNC connector for
DELAY. This IO-turn precision potentiometer adjusts optimum timing resolution. This is a current output pulse
fhee from the timing comparator signal to the SCA that produces 0.7 V minimum into 50 ohms.
output signals, except when a rear-panel switch is set at
External Strobe. The delay can be adjusted from 0.1 POS. OUT. A standard ORTEC land NIM) slow positive
through 11 JIS; a rear-panel switch selects either an logic signal is available through ‘this BNC connector
0.1. to 1.1./JS range or a 1.0. to 1 I-/IS rangeand the selected for applications such as analyzer gating and coincidence
delay is read directly on the control of the potentiom- timing.
eter.
UL. A standard ORTEC land NIM) slow positive logic
WALK ADJ. This screwdriver potentiometer adjusts for r&J is furnished through this BNC connector each time
minimum time walk, as a fine control for any selected the upper-level discriminator is triggered, without regard
fraction. See Section 6.7 for further information. to the internal use of the upper-level, response.

LL. A standard ORTEC land NIMI slow positive logic

4.4 Rear-Panel Control Functions *aI is furnished through this BNC connector each time
the lower-level discriminator is triggered, without regard
EXT STROBE/INT/EXT EL. This 3position slide switch to the internal use of the lower-level response.
permits the adjacent~ BNC connector to be used for either
of two externally controlled functions. When it is set at EXT INPUT. This BNC connector accepts either external
INT, neither of the external functions will be effective. strobe pulses or 8” external baseline bias level. depending
When it is ~set at EXT STROBE, the SCA timing outputs upon the selection of the adjacent 3.position slide switch.
occur in coincidence with an external strobe input pulse
furnished thrwgh the BNC, and this must occur within less Test Points. Oscilloscope test point?. for monitori@ the
than 50 .us after the lower-level discriminator is triggered; input and the two single-channel outputs on the front panel
the lower-level reference is set by the front-panel Lower are availableat each connector. Each test point is connected
Level controL during the external strobe mode. When the to its respective connector through a 470.ohm series
switch is set at EXT BL, the front-panel Lower Level resistor.
 7

5. CIRCUIT DESCRIPTION

5.1 Input Circuit comparator output. The output pulse duration is 0.5 p
and its amplitude is +5 V approximately. The pulse occurs
The input signal is presented to a dorestorer circuit, or is on the leading edge of the input pulse when the input
dc-coupled, directly info a unity gain amplifier, Q5 to Q9. exceeds the Lower Level bias and is available through the -
A rear-panel switch selects either HI or LO dc-restoration rear-panel LL connector.
rate or de-coupling. Input capacitor Cl i%simply bypassed
for dc-coupling. For the LO restoration rate, Ql and Q2 The Upper Level output pulse is identical to the Lower
form a Robinson type of restorer circuit. For the HI Level output discussed above and is generated by IC 4A.
restoration rate, Q3 and Q4 operate as a high-gain dif- Q40, and Q41. It occurs on the leading edge of the input
ferential amplifier to feed back a voltage to the emitter of pulse when the input exceeds the Upper Level bias and is
02 that is inversely proportional to the dc offset voltage available through the rear-panel UL connector.
at Cl. Thus, in the HI rate circuit, restoration of thevoltage
to zero is achieved~ by an active closed-loop feedback The temporary memory for the Lower Level comparator
amplifier. is IC 2, sections A, 6, C, and D. It is a monostable with e
duration of 50 flus but is normally re?et prior to this time,
Following the restorer. the signal is attenuated for half of just after the pulse-height decision is made. Its output
its input value, using resistors R9 and RlO. It is then buf- goes from +1.5 V to -0.5 V and is furnished es one of two
fered by the unity gain amplifier, Q5 - Q9, and furnished inputs to IC 1 D. The temporary memory for the Upper Level
to four internal circujts. The amplifier is dc-coupled with a comparator is IC 1, sections A, B, end C. It also has a dura-
.very low output impedance to drive all three comparators, tion of 50 us, subject to prior reset. The output from this
IC 5 through IC 7. with no appreciable loading effectsdue memory, furnished as the second input to IC 1D. goes from
to the comparator base currents. The signal et the unity -0.5 V to +1.5 V when it is triggered.
gain amplifier output has half of the input amplitude for its
positive polarity; any negative polarity included in the When either input (or both) to OR gate IC 1D is et +1.5 V,
input is clipped two diode junctions (approximately -1.4 VI it will drive Q67 into saturation, thus preventing the timing
below zero. The quiescent voltage et the amplifier output is signal from appearing at the collector of Q38. A single-
zero volts. channel output pulse will be generated by e delay mono-
stable, Q45 to Q49, when it recovers after being triggered
The amplifier output signal is presented to three voltage by a pulse through Q38; but Q67 must be cut off to
comparators, IC 5. IC 6, and IC 7. and to a pulse stretcher, permit the trigger pulse to reach the monostable. Only
Q17 through Q21. Comparators IC 5 and JC 6 form a con- when both IC 1D gate inputs are at the low state I- 0 VI
ventional single-channel pulse-height analyzer. Comparator will the trigger pulse be effective. This condition is
IC 7 and the stretcher perform a unique timing analysis. equivalent to the logic that permits the generation of e
single-channel output pulse and allows the timing circuit
5.2 Single Channel Analyzer to determine when the pulse will be generated. The sig
nal into IC ID from IC 1A. B, and C is low when
Lower Level comparator IC 6 accepts a bias level 6 from the Upper Level discriminator has not been triggered or when
IC 8B and the unity gein amplifier output. In the the front-panel selector switch is set for Integral mode
quiescent state, IC 6 output is z +1.5 V. When the signal operation. The signal into IC 1D from IC 2 is low
level exceeds the reference level B, the output switches only after the Lower Level discriminator has been trig-
rapidly to - -0.5 V and remains until the signal level drops gered. Thus, for the Integral mode of operation, e single-
below the reference level again. The comparator is a type channel output will be generated for each pulse that has an
~A710 with fast switching speed, and responds to signals amplitude greater than the setting of the Lower Level bias
as short es 200 ns. The negative transition of the output B. For Normal and Window modes e single-channel output
triggers two monostables; one forms a Lower Level output will be generated if the input pulse amplitude exceeds the
pulse through the rear-panel LL connector and the other is B reference level but does not exceed the A reference level
e temporary memory, to hold the response until an output (Upper Level). For each such ,input pulse with too large an
trigger occurs. amplitude, a permissive condition will exist for e short
time interval during the input pulse rise time, but the out-
Upper Level comparator IC 5 accepts a bias level A from put trigger. will not occur until a selected time after the
IC 8A and the output from the unity gain amplifier. Its input pulsepesk;so the false indication will not be sampled.
operation is identical to that of IC 6, discussed above, and
this comparator also triggers two monostabl,~; one forms 5.3 Reference Levels
an Upper Level output pulse and the other is a temporary
memory. A 3.bosition rear-panel switch selects External Strobe with
internal baseline control. External Baseline control with
The Lower Level output pulse is a NIM standard slow internal strobe, or Internal strobe and baseline. The BL
positive pulse formed when IC 46 and Q32 and Q33. a switch position selects external baseline control. which re-
monostable, receives the negative transistion of the IC 6 move-s the Lower Level control from the 455 internal cir-
 8

cuit and allows a 0- to -10-V signal to be accepted through The pulse stretcher accepts an attenuated signal from the
the rear-panel BNC connector for “se as the B reference un~ity gain amplifier, Q5 through Q9. Attenuation is
level after attenuation by a factor of 2. For either of the selected by the setting of the FRACTION switch on the
other two switch positions, reference level B is determined front panel. The attenuated positive portion of the signal
by the setting of the front-panel Lower Level control. passes through the stretcher amplifier, Q17 to Q21, which
charges C49 through D16 until the input signal peak occurs.
The Lower and Upper Level channels have a common -5-V This charge is maintained by the. Q23 stretcher gate,
reference level, regulated by DE. Lower Level adjustment opened at the proper time. The timing reference for
R39 selects a level between 0 and -5 V and applies it to comparator IC 7 is obtained from the charge on C49
unity gain amplifier Q56, Q59, Q60, Q61, and Q65. The through unity gain amplifier Q24 through 029.
unity gainamplifier hasa high input impedance for minimum
current drain from the DE reference source and for buffering During quiescent intewals the B reference level is applied
the potentiometer from all other circuitry. Upper Level es the timing reference input through Q15 and Ql6. When
adjustment R29 independently Selects a level between 0 and the input pulse amplitude exceeds the B reference level,
-5 V and applies it to its unity gain amplifier, 054 through comparator IC 7 switches from high to low. This coincides
Q57 and Q67. with the switching time of IC 2, which switches Qll off
and Q12 on. From this time until internal re%et,the timing
Following the unity gain amplifiers is the dual operational reference level is the stretched output through Q13 and
amplifier IC 8. The unity gain amplifier for the Lower Level Q14 and the input signal will logically exceed the timing
furnishes its output directly to IC 88 to be inverted for a reference level until it reaches a point on the decay of the
0 to +5-V reference level B. The input to IC 8A is input signal where them is a crosswei. At the time that the
determined by the Setting of the fmnt-panel mode selector input signal crosses through the timing reference level
and either is the independent Upper Level selection or is IC 7 resets for a high output, this transition being the timing
the sum of the Lower’ Level and the Upper Level adjust- signal. IC 7 remains in its high stati only momentarily if
ments. Its output is reference level A, applied to the Upper the input signal exceeds the B reference level. After the
Level comparator. signal decreases below the B reference level, IC 7 again
switches to high and this closes the stretcher gate to
For the Integral mode the Upper Level reference A is full- discharge C49.
rang@ 0 to +5 V. The Upper Level comparator triggers its
monostables in the normal manner to provide an Upper The timing signal from IC 7 is differentiated and inverted
Level output signal if the input amplitude exceeds reference by C56, Q34, and Q44 and is routed to parallel gate Q38
level A; the mode switch furnishes ground potential to OR and Q67: If the input signal has met the single-channel logic
gate IC 1D to cwercome and defeat any inhibit that is conditions, the gate will be opened and the timing signal
generated in IC IA. B, and C. triggers the delay generator, Q45 and Q46.

For the Normal mode the same circuit is used for the input 5.5 Single Channel Output
to the Upper Level comparator, and .the mode switch now
opens the ground circuit and permits the response in the The delay generator, Q45 and Q46, is a monostable with an
Upper Level to inhibit a single-channel output pulse. adjusted recovery period. The delay interval is selected
within the range of 0.1 through 1,l w with front-panel
For the 20% Window mode. reference B is determined by controls. The delay generator output triggers a current
the Setting of the Lower Level adjustment or by the Ex- switch, Q50 to Q53, to produce the NIM standard Fast
ternal Baseline input and is also applied through R61 into Negative output, and it also triggers a 0.5~j15 shaping
IC EA. The signal from the Upper Level adjustment is monostable. IC 4C. Q42. and Q43~for the NIM standard
applied through R62 and is summed with the signal from Slow Positive output.
the Lower Level adjustment at the input to IC EA. Thus
the reference level A is based on both adjustment levels, 5.6 External Strobe Operation
and the range of the Upper Level (Window) above the
Lower Level is 20% of the normal full range. The External Strobe mode can be selected by setting the
rear-panel switch at its STROBE position. A NIM standard
In the 100% Window mode a similar circuit connects the Slow PoSitive signal through the rear-panel BNC connector
Upper Level selection into ,the summed junction through will then determinewhen theoutput pulse will be generated.
R60; so it is not attenuated and the range is 100% of the For this mode of operation all of the internal logic operates
normal full range. in the same manner as for internal strobe, except that the
delay time of monostable Q45 and Q46 is extended and the
5.4 Internal Timing Signal external strobe will reset it prior to its natural recovery to
generate the output. The delay circuit recovery is extended
A timing signal is derived with two basic circuits, pulse to _ 50~s by setting the front-panel controls for maximum
stretcher Q17 through Q29 and fast comparator IC 7. delay. 11 /.Is.
 0

6. MAINTENANCE

6.1 Testing Performance steps will prove that the 455 is operating correctly as a
single-channel analyzer in all three basic modes. The steps
6.1.1 Introduotion. The following material will aid in may be repeated for other levels of pulse height and for
installing and checking out the 455. It consists of in- other logical combinations of Lower Level and Upper Level
formation on front panel controls, waveforms, test points, adjustments and for the NORM mode selection,
and output connectors.
6.2 Calibration Adjustments
6.1.2 Test Equipment. The following, or equivalent, test
equipment is needed: 6.2.1 Input Offset Adjustment. Potentiometer R12 is used
1. ORTEC 419 Pulse Generator to zero the dc offset at the amplifier input. R12 is the4th.
‘2. Tektronix 454 Series Oscilloscope potentiometer from the front of the printed circuit board.
3. loo-ohm BNC terminators Use TP4 to observe the dc offset. TP4 is the 2nd test
4. ORTEC 410 or 450 Amplifier point from the front panel near the top of the printed
5. Schematics and Block Diagrams for the 455 Timing circuit board. With no input signal applied,set R12 for zero
Single Channel Analyzer 72 mV at TP4.

6.1.3 Pmliminary Procedures. 6.2.2 Lower Level Zero Adjustment Potentiometer R52
adjusts the Lower Level Zero, and is the 2nd from the
1. Visually check module for possible damage due to front of the printed circuit board. Use the following steps:
shipment.
2. Plug module into Nuclear Standard Bin and Power 1. Connect the system shown in Figure 6-l.
Supply, e.g., ORTEC 401Al402A. and check for proper 2. Set the 455 for BLR LO, for the INT mode, and for a
mechanical alignment. Lower Level setting of 1000 dial divisions. Adjust the
3. Connect ac power to Bin. pulser for half-triggering, which should occur at about
4. Switch on ac power and check the dc power voltages et 10 v.
the test points on the 402A Power Supply control 3. Reduce the Lower Level control to 10 dial divisions and
panel. attenuate the pulser output bv 100; this should provide
100 mV to the 455 input. Adjust R52 for half-triggering
6.1.4 Testing the Single Channel Function of the Lower Level o”tput.
4. Repeat steps 2 and 3 to overcome any interaction of
1. Connect the direct output of the pulse generator to the controls.
scope trigger. Connect the attyuated output of the pulse
generator to the input of the Amplifier. Place all attenuator 6.2.3 Upper Level Zero Adjust. Zero adjustment for the
switches on the pulse generator to the OUT position except Upper Level controls uses R57, which is the 3rd potenti-
one switch, which should be a X10 switch. Adjust the pulse ometer from the front panel on the printed circuit board. Use
generator output and/or amplifier gain control to achieve the four steps of Section 6.2.2 with the 455 set for NORM
an amplifier output pulse height of approximately 10 V. mode. Observe the output through the UL connector on
the rear panel.
2. Connect the amplifier output to the 455 input. Set the
455 mode selector at I NT. Set the rear-panel 3.position
slide switch at INT and the BLR switch at DC. Adjust the
Lower Level dial to 5OO/lOOO divisions. There should now
be a” output from both the NEG and POS OUT connectors
on the 455. Turn the Lower Level control to read 1000,
then adjust the pulse height from the amplifier so the 455
half-triggers. Now set the X2 attenuator switch on the pulse
generator to reduce the pulse amplitude to half of the pre-
vious level. Reduce the 455 Lower Level control; the half-
trigger point should occur at - 500 dial divisions. Next,
reduce the Lower Level control to 400 dial divisions and
set the mode selector et 100% WIN. Starting with the

-6 i-t-
Upper Level control well above 100 dial divisions, reduce
the Upper Level toward zero; a half-trigger point should be
noted et about 100 dial divisions. Now switch the mode
selector for a 20% WIN setting. and advance the Upper
Level control until the 455 again half-triggers, which should
occw with the control at about 500 dial divisions. These Figure 6-l. Basic Intarconnections for Level Calibrations
 10

6.2.4 Timing Discriminator Sensitivity Adjustments. The 3. Set a X100 attenuation in the 419 for a 1OOmV input to
timing discriminator should trigger at an amplitude only the 455. Adjust the front-panel WALK ADJ control for
slightly less on the input signal than the Lower Level zero time shift for Xl00 attermation. Observe the time
trigger. After the Lower Level has been adjusted as shift for X5, X10. X20, and X60 attenuation. Note
discussed in Section 62.2, connect a sensitive dc milli- that the noise of the 410 Amplifier begins to dominate
ovoltmeter to pin 2 of IC 7. Adjust RlOO, at the front at the Xl00 attenuation level, causing a time dispersion
on the printed circuit board, for 20 to 30 mV on the meter. which makes the time centroid difficult to locate. The
dispersion will normally be approximately 4 ns.
6.3 Testing the 455 Timing Walk
6.4 Pmcadurs for Adjusting Wdk
A system for checking the walk of the 455 SCA output is
The ORTEC 455 Constant-Fraction Discriminator is ad-
shown in Figure 6-2. Adjust the pulsar’s Normalize control justed for minimum walk at the factory for the 10%
for 10 V at the 455 input. Set the Tektronix 464 Oscillc- fraction on unipolar signals. The Walk adj. control on the
scope 6 Sweep Mode to 6 Starts After Delay Time; set the front panel adjusts the dc level of the stretched signal as
Horizontal Display switch to 6 (Delayed Sweep); set the shown in Figure 6.3.
Delay Time to 0.2 #s and X10 Magnified, for 5 nsldivision:
adjust the Delay Time Multiplier control until the negative
signal appears at the center of the oscilloscope face. The
intensity should be near maximum.

1. Set a X10 attenuation in the 419 for a 1-V input to the

455. Adjust the front-panel WALK ADJ for zero walk
with X10 attenuation. Observe the walk for X2 and X5
attenuation.
2. Set a X50 attenuation in the 419 for a 200.mV input to
20011* Y
the 455. Readjust the front-panel control if necessary
for a zero time shift for the X50 attenuation. Observe
Figure 6.3. Waveforms for Proper Adjustment
the time shift for X5, X10. and X20 attenuation.
For smalL input signals, the timing signal will occur on the
leading edge of the input signal if the Walk adj. control is
Seth too far counterclockwise. This malfunction is shown in
Figure 6.4.

The condition in Figure 6.4 can be observed by triggering

the oscilloscope from the pulse generator and observing
either the positive or negative output on the oscilloscope.
RG 58
ForlO?&fraction mode anda 200.mVinput signal, turn the
Walk adj. clockwise until the output jumps from left
I , I I (Figure 6.4) to right (Figure 6.3). Do not operate the
leading edge mode as shown in Figure 6.4.

Since the 455 is dc-coupled, a small dc offset at the input

can cause the apparent malfunction shown in Figure 6.4. If
the user does not desire to ensure that the amplifier
Dscillpscopa Settings: Fine Gain - minimum providing the455 inputsignal isdc zeroed. he should always
Coarse Gain - 1 “se the dc-restoration mode on the 455.
Input Attenuator - Xl
410AmplifierSettings: Diff control - Double Delay Line
Integrate -Out
Input Polarity - Pas
419 Pulser Settings: X10 Attenuation - In
Polarity - + (Positive)
455 Settings: Lower Level - 10/1000
Mode - INT (Integral)
Ext/lnt/Strobe - INT (Internal)
Delay - minimum
BLR - DC

Fi(lun 6-2. 6ystem lntwwnnections for 455 Walk Test Figure 6.4. Waveforms for Improper Adjustment
 11

6.5. Factory Repair repaired instrument receive the same extensive quality
control tests that a new instrument receives. Please contact
The 455 may be retuked to ORTEC for repair service at our Customer Service Department at (615) 482.4411 for
nominal cost. Our standard procedure requires that each shipping instructions before returning this instrument.
 BIN/MODULE CONNECTOR PIN ASSIGNMENTS
FOR AEC STANDARD NUCLEAR INSTRUMENT MODULES
PER TID-20893

Pin Funnion Pin Fwwtion

1 +3 volts 23 Reserved
2 -3 volts 24 Reserved
3 Spare Bus 25 Reserved
4 Reserved Bus 26 Spare
5 Coaxial 27 Spare
6 Coaxial ‘28 +24 volts
7 Coaxial l 29 -24 volts
8 200 volts dc 30 spare Bus
9 spare 31 Spare
‘10 t6 volts~ 32 spare
*11 -3 VOb l 33 115 volts ac (Hot)
12 Reserved Bus f34 Power Return Ground
13 Spare **35 Reset (Scaler)
14 spare ‘“36 Gate
15 Reserved **37 Reset (Auxiliary)
l 16 +12 volts 38 Coaxial
l 17 -12 volts 39 Coaxial
18 Spare BUS 40 Coaxial
19 Reserved Bus ‘41 115voltsac (Neut.)
20 Spare *42 High Quality Ground
21 spare G Ground Guide Pin
22 Reserved

Pino marked (“1 are incallec and wired in ORTEC401 A and 401 S Modular Svstem Bins.
Pino marked I*) and (“) are installed and wired in EG&G/ORTEC-HEP MZSCVN and M350/N NIMBINS.
-455-020/ 0 @ m
-