🟩 1.

Number Systems & Binary Arithmetic

🔹 What is it?

It’s how a computer understands numbers (it only knows 0s and 1s).

Number System Base Digits Used

Binary 2 0, 1

Octal 8 0 to 7

Decimal 10 0 to 9

Hexadecimal 16 0–9, A–F

🔹 Important Concepts:

 Decimal ↔ Binary conversion

 1’s Complement: Flip 0→1 and 1→0

 2’s Complement: 1’s comp + 1 → used for subtraction

 Binary Addition/Subtraction

 Overflow detection: Happens if result is out of range

🟨 2. Logic Gates & Boolean Algebra

🔹 What is it?

Basic building blocks of digital electronics.

Gate Symbol Output Example

AND A·B 1 if A and B are 1

OR A+B 1 if A or B is 1

NOT A' Flips value

NAND (A·B)' Inverted AND

NOR (A+B)' Inverted OR

XOR A⊕B 1 if A≠B

🔹 K-Map:

 Used to simplify boolean expressions easily.

🔹 Flip-Flop:

 Smallest memory unit (1-bit)

 Stores 0 or 1

 Types: SR, D, JK, T

🔹 Registers:

 Group of flip-flops (e.g., 4-bit register stores 4 bits)

🔹 Counters:

 Used to count clock pulses

 e.g., 3-bit counter counts 0 to 7 (8 states)

🟥 4. CPU Organization & Addressing Modes

🔹 CPU has:

 ALU (Arithmetic Logic Unit): Does calculations

 Control Unit: Controls execution

 Registers: Temporary data storage

🔹 Addressing Modes (how to find data):

Mode Example

Immediate Value is inside the instruction

Direct Address is given directly

Indirect Address is inside a register

Indexed Base + index for arrays

🟪 5. Memory & Cache

🔹 Memory Hierarchy:

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Registers < Cache < RAM < HDD

Smaller → Faster → Costlier

🔹 Cache Mapping:

 Direct Mapping: One block to one line

 Associative Mapping: Any block to any line

 Set Associative: Grouped blocks

🟫 6. Input/Output (I/O), Interrupts, DMA

🔹 I/O Devices:

 Keyboard, mouse, printer — connected via buses

🔹 Interrupts:

 Signal to CPU to pause current task and handle urgent task

🔹 DMA (Direct Memory Access):

 Allows devices to access memory without CPU help → faster

🟧 7. Control Unit & Pipelining

🔹 Control Unit:

 Sends control signals to all CPU parts

 Two types:

o Hardwired: Faster but fixed

o Microprogrammed: Slower but flexible

🔹 Pipelining:

 Like a production line. Multiple instructions processed in parallel.

o IF (Fetch)

o ID (Decode)

o EX (Execute)

o MEM (Memory)
 o WB (Write Back)

🔹 Hazards:

 Data Hazard: Instructions depend on each other

 Control Hazard: Jump or branch instructions

 Structural Hazard: Hardware resource conflict

 "Addressing modes with examples"

🟩 8. Instruction Formats & Types

🔹 What is it?

Instructions tell CPU what operation to perform.

 Opcode (what to do)

 Operands (what to use)

🔹 Instruction formats:

Format Type Meaning

0-address No operands (e.g., stack machines)

1-address One operand + implicit accumulator

2-address Common in real CPUs

3-address Two source + one destination operand

🔹 Example:

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ADD R1, R2, R3 → R1 = R2 + R3

🟨 9. Micro-operations & Bus System

🔹 Micro-Operation:

Smallest operation done on data inside registers.

 E.g., R1 ← R2 + R3

🔹 Types:
  Register transfer: Move data

 Arithmetic: Add, subtract

 Logic: AND, OR

 Control: Enable signals

🔹 Bus:

Wires that transfer data between CPU, memory, I/O.

 Data Bus: Transfers data

 Address Bus: Sends memory address

 Control Bus: Sends control signals

🟦 10. Interrupts & DMA (Direct Memory Access)

🔹 Interrupt:

Special signal sent to CPU → current task paused → important task runs
Types:

 Hardware interrupt (printer, keyboard)

 Software interrupt (OS calls)

 Maskable / Non-maskable

🔹 DMA:

 A method where data is moved directly between memory and I/O, without CPU.

 Increases speed.

🟥 11. Memory Hierarchy & Mapping

🔹 Memory Levels:

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Registers < Cache < RAM < SSD/HDD

🔹 Cache Mapping:

 Direct Mapping: Each block has one place

 Set-Associative: Fixed sets (combo of above two)

🟪 12. RISC vs CISC

Feature RISC CISC

Full form Reduced Instruction Set Comp Complex Instruction Set Comp

Instruction Simple & small Complex & large

Execution One per cycle May take multiple cycles

Hardware Simpler More complex

Example ARM, MIPS x86, Intel

✅ For embedded systems, RISC is preferred (fast and low power).

🟫 13. Hazards in Pipelining

Hazard Type Meaning Example

Data hazard One instruction depends on another ADD R1, R2, R3 → SUB R4, R1, R5

Control hazard Happens after branch instructions IF R1==0 GOTO X

Structural Hardware resource conflict 2 instructions using same ALU

✅ Interview Q: How to solve data hazards?

🟧 14. Control Unit Design

🔹 Types:

Type Description

Hardwired Uses logic gates & flip-flops

Microprogrammed Uses ROM with microinstructions

✅ Hardwired is fast but fixed.

🟩 1. Registers & Counters

 Small, fast memory inside CPU.

 Used to store temporary data or instructions during execution.

 Examples:

o MAR (Memory Address Register)

o MDR (Memory Data Register)

o PC (Program Counter)

o IR (Instruction Register)

o Accumulator

🔹 Counters:

 A type of register that counts (increments or decrements) automatically.

 Used in:

o Program Counter

o Timing circuits

o Frequency division

🟨 2. Instruction Cycle & Addressing Modes

🔹 Instruction Cycle:

 The process through which a computer reads and executes an instruction.

 3 main phases:

1. Fetch (get instruction from memory)

2. Decode (understand the instruction)

3. Execute (perform the action)

🟦 3. Fetch-Decode-Execute Cycle (FDE)

Phase Description

Fetch CPU gets the next instruction (PC → IR)

Decode CU decodes what needs to be done

Execute ALU or memory performs the operation

✅ Happens for every instruction in CPU.

🟥 4. Addressing Modes

Used to locate operands (data) for instructions.

Mode Meaning Example

Immediate Data is inside instruction MOV A, #5 (A = 5)

Direct Address is given directly MOV A, 2000

Indirect Address is inside a register MOV A, @R0

Indexed Use base + index MOV A, [R1 + i]

✅ Interview Tip: Know examples and use-cases!

🟪 5. Memory Organization

🔹 Memory Types:

Type Description

RAM Volatile, Read/Write

ROM Non-volatile, Read-only

Cache Very fast, between CPU and RAM

🔹 Cache Mapping:

Mapping Type Description

Direct 1 block → 1 cache line (simple)

Associative Any block → Any cache line

Set-associative Cache divided into sets

✅ Cache helps CPU access data faster!

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Registers < Cache < RAM < SSD < HDD

 Speed ↓ as you go down

 Size ↑

 Cost per bit ↓

✅ Principle of Locality helps CPU predict what data you’ll need next.

🟧 7. Hit/Miss & Access Time

🔹 Hit: Data found in cache

🔹 Miss: Data NOT in cache → load from lower memory

Access time = Time taken to read/write data

✅ Formula:
Effective Access Time (EAT) =

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Hit Ratio × Cache time + Miss Ratio × Main memory time

🟥 8. CPU Organization & Control Unit

🔹 CPU has:

 ALU: Arithmetic/Logic operations

 Control Unit (CU): Controls all operations

 Registers: Small internal memory

🟨 9. ALU & Register Transfer

 ALU performs:

o Add, Subtract, AND, OR, Shift

o Example: R1 ← R2 + R3

✅ Registers are used to store intermediate results.

🟦 10. Hardwired vs Microprogrammed Control

Type Hardwired Microprogrammed

Speed Faster Slower

Flexibility Not flexible Easy to modify

Control logic Built with gates Stored in ROM (firmware)

Used in RISC processors CISC processors

✅ Microprogrammed is easier to update or fix.

🟩 11. Pipelining & Hazards

🔹 Pipelining:

 Like a factory assembly line

 Multiple instructions processed in parallel stages:

1. IF: Instruction Fetch

2. ID: Instruction Decode

3. EX: Execute

4. MEM: Memory access

5. WB: Write Back

✅ Increases instruction throughput!

🔻 Hazards in Pipelining

Type Cause

Data Hazard Instruction depends on previous one

Control Hazard Branching (like if)

Structural Hardware resource conflict

✅ Solutions:

 Forwarding, Stalling, Branch prediction

🔚 Summary Table (for Revision)

Concept Key Point

Registers Small fast storage in CPU

Counters Used to count clock pulses

Instruction Cycle Fetch → Decode → Execute

Addressing Modes Ways to locate operands

Cache Mapping Direct / Associative / Set-Assoc.

Memory Hierarchy Register → Cache → RAM → HDD

Hit/Miss Data found/missed in cache

Control Unit Types Hardwired vs Microprogrammed

Pipelining Parallel instruction execution

Hazards Data/Control/Structural conflicts

1. Pipeline Hazards – Problems in pipelining execution

🔹 A. Data Hazard

Occurs when one instruction depends on the result of a previous instruction.

🧠 Example:

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ADD R1, R2, R3

SUB R4, R1, R5 ← Needs R1 before it's ready

✅ Solution:

 Forwarding (pass result early)

🔹 B. Control Hazard

Occurs with branch or jump instructions (like if/else) → CPU may not know where to go
next.

✅ Solution:

 Branch Prediction

 Branch Delay Slots

🔹 C. Structural Hazard

Occurs when two instructions need the same hardware at the same time.

🧠 Example: ALU being used by 2 instructions

✅ Solution:

 Use duplicated hardware

 Organize instruction scheduling

🟩 2. I/O Organization

This is how input/output devices (keyboard, printer, etc.) communicate with CPU and
memory.

🔹 Two main methods:

Type Description

Programmed I/O CPU checks device status constantly (polling)

Interrupt-driven I/O Device interrupts CPU when ready

DMA (Direct Memory Access) Device talks directly to memory without CPU

🟨 3. DMA (Direct Memory Access)

🔹 What is it?

Allows I/O devices to transfer data directly to/from memory without involving CPU.
✅ Faster than Programmed or Interrupt-driven I/O.

🧠 Example:
Copying files from pen drive → DMA handles the memory transfer.

🔹 Steps in DMA:

1. CPU gives memory address and count to DMA controller

2. DMA handles full transfer

3. Sends interrupt to CPU after completion

✅ CPU is free to do other tasks in parallel.

🟦 4. Interrupts

🔹 What is it?

Signal from a device telling CPU to stop and do something urgent.

🔹 Types:

Type Example/Trigger

Hardware From external device (keyboard press)

Software From program (division by zero)

Maskable Can be ignored by CPU

Non-maskable Cannot be ignored (critical)

🔹 Working:

1. Device sends interrupt signal

2. CPU pauses current task

3. Executes ISR (Interrupt Service Routine)

4. Returns to original task

🟥 5. I/O Mapped I/O vs Memory Mapped I/O

Feature I/O Mapped I/O Memory Mapped I/O

Address Space Separate I/O address space Uses same memory space as RAM
Feature I/O Mapped I/O Memory Mapped I/O

Instructions Used Special instructions like IN, OUT Regular instructions (MOV, ADD)

Size of Addressing Limited (usually 256 ports) Large (same as memory address space)

Data Transfer Only to/from I/O ports To/from any memory or I/O location

✅ Memory-Mapped I/O is used in modern systems, as it's more flexible.

🔚 Summary – Super Easy Revision Table

Concept Key Point

Data Hazard Depends on previous instruction → use forwarding

Control Hazard Due to jumps/branches → use branch prediction

Structural Hazard Hardware conflict → delay or duplicate hardware

Programmed I/O CPU checks device (polling)

Interrupt-driven I/O Device interrupts CPU when ready

DMA Fastest → device ↔ memory without CPU

Interrupt Types Hardware/Software, Maskable/Non-maskable

I/O Mapped I/O Separate address space for I/O

Memory Mapped I/O I/O shares memory space → flexible, modern