Peripheral Controller Chips

❖ Intelhas developed several peripheral controller

chips designed to support the 8086 processor
family such as:

➢ the 8255A Programmable Peripheral Interface (PPI),

➢ the 8254 Programmable Interval Timer (PIT),
➢ the 8251 Programmable Communication Interface,
➢ the 8279 Keyboard and display Interface,
➢ the 8259 Programmable Interrupt Controller (PIC).

❖ The objective is to provide a complete I/O

interface in one chip.
 8255A Programmable
Peripheral Interface (PPI)
❖ Intel 8255A is a general purpose parallel I/O interface.

❖ The peripheral devices are slower than the microprocessor. PPI makes
an inter-relation between microprocessor and peripheral devices.

❖ It provides three I/O port (Port A, Port B and Port C)

 Description of 8255A Internal Block Diagram
Data Bus Buffer
•This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data
bus.
•Data is transmitted or received by the buffer upon execution of input or output instructions
by the CPU.
•Control words and status information are also transferred through the data bus buffer.
Read/Write Control Logic
The function of this block is to manage all of the internal and external transfers of both Data
and Control or Status words.
(CS) Chip Select. A "low" on this input pin enables the communication between the 8255
and the CPU.
(RD) Read. A "low" on this input pin enables 8255 to send the data or status information to
the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR) Write. A "low" on this input pin enables the CPU to write data or control words into
the 8255.
(A0 and A1) These input signals, control the selection of one of the three ports or the
control word register.

(RESET) Reset. A "high" on this input initializes the control

register to 9Bh and all ports (A, B, C) are set to the input mode.
Description of 8255A Internal Block Diagram (Continued)
Group A and Group B Controls
Each of the Control blocks (Group A and Group B) accepts "commands" from the CPU
as "control word" and configure the ports (Port A, Port B and Port C) accordingly.
Port A and upper 4 bits of Port C are controlled by Group A Port B and lower part of Port
C are controlled by Group B
Ports A, B, and C
The 8255 has three 8 bit I/O ports and each one can be connected to the physical lines
of an external device. All can be configured to a wide variety of functional
characteristics by the system software .These ports are labeled as PA0-PA7 (PortA),
PB0-PB7 (PortB) and PC0-PC7 (PortC).
GND (Ground) and Vcc

Summary of 8255A Pins

Port Pins: 24 ( Port A = 8,Port B =8,Port C =8)
Control Pins: 6 (RD, WR, CS, RESET, A1, A0)
Data Lines: 8
Power Supply: 2 (VCC, GND)
Total 40 pins
Handshaking
The making of inter relation between slower peripheral device and
microprocessor is called handshaking.

Handshaking Signal
Before making the inter-relation between peripheral device and
microprocessor the PPI send some signals to microprocessor and peripheral
device to perform the process, these signals are called handshaking signal.
8255-based devices that perform handshaking support following
handshaking signals:
Read Operation
STB goes low indicates that data are loads into port latch.
IBF Becomes high (at high to low transition of STB) indicates that input latch
contains data
INTR Becomes high (at low to high transition of STB) uP goes interrupt
subroutine to read data. RD becomes low.
IBF becomes low when read complete, RD becomes high and IBF goes low.
IBF low means input latch has no data (Read complete)
Write Operation
Programming 8255A
Modes of Operation
8255 can be configured in two modes
•BSR (Bit Set Reset) Mode
•I/O (Input-Output) Mode: Mode 0, Mode 1 and Mode 2 Modes are configured by
Control Word
Control Word
A Control Word is an 8-bit data that stored in control register. Control Words are two
types: (a) BSR Control Word (b) Mode definition Control Word
BSR Mode (Configured by Bit Set-Reset Control Word)
•If bit 7 of control word is a logic 0 then 8255 will be configured as BSR (Bit Set
Rest) mode.
•In this mode we can set or reset the pins of port C

N.B: Don’t Cares are

Generally set as zero.

Problems: (a) Write a control word to reset PC5. (Ans: 0AH)

(b) Write a Control Word to Set PC2. (Ans: 05H)
I/O Mode (Configured by Mode definition CR)
•If bit 7 of the control word is a logical 1 then the 8255 will be configured as I/O mode.
•I/O mode consists of Mode0, Mode1 and Mode2.
Mode 0
•Port A works as simple input or output without handshaking.
•Port B works as simple input or output without handshaking.
•Port C can be used together as an additional 8 bit port or they can be used
individually as two 4-bit ports.
•When used as outputs, the Port C lines can be individually set or reset by sending
a special control word to the control register address.
I/O Mode (Cont.)
Mode 1
•Used for handshake input/output operation.
•Port B is initialized in mode 1 for either input or output, Pins PC0, PC1 and PC2
function as handshake lines.
•Port A can also be configured as input or output in mode 1. But handshake
signal pins are not same for input and output mode as like Port B.
•If port A is initialized in mode 1 as handshake input port, then pins PC3, PC4
and PC5 function as handshake signals. (PC6 and PC7 are available for using as
input lines or output lines)
•If port A is initialized as handshake output port, then PC3, PC6 and PC7 function as
handshake signals. (PC4 and PC5 are available for using as input or output lines)
I/O Mode (Cont.)
Mode 2
•Only port A can be initialized in mode 2.
•In mode 2, port A can be used for “bi-directional handshake” data transfer i.e.
data can be input or output on the same eight lines.
•Pins PC3, PC4, PC5, PC6, PC7 used as handshake lines for port A.
•Port B is operating in either mode 0 or mode 1.
•If port B is in mode 0, then PC0, PC1 and PC2 used for I/O.
•If port B is in mode 1, then PC0, PC1 and PC2 used as handshake lines.
A

A
I/O Mode (Cont.)
Configuring I/O Mode
I/O Mode is configured by Mode Definition Control Word
 Problems
Problem1: Write a control word to configure port A as input port in mode 0 and port B
in mode 1 as output port.
Solution:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 1 0 0
The control word is 94H.
N.B. D0 and D3 are low if port C is used as output or if unused.
Problem 2: A control word is given CW=CDH. Explain the conditions of ports of 8255A.
Solution:
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 1 1 0 1

D7=1; I/O Mode.

D6=1 and D5=0; Port A is in Mode 2.
D4=0; Port A is output port
D3=1; Port C (Upper) is input port.
D2=1; Port B is in Mode 1.
D1=0; Port B is output Port.
D0=0; Port C (Lower) is input port.
Q3: Configure Port A in Mode 2, Port B as o/p in mode 1.
 Problems
Problem 3: Configure Port A in Mode 2, Port B as o/p in mode 1.
Solution: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 1 0 X
Control word is C4H / C5H….. etc
Problem 4: Write an 8086 assembly language procedure to read an ASCII character
from a keyboard via PORT A of an 8255 PPI when PORT C bit PC4 is strobed low.
Assume a base address of 20H.
Problem 5: Write an 8086 assembly language procedure to send an ASCII
character, stored in register AH, to a printer via PORT B of an 8255 PPI when
PORTC bit PCO is strobed low and after an active low acknowledge signal is
detected on PORT C bit PC5 from the printer. Assume a base address of 60H.

Solution:
PORTB EQU 61H
PORTC EQU 62H
CONTROL EQU 63H
PRINT PROC NEAR
MOV AL, 88H ; 1000 1000
OUT CONTROL, AL;
PRINT1:
IN AL, PORTC ; Is Acknowledge PC5 Low?
TEST AL, 20H ; 0010 0000
JNZ PRINT1
MOV AL, FEH ; 1111 1110
OUT PORTC, AL ; strobe output PC0
MOV AL, AH ; Send character
OUT PORTB, AL;
RET
PRINT ENDP
Problem 6: An 8086-8255 based microcomputer is required to drive an LED
connected to bit 2 of Port B based on two switch inputs connected to bit 6 and 7
of port A. If both switches are either high or low, LED will turn on ; otherwise,
it will remain OFF. Assume base address of 60H . Write an 8086 assembly
language program to accomplish this.

Solution:
PORTA EQU 60H
PORTB EQU 61H
CONTR EQU 63H
MOV AL, 10010000B; Configure Port A as input and Port B as output.
OUT CNTRL, AL;
MAIN : IN AL, PORTA;
AND AL, 11000000B;
JPE LEADON; (JPE= Jump if parity even, p=1)
MOV AL, 00H;
OUT PORTB, AL;
JMP MAIN;
LEDON : MOV AL, 00000100B;
OUT PORTB, AL;
JMP MAIN;
Problem 7: Figure shows an 8255A interfaced with 8086 microprocessor.
Perform the following-
(a) Identify the Port Address.
(b) Identify the Mode 0 control word to configure Port A and Port CU as output
ports and Port B and Port CL as input ports.
(c) Write a program to read the DIP switches and display the reading from Port B
at Port A, and from Port CL at Port CU.
PPIA EQU 00F8H
PPIB EQU 00F9H
PPIC EQU 00FAH
PPICR EQU 00FBH
MOV AL, 83H
OUT PPICR , AL
IN AL, PPIB
OUT PPIA, AL
IN AL, PPIC
AND AL, 0FH
MOV CL, 04H MOV CL, 04H
ROL AL, CL SHL AL, CL
OUT PPIC, AL OUT PPIC, AL
HLT HLT
Problem 8:
Write a BSR control word subroutine to set bit PC7 and PC3 and reset them after
10ms. Use the previous schematic (Figure of problem 7). Also write the delay
procedure considering the processor clock at 5 MHz .
Solution:
BSR Control Word:

Address of control register: 8003H (See previous problem)

Duration of 1 clock pulse= (1/5MHz) = 200 ns
So, for 10ms we have to count = (10ms/200ns) = 50,000
Subroutine:
CALL DELAY DELAY PROC NEAR
PPICR EQU 8003H
MOV AL, 06H MOV CX, 50,000
BSR: MOV AL, 0FH
OUT PPICR, AL HERE: LOOP HERE
OUT PPICR, AL
MOV AL, 0EH RET
MOV AL, 07H
OUT PPICR, AL DELAY ENDP
OUT PPICR, AL
RET
Assignment: A 8086-8255A based system is given in fig. The Port A of 8255A
is connected with a 7-segment display. Write an assembly language program to
display the numbers 1,3,5,7,9 repeatedly
Programmable Interval
Timer - 8254
❖ The Intel 8254 is a counter/timer device designed to solve the common timing
control problems in microcomputer system design.
❖It provides three independent 16-bit counters, each capable of handling clock
inputs up to 10 MHz.
❖ All modes are software programmable.
❖The 8254 is a superset of the 8253.

Pin Diagram of 8254

0
0
0

Block Diagram of 8254

Application
Some of the other counter/timer functions common to microcomputers
which can be implemented with the 8254 are:
✓Real time clock
✓Event-counter
✓Digital one-shot
✓Programmable rate generator
✓Square wave generator
✓Binary rate multiplier
✓Complex waveform generator
✓Complex motor controller
8254 System Interface
✓ It includes three 16-bit counters that can work independently in 6 different
modes.
✓It is packaged in a 24-pin DIP(Dual in-line package) and requires +5V
power supply.
✓ It can count either in binary or BCD.
✓ It’s counters can operate at a maximum frequency of 10 MHz

Programming the 8254

Counters are programmed by writing a Control Word and then an initial count.
The Control Words are written into the Control Word Register, which is
selected when A1 A0 = 11. The Control Word itself specifies which Counter is
being programmed.
Read/Write operation Summary
Six Different Modes
Mode 0: Interrupt on Terminal Count
Mode 1: Hardware Re-triggerable One-shot
Mode 2: Rate Generator
Mode 3: Square Wave Mode
Mode 4: Software Triggered Mode
Mode 5: Hardware Triggered Mode (Re-triggerable).
 Mode 0: Interrupt on terminal count

* N stands for an
undefined count.

✓Mode 0 is typically used for event counting.

✓After the Control Word is written, OUT is initially low, and will remain low
until the Counter reaches zero. OUT then goes high and remains high until a
new count or a new Mode 0 Control Word is written into the Counter.
✓GATE =1 enables counting; GATE = 0 disables counting.
 Mode 1: Hardware Retriggerable One-Shot.

✓OUT is initially (after loading CW) high. Also remain high when count
is written.
✓When gate is triggered, OUT goes low and will remain low until the
Counter reaches zero. On completion of count OUT goes high again.
 Mode 2: RATE GENERATOR
✓Allows the counter to generate a series of continuous pulses that are
one clock pulse wide.
✓The separation between pulses is determined by the count.
✓If count N is loaded then, output will remain high for (N-1) clock
period and low for 1 clock period

✓In mode 2, a COUNT of 1 is illegal.

 Mode 3: Square Wave Mode.
✓Generates a continuous square wave at the out connection
✓Mode 3 is similar to Mode 2 except for the duty cycle of OUT.
✓If the count (N) is even, the output is high for one half (N/2) of the count
and low for one half (N/2) of the count.
✓If the count (N) is odd, the output is high for one clocking period longer
than it is low i.e. high for (N+1)/2 clock pulses and low for (N-1)/2 clock
pulses.
 Mode 4: Software Triggered One-shot.
✓Allows the counter to produce a single pulse at the output

✓If count of N is loaded, then OUT will be high for N clock cycles and low
for one clock cycle at the end.
✓The cycle does not begin until the counter is loaded again.
 Mode 5: Hardware Triggered Mode.

✓A hardware triggered one-shot that function as mode 4, except that it is

started by a trigger pulse on the G pin instead of by software.
✓When the GATE pulse is triggered from low to high the count begins. At
the end of the count OUT goes low for one clock period.
 Problem 1
(a) Identify the port address of the control register and counter 2 in figure.
(b) Write a subroutine to initialize counter 2 in mode 0 with a count of 50,000.
Solution (a):

Addres
A15 A14 A13 A12 A11…………A5 A4 A3 A2 A1 A0 s

1 0 0 0 ………………… 0 0 0 0 0 8000H Counter 0

1 0 0 0 …………………. 0 0 0 0 1 8001H Counter 1

1 0 0 0 …………………. 0 0 0 1 0 8002H Counter 2

1 0 0 0 …………………. 0 0 0 1 1 8003H Control

Register

Address of counter 2 = 8002H

Address of control register = 8003H
Solution (b):
We have to initialize counter 2 in Mode0.
Count= (50,000)10 = C350H
Control Word to initialize counter 2 in mode 0 and to load 16-bit count:
1 0 1 1 0 0 0 0 B0H
Control
Load 16 bit Count in Word
Counter 2 count Mode 0 binary

Subroutine:
COUNTER PROC NEAR
CNT2 EQU 8002H
CNTR EQU 8003H
MOV AL, B0H
OUT CNTR, AL
MOV AL, 50H
OUT CNTR2, AL
MOV AL, C3H
OUT CNTR2, AL
COUNTER ENDP
 Problem 2
Write instructions to generate a pulse in every 50 μs later from counter 0.
Consider the figure of problem1.

Solution
To generate a pulse in every 50 μs later, we should initialize counter 0 in mode
2. Gate 0 should be high.

Control Word
0 0 0 1 0 1 0 0 14H
Counter 0 Load least significant byte Mode 2 Count in Control Word
only binary

Instructions:

CNT0 EQU 8000H OUT CNTR, AL

CNTR EQU 8003H MOV AL, 64H
MOV AL, 14H OUT CNT0, AL
 0 1 1 1 0 1 1 0 76H
Control Word
Counter 1 Load both byte Mode 3 Count in binary

CNT1 EQU 8001H

CNTR EQU 8003H
MOV AL, 76H Gate should be maintained at logic 1 always
OUT CNTR, AL (GATE =1 enables counting; GATE =0 disables
MOV AL, D0H counting.
OUT CNT1, AL
MOV AL, 07H
OUT CNT1, AL
Problem 4
Write a subroutine to generate an interrupt every 1sec. Consider the figure of
problem1.
Solution
To obtain a pulse every 1 sec, the count should be 2 × 26, which is too large
for one 16-bit counter. We can divide this counter as follows:
Counter 1 [gate pulse=2 MHz]--- Mode 2 ----- Count 50,000 (C350H)
Counter 2 [gate pulse=out1 (output of counter 1)]---- Mode 2 ---- Count 40
(28H)
So, finally we get 50,000 × 40 = 2 × 106 desired output.

Control word:
Counter 1= 01 11 010 0 = 74H
Counter 2= 10 01 010 0 = 94H
OUT CNTR, AL
Subroutine: MOV AL, 50H
INTRP PROC NEAR OUT CNT1, AL
CNT1 EQU 8001 H MOV AL, C3H
CNT2 EQU 8002H OUT CNT1, AL
CNTR EQU 8003H MOV AL, 28H
MOV AL, 74H OUT CNT2, AL
OUT CNTR, AL RET
MOV AL, 94H INTRP ENDP
 8251 -USART
Serial I/O - Programmable Communication Interface
 Data Communications
• Data transfer between two entities.

• Data communications refers to the ability of one

computer to exchange data with another computer
or a peripheral.

• Physically, the data communication path may be a

short, 5 to 10 feet ribbon cable connecting a
microcomputer and parallel printer; or it might be
a high speed telecommunications port connecting
two computers thousands of miles apart.
 Data Communications
Classification:
• Serial Communication
• Parallel Communication
Types of Transmission
 Transmission Modes

• Two types of serial data communications are

widely used
– Synchronous communications
– Asynchronous communications
Pin Diagram of USART 8251
Block Diagram of USART 8251
 Examples
• What is the data rate in bits/sec and character rate if the bit
time is 3.33 ms
– Bit rate = 1 / 3.33 ms = 300 bits/sec
– 11 x 3.33 ms = 36.63 ms required to transmit a character so
character rate = 1/36.63 ms = 27.3 char/sec
• Modems typically transmit data over the telephone
network at 9600, 14400, 28800 or 56K bps.
• Ex: If 1 MByte file is to be transmitted to another computer
using a modem calculate the transmission time
– 9600 bps: 1048576x10/ 9600 bits/sec = 1092 s = 18 minutes and
12 sec
– 28800 bps: 364 s = 6 minutes and 4 sec
Building a Serial I/O port
Receiver- Flowchart
8279 KEYBOARD AND DISPLAY
INTERFACING
 8279 contains the following features:
 Simultaneous and independent scanning of a
keyboard and refresh of a display,
 significantly offloading these functions from the
microprocessor.
Keyboard section:
 8-character Keyboard FIFO
 2-Key Lockout or N-key Rollover with Contact Debounce
 Interrupt Output on Key Entry
 Programmable Keyboard Scan & Debounce rates

Display Section:
 Dual 8- or 16-Numeric Display
 Single 16-Character Display
 Right or Left Entry 16-Byte Display RAM with address auto
increment
 Programmable display refresh rate
➢ It is designed by Intel
➢ It is support 64 contact key matrix with two more keys “CONTROL” and
“SHIFT”
➢ It provides 3 operating modes
1.Scanned keyboard mode 2.Scanned sensor matrix mode 3.Strobed Input mode.
➢ Ithas inbuilt debounce key .
➢It provides 16 byte display RAM to display 16 digits and interfacing 16 digits.
➢It provides two output modes:
1.Left entry (Typewriter type).
2.Right entry (Calculator type).
➢The interrupt output of 8279 can be used to tell CPU that the key press is
detected, this eliminates the need of software polling.
Pin Configuration of 8279
 KEYBOARD SECTION
◼ Has eight lines: RL0 to RL7 + two additional lines:
CNTL/STB; connected to 8 columns of the keyboard
◼ 2 modes:
◼ 2 key lockout: if two keys are pressed simultaneously only 1st key is
recognized
◼ N-key rollover: simultaneous keys are recognized and their codes are
stored in internal buffer.
◼ Keyboard section also includes 8X8 FIFO which further
consists of eight registers that can store 8 keyboard entries.
 SCAN SECTION
◼ Has scan counter and four scan lines: SL0 to
SL3
◼ These are decoded using 4X16 decoder
◼ Further these 16 lines are connected to rows
of matrix keyboard and digital drivers of
multiplexed display
 DISPLAY SECTION
◼ Has 8 output lines divided into 2 groups A0 to
A3 and B0 to B3
◼ These lines can be used as a group of 8 lines
or 2 groups of 4 lines each in conjunction to
scan lines for display
◼ Display can be blanked by BD line
◼ Includes 16X8 display RAM
◼ MPU can read or write into these registers
 MPU INTERFACE SECTION
◼ Includes 8 bi-directional Data lines (DB0-
DB7), one Interrupt Request (IRQ) and six
lines for interfacing, including buffer add line
A0
◼ When A0 is high – control word
◼ When A0 is low – signals are interrupted and
they act as data lines
◼ IRQ goes high whenever data entries are
stored in FIFO
ENCODED SCAN DECODED SCAN
MOV AL, 90H
OUT 31H, AL
MOV AL, 93H
OUT 30H, AL
MOV AL,
B5H
OUT 30H, AL
Operating modes
 It is two types,
1. Input modes.
2. Display modes.
INPUT MODES:
➢ It is basically 3 types,
1. Scanned keyboard.
2. Scanned sensor matrix.
3. Strobed mode.
SCANNED KEYBOARD:
Key board can be scanned in two ways.
1.Encoded Scan 2.Decoded Scan.
ENCODED SCAN:
➢ In this scan, scan lines (SL2-SL0) are decoded
externally to provide 8 scan lines.
➢ Additionally it provides 8 return lines.
➢ So the size of matrix keyboard is 8*8 (i.e Scan *
Return)=64.
➢ When the key is pressed , it is stored the status of
return lines , Scan lines ,SHIFT and CNTL/STB
keys into FIFO RAM.
➢ The Scanned keyboard structure is,

D7 D6 D5 D4 D3 D2 D1 D0
CNTL SHIFT SCAN RETURN
Example:
➢ Find the key code for given condition
below:
CNTL/STB SHIFT keys are open.
The pressed keys are to scan lines 2 and
return lines 4.
SOLUTION:
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 1 0 1 0 0

➢ CNTL=1
➢ SHIFT=1
➢ Scan mode=010 (Scan line 2)
➢ Return mode=100 (Return line
4)
➢ Key code =D4 H
DECODED SCAN:
➢ In this mode ,internal decoder decodes the
least significant bits of scan lines (SC3-SC0).
➢ That is provide the four combination such as
1110,1101,1011 and 0111.
➢ So the maximum size of keyboard is
8*4=32.
➢ The key code is similar to encoded code ,
only bit 5 (B5) is always zero.
2-KEY LOCKOUT:
➢ In this mode, the two key depression is not
allowed.
➢ When any key is depressed, the debounce
logic is set and 8279 checks for any key
depress next two scans.
➢ Three possible condition to avoid debouncing:
➢ Condition 1:
➢ If other key depression is not found during
next two scan, it is a single key is depressed
.Then the status of key code is entered into
FIFO RAM along with the status of CNTL and
SHIFT lines
➢ If FIFO RAM is empty , The CPU is entry the
data.
➢ If FIFO RAM is full , The CPU does not entry
the data.
Condition 2:
➢ If any other key depress is encountered ,
no entry to the FIFO can occur.
➢ When the key is released after that only
Entry will be allowed.
Condition3:
➢ If the two key is pressed in simultaneously
in a debounce cycle, both depression is not
considered.
 N-KEY ROLLOVER:
➢ Each key is depression is treated as
independently from all others.
SCANNED SENSOR MATRIX:
➢ In this mode , image of the sensor matrix
is kept in the sensor RAM.
➢ The status of sensor switches are input
directly to the sensor RAM.
➢ 8279 scans row one by one and store the
status of each row in the corresponding
memory location.
➢ STROBED INPUT MODE:
➢ The data is entered from Returned lines.
Display modes:
 It is basically two types,
1. Left entry (Type writer mode).
2. Right entry (Calculator mode).
LEFT ENTRY:
➢ In this mode , 8279 display characters
from left to right.
➢ Like a typewriter.
AUTOINCREMENT IN LEFT ENTRY:
➢ In left entry mode , Autoincrement flag
is set after each operation display RAM
address is incremented.
RIGHT ENTRY:
➢ In this mode , 8279 display characters
from Right to left.
➢ Like a Calculator.
AUTOINCREMENT IN RIGHT ENTRY:
➢ In right entry mode , Auto increment
flag is set after each operation display
RAM address is incremented.
INTERRUPT &
PIC 8259
Interrupt :
INTERRUPTS
An interrupt is an event which informs the CPU that its service
(action) is needed.
The process starts from the I/O
device
The process is asynchronous.
Classification of Interrupts
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected)
Non-Maskable Interrupts (Can not be delayed or Rejected)

Interrupts can also be classified into:

Vectored (the address of the service routine is hard-wired)
Non-vectored (the address of the service routine needs to be supplied
externally by the device)
 Basic Procedure for Processing
Interrupts
When an interrupt is executed, the mp:
❖ Ffinishes executing its current instruction (if any).
❖ Saves (PUSH) the flag register, IP and CS register in
the stack.
❖ Goes to a fixed memory location.
❖ Reads the address of the associated ISR.
❖ Jumps to that address and executes the ISR.
❖ Gets (PULL) the flag register, CS:IP register from the
stack.
❖ Continues executing the previous job (if any).
8086 INTERRUPT CATAGORIES

Interrupt can divide to five groups:

i. Hardware interrupt

ii. Non-maskable interrupt

iii. Software interrupt

iv. Internal interrupt

v. Reset
 In the 8086 there are a total of 256 interrupts (or interrupt types):
-INT 00H
-INT 01H
-……….
-INT FFH

❖For every interrupt there must be a program associated with it .

❖This program is called Interrupt Service Routine (ISR) .
❖ It is also called an interrupt handler.
❖ But where the interrupt handler.
-- In the Interrupt Vector Table (IVT).
 Type 0 interrupts: This interrupt is also known as the divide by zero
interrupt. For cases where the quotient becomes particularly large to be
placed / adjusted an error might occur.

Type 1 interrupts: This is also known as the single step interrupt. This type
of interrupt is primarily used for debugging purposes in assembly language.

Type 2 interrupts: also known as the non-maskable NMI interrupts. These

type of interrupts are used for emergency scenarios such as power failure.

Type 3 interrupts: These type of interrupts are also known as breakpoint

interrupts. When this interrupt occurs a program would execute up to its
break point.

Type 4 interrupts: Also known as overflow interrupts is generally existent

after an arithmetic operation was performed.
Programmable Interrupt Controller 8259
PIC 8259

The Programmable Interrupt Controller (PlC)

functions as an overall manager in an Interrupt-
Driven system.

It accepts requests from the peripheral equipment,

determines which of the incoming requests is of
the highest importance (priority), ascertains
whether the incoming request has a higher priority
value than the level currently being serviced, and
issues an interrupt to the CPU based on this
determination.
CONT’D…

Each peripheral device or structure usually has a

special program or “routine” that is associated with
its specific functional or operational requirements
this is referred to as a “service routine”.

The PlC, after issuing an interrupt to the CPU,

must somehow input information into the CPU that
can point (vector) the Program Counter to the
service routine associated with the requesting
device
CONT’D…

The PIC manages eight levels of requests and has

built-in features for expandability to other PIC (up
to 64 levels). It is programmed by system software
as an I/O peripheral.

The priority modes can be changed or

reconfigured dynamically at any time during main
program operation .
FUNCTIONAL BLOCK DIAGRAM DESCRIPTION

Interrupt Request Register (IRR) and In-Service

Register (ISR)

The interrupts at the IR input lines are

handled by two registers in cascade, the Interrupt
Request Register (lRR) and the In- Service
Register (lSR). The IRR is used to indicate all the
interrupt levels which are requesting service, and
the ISR is used to store all the interrupt levels
which are currently being serviced.
CONT’D…

Priority Resolver

This logic block determines the

priorities of the bits set in the lRR. The
highest priority is selected and strobed into
the corresponding bit of the lSR during the
INTA sequence.
CONT’D…

Interrupt Mask Register (IMR)

The lMR stores the bits which

disable the interrupt lines to be masked. The
IMR operates on the output of the IRR.
Masking of a higher priority input will not
affect the interrupt request lines of lower
priority.
CONT’D

Data Bus Buffer

This 3-state, bidirectional 8-bit buffer is

used to interface the PIC to the System Data Bus.
Control words and status information are
transferred through the Data Bus Buffer.
CONT’D…
 Read/Write Control Logic

The function of this block is to accept output commands from

the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers which
store the various control formats for device operation.

This function block also allows the status of the PIC to be

transferred onto the Data Bus. This function block stores and
compares the IDs of all PICs used in the system.

The associated three I/O pins (CAS0- 2) are outputs when the
8259 is used as a master and are inputs when the 8259 is used as a
slave. As a master, the 8259 sends the ID of the interrupting slave
device onto the CAS0 - 2 lines. The slave, thus selected will send its
preprogrammed subroutine address onto the Data Bus during the
next one or two consecutive INTA pulses.
PIN DIAGRAM
8259 PINS

D[7..0] These wires are connected to the

system bus and are used by the
microprocessor to write or read the internal
registers of the 8259.

A[0..0] This pin acts in conjunction with

WR/RD signals. It is used by the 8259 to
decipher various command words the
microprocessor writes and status the
microprocessor wishes to read.
CONT’D…

 WR When this write signal is asserted, the 8259 accepts the

command on the data line, i.e., the microprocessor writes to the 8259 by
placing a command on the data lines and asserting this signal.

 RD When this read signal is asserted, the 8259 provides on the

data lines its status, i.e., the microprocessor reads the status of the 8259 by
asserting this signal and reading the data lines.

 INT This signal is asserted whenever a valid interrupt request is received

by the 8259, i.e., it is used to interrupt the microprocessor.
CONT’D…
 INTA This signal, is used to enable 8259
interrupt-vector data onto the data bus by a
sequence of interrupt acknowledge pulses issued
by the microprocessor.

 IR 0,1,2,3,4,5,6,7 An interrupt request is

executed by a peripheral device when one of
these signals is asserted.

 CAS[2..0] These are cascade signals to enable

multiple 8259 chips to be chained together.

 SP/EN This function is used in conjunction with

the CAS signals for cascading purposes