RISC and CISC Performance Amdahl’s Law Multiplication Algorithms Division Algorithms Single-Cycle Datapaths Control Signal Summary

RISC Register-Based Instructions

- Simple instructions, fixed format,
optimising compiler
- Speed, low development cost, adapt
to new technology
CISC
- Dense code, simple compiler
- Powerful instruction set, variable RISC
format - Reduced Instruction Set Computers
- Simple instructions, fixed format, optimising compiler
- Speed, low development cost, adapt to new technology
opp for CISC
CISC
MIPS Architecture - Complex Instruction Set Computers
-32 registers ($0..$31) 32 bits each - Dense code, simple compiler
- $0 wired to 0, others general purpose - Powerful instruction set, variable format
Execution Cycle
- register-register or load-store arch. ALU
- e.g. add $1, $2, $3 or lw $8 Selecting ALU operation:
Instruction Formats
Memory Access Instructions – Load
3-types: Register, Immediate, Jump
R-type:
arithmetic, comparison, logical

I-type:
memory access, conditional branches, Multi-Cycle Datapath
arithmetic with constants

Memory Access Instructions – Store

Aspects of Processor Performance

J-type:
unconditional jump to instruction in memory

Key Components (dash-boxed respond in same cycle)

After adding XOR gates as inverters and multiplexors for selecting
the outputs, we can form an ALU design based on ALUb – a one-bit
ALU element.
Design will be managed by two control signals, d0 and d1, to Booth’s Algorithm
select one of the four functions – each corresponds to a MIPS Hardware Combined Datapath for R-type and Memory:
instruction.
Algorithm – determines no. of instructions from source
The wiring block L is needed to provide the appropriate ROM size: 2^input *
program, can affect CPI by favouring slower/faster instructions
initialisation to the 4 left inputs of ALUb. output bits
(e.g. more divide vs add/sub)
Language – statements in language are translated, language Comparison Operations
with heavy support for data abstraction will require indirect - slt: set if less than, if a < b then 1 else 0 Microprogramming
calls, often using instructions with higher CPI - If a < b, a – b < 0, so MSB of (a – b) is 1 (32 bits) Microsequencer
Example Program
Compiler – compiler determines translation of source - Implementation
language instructions into processor instructions - provide additional input to each cell, left of ai, bi
Instruction Set Architecture – affects all three since it affects - LSB input from MSB ALUb output, other inputs set to 0 We add two MUXs to control: (a) the second input
the instructions needed for a function, the cost in cycles of - include additional mux in cell for selection to the ALU, and (b) the Write data input to the
each instruction, and the clock rate of the processor. - to select slt, s=0, d0=1, d1=1 Registers. When the two MUXs receive certain
Improving Performance control signals, this combined datapath behaves
exactly like the R-type/Load datapath above. State Diagram
Branch Instructions
*
More instructions
Only 2 conditional branches, bne (branch not
equal) and beq (branch equal)
Datapaths
The red wire connects the sum output of the rightmost ALUb’ (the
MSB of a – b) to a new MUX which either selects it or the sum
output of the LSB of ALUb, so the LSB output will be the same as
the sum output in the MSB for the SLT instruction, because if a<b,
a-b<0 so the MSB will be set, so the output of SLT will be a one.

Zero Detection
Evaluation Methods

Addressing Modes
- Register addressing: data in registers
- Immediate addressing: data in instruction
Ititself (I-type)
- Base addressing: data in memory e.g.
itload/store instructions RISC
- PC-relative: like base addressing with - Reduced Instruction Set Computers
itregister replaced by the PC - Simple instructions, fixed format, optimising compiler
Handling Exceptions

Comparing Architectures Stack compact since addresses can be found using stack pointer.
Register faster than memory, reduce memory traffic,
compiler friendly, improved code density

Performance Estimation
- clocked circuit: no combinational loops
- speed limited by propagation delay through the slowest
itcombinational path
- slowest path: usually carry path
- clock rate: approx. 1/(delay of slowest path), assuming
* The BEQ datapath needs to do two things: (a) to check if two registers contain the same
value by subtracting one from the other and see if the zero output of the ALU is one or
- edge-triggered design not; (b) if the zero output is one, then we need to find the amount of the branch specified
- flip-flop propagation delay, set-up time, clock skew etc. negligible by the offset field.
 Wh le General

Al gned Data:
Pr m t ve data type
requ res K bytes
Address must be mult ple
of K
So for the example below,
there w ll be empty space n
memory n so as to allow the
Operand Types addresses of each part to be
Immed ate - Format: $Imm (e.g.): $-536, $0x1F mult ples of the r k bytes.
Reg ster - Format: reg ster rb, referenced value s then R[rb] (e.g.): %rax,%eax Memory allocated n order
Memory Reference - Format: memory address Addr, referenced value s then M[Addr] declared so th nk about how
An Immed ate (Imm) or a Reg ster (R[rb]) spec f es the memory address e.g. movq you can save space w th th s,
(%rcx), %rax

Array Elements:
A[ ][j] s element of type T, wh ch
requ res K bytes Address =
Wr te H t:
A + * (C*K) + j*K = A + ( *C + j) * K

Assoc at v ty(N) - Number of l nes for

each set - “N-way set assoc at ve
cache”
Does Src1 - Src2 We now ndex nto cache sets, of
wh ch there are C/B/N
Use lowest log2( C/B/N) = I b ts of
test a, a shows f a s +, - or 0 block address
D rect-mapped: N=1, so I = log2( C/
B)
Fully-assoc at ve: N= ΤC B, so I = 0
b ts
D rect Mapped - Each set corresponds
Spat al local ty: A data n close prox m ty to the current to one block
data w ll be accessed n a small amount of t me. Fully Assoc at ve - One set that
conta ns every block
Temporal local ty: A data that has been accessed w ll be
accessed aga n n a small amount of t me.
Average Memory Access T me (AMAT) - AMAT = H t t me + M ss
H t Rate: rate × M ss penalty
L1 MR = 3-10%
L2 MR = <1%
Wr te M ss:
H t T me:
L1 HT = 4 clock cycles
L2 HT = 10 clock cycles

Block / L ne - Smallest un t of memory

M ss Penalty:
P = 50-200 cycles for m ss ng n L2 and go ng to ma n memory that can be transferred between ma n
Cache S ze (C): number of sets per the number of l nes (N) n eachmemory and cache
set and block s ze, C = S x N x B Set - A group of l nes / blocks