ITI analog IC design
LAB06
Differential Amplifier
Undersupervision
Prof.Hesham Omran
Date
5 august 2025
Part 1: Differential Amplifier Design
𝐼𝑆𝑆𝑅𝐷=2𝑉𝑜𝑢𝑡−𝐶𝑀 must be smaller than (𝑉𝐷𝐷 – 𝑉𝑑𝑠𝑎𝑡−𝑡𝑎𝑖𝑙) for proper
large signal characteristics (why?).
To keep both transistors in saturation as if Vout increases and nearly equal
vdd a larger voltage drop on the resistance and it may lead to get both
transistors (input and tail) out of saturation
3)Choose 𝑹𝑫 to meet the CM output level spec.
2Vout-cm
Rd= = 30kΩ
Iss
6)Choose 𝑽∗ to meet the differential gain spec.
1.82Vrd
V*= = 136.5𝑚𝑉
Av
Assume we will set 𝑉𝐷𝑆 of the tail current source to 300𝑚𝑉 to allow more
output swing. Report the input pair sizing using SA.
Given the above assumption for 𝑉𝐷𝑆 of the tail current source, calculate
the required CM input level.
Vicm=-Vgs-Vds+1.8=0.56V
Use SA to plot the sizing at a constant 𝝈(𝑰𝒐𝒖𝒕)/𝐼𝑜𝑢𝑡.
report the above figure with a cursor added to the selected design point.
The same picture that has been attached.
Calculate the min and max CM input levels. Is the previously selected CM
input level in the valid range?
VinCm-min = 0.6 – 0.8702 = - 0.2702 V
VinCM_max =– 0.9404– 0.2 +1.8= 0.6596 V
Yes the input is in the range between tha max and min
Part 2: Differential Amplifier Simulation
Create the schematic of a differential amplifier “lab_06_diff_amp”.
Create a symbol for the diff pair. Edit the symbol to look as shown below
in the testbench schematic.
OP simulation.
All transistors operate in saturation because Vds > Vdsat &&Vds>Vov
Diff small signal ccs:
Report the Bode plot of small signal diff gain.
Hand analysis
Avd=gmRd=8.5 V/V
1
BW= =36.42Mrad =5.83Mhz
Rout*Cl
Simulation Hand analyisis
BW 5.67 MHz 5.83Mhz
gain 7.77 V/V 8.5 V/V
CM small signal ccs:
Report the Bode plot of small signal CM gain.
Compare the DC CM gain with hand analysis in a table. Is it smaller than
“1”? Why?
-gmRd
Avcm= =7.32 x 10-2
1+2gmRss
Hand analysis Simulation
Gain 7.32 x 10-2 5.5 x 10-2
Yes it is much smaller than ‘’1” as gm is degenerated with very high Rss
and that’s what is needed to reduced common mode gain as much as
possible till it reaches 0 to increase CMRR (noise rejection)
Justify the variation of Avcm vs frequency.
As frequently increase the capacitors degenerades both Rd and Rss which
leads to smaller gain
Plot Avd/Avcm in dB. Compare Avd/Avcm @ DC with hand analysis in a
table.
Simulation Hand Analysis
CMRR gain 1.14x102 Avd/Avcm=1.16x102
Justify the variation of Avd/Avcm with frequency.
As explained before as frequency increases Rss is degenerated by
parasitic capacitance which decreases the noise rejection.
Report diff large signal ccs (VODIFF vs VIDIFF). Compare the extreme
values with hand analysis in a table.
Extremes when one side of inputs is much higher than the other side
which leads to the whole current 40u flow through one half and the other
half has 0 current (O.C) . Vdiffmax=40u*30*103 ,the min =-Vdiffmax both
are equal1.2V
Simulation Hand analysis
Gain 1.918 || -1.1927 1.2 || -1.2
We will use parametric sweep on AC analysis to get GBW.
Find the CM input range (CMIR). Compare with hand analysis in a table.
Simulation Hand analysis
CMIR_max 0.82 V 0.66 V
CMIR_min -0.3 V -0.28 V
CMIR_range 1.12 V 0.94 V
