Computer Organization &
Architecture
Mohona Ghosh
Instruction Format
• Any basic computer has 3 types of instruction formats:
1) Memory Reference Instruction
2) Register Reference Instruction
3) Input-Output Instruction
Memory Reference Instruction
Register Reference & Input-Output Instruction
List of Operations
Instruction Address Formats
• What is the maximum number of addresses one might need in an
instruction?
• Depends upon the address format we choose …
• 4 types
• Three-address format
• Two-address format
• One-address format
• Zero-address format
• Line of code to be executed: C = A+ B
Three Address Format
Operation Source1 Addr., Source 2 Addr., Destination Addr.
• RTN: M[C] ← 𝑀 𝐴 + 𝑀 𝐵
• ADD A,B,C
• If k bits are needed to specify the memory address of each operand, then in the
encoded binary form of the above instruction, we need 3k bits plus bits needed
to represent the ADD opcode
• In modern processors (e.g., 32-bit), this format is not common as it becomes too
large to fit in one word of memory
Two Address Format
Operation Destination Addr., Source Addr.
• RTN: M[A] ← 𝑀 𝐴 + 𝑀 𝐵 ( Add the contents of mem. loc. A and B
and store the result back in A )
• ADD A,B
• Instruction size decreases, however original contents of A are lost
• Operand A is both a source and a destination
Instruction Address Formats
• We may use a third location (C) to alleviate this problem
• MOV C, B M[C] ← 𝑀 𝐵
• ADD C, A M[C] ← 𝑀 𝐴 + 𝑀[𝐶]
• Contents of A are not destroyed
• However, no. of instructions needed to execute the original code
increases
One Address Format
Operation Operand Addr.
• Here the second operand address is implicit (implied)
• The CPU register Accumulator (AC) is generally the implicit operand
used for all data manipulations
• The MOV operation in the earlier format is replaced by two special
instructions:
• LOAD A AC ← 𝑀 𝐴 (Copy the content of location A into accumulator)
• STORE A M[A] ← 𝐴𝐶 (Copy the content of accumulator into memory
location A)
One Address Format
• Operation C = A + B can be executed as follows:
• LOAD A AC ← 𝑀 𝐴
• ADD B AC ← 𝐴𝐶 + 𝐵
• STORE C C ← 𝐴𝐶
• Instructions are much simpler but number of instructions required
further increases
Zero Address Format
Operation
• Can be found in a stack based memory organization
• The stack is always in a known location, thus address of operands is
implicit and need not be included in the instruction
Unary and binary operations do not use an address field for the instructions
E.g., ADD operation has the effect of popping the top two numbers from the stack, adding
them and pushing the sum into stack
Instruction Address Formats
Q. Write a program to evaluate X = (A+B) x (C+D) in
1) Three address format
2) Two address format
3) One address format
Assume you have 4 registers (R1-R4) with you
X = (A+B) x (C+D)
• Three address format
• Two address format
X = (A+B) x (C+D)
• One address format
Instruction Address Formats
• The number of addresses per instruction is a basic design decision
• Tradeoff
• Fewer addresses per instruction -> instructions are simpler requiring a less
complex processor
• Also results in instructions of shorter length
• But at the same time, programs contain more total instructions -> longer
execution time
• Most modern processors support and employ multiple instruction
formats to provide flexibility and efficiency
ADDRESSING MODES
ADDRESSING MODES
• The different ways in which the location of an operand is specified in an instruction
are referred to as addressing modes
• Effective Address (EA): Actual address of the location containing the referenced
operand
Implied Mode
Immediate Mode
• Used when we want to directly use some constant value
• Here, the operand is given explicitly in the instruction
• We have operand field instead of address field in the instruction
• E.g., HLL: A = 6;
Instr.: MOV A, #6
• A common convention is to use the sharp sign (#) in front of the value to
indicate that this value is to be used as an immediate operand
• E.g., HLL: A = B+6;
ALN: MOV R1, B
ADD R1, #6
MOV A, R1
ADDRESSING MODES
• Register Mode
• Absolute Mode
• Used when we want to fetch operands stored in a register or memory
location
• May be used as a combination of these modes as well in the same
instruction
Absolute Mode
• Also called direct mode
• The operand is in a memory location
• Address of this location is given in the instruction
• Here, EA = LOC
• E.g., HLL : int A, B (2 variables stored in memory at loc. A and B)
• To access these locations, instructions will be of form – ADD A,B
• This is absolute or direct mode
Register Mode
• The operand is the contents of a processor register
• The name (address) of the register is given in the instruction
• Here, EA = 𝑅𝑖
• E.g., MOV R2, R1
• Copy the contents of R1 into R2
• E.g., MOVE LOC, R2
• Combination of both register and absolute mode
Indirect Mode
• With direct addressing, the actual address space covered is limited to
the k - address bits an instruction can hold
• This length of the address field is usually less than the memory word
length, thus limiting the address range
• To alleviate this problem, we use indirect address mode
• Instruction does not give the operand or its address explicitly
• Instead the address field holds a second memory loc. / register
• The effective address of the operand is the contents of a register or memory
location whose address appears in the instruction
Indirect Mode
Indirect mode through a memory loc. Register indirect mode
ADD (A), R0 ADD (R1), R0
A B B Operand
B Operand
R1 B
• Indirection is denoted by placing the name of the register or the memory location inside a parentheses ()
• The register or memory location that contains the address is called a pointer
Indirect Mode
• E.g., HLL: A = *B (B is a pointer variable)
Instr.: MOV A,(B)
• Here, EA = [Ri] or [LOC]
• Advantage: Increased address space is now available
• Limitation: Instruction requires to access the memory twice to fetch
the operand
• Register indirect mode is better as access to memory is only once
Base Register Addressing Mode
• Another form of indirect addressing mode
• Useful for dealing with arrays
• The effective address of the operand is generated by adding a
constant value to the contents of a register
• The operation is indicated as X(Ri)
• X = the constant value that defines the offset
• Ri = name of the register which contains the address of the location. Also
known as base register
• Here, EA = [Ri] + X
• X can be positive as well as negative (signed or unsigned)
Index Mode
Here, R5 is the base register
• Here EA = 20 + [R5] = 20 + 1000 = 1020
Indexed Addressing Mode
Base with Index Mode
• Another version of Index mode that uses two registers
• Operation is indicated as: (Ri, Rj)
• Here, a second register called the index register is used to contain the
offset X
• EA = [R1] + [R2]
• Provides more flexibility in accessing operands because both
components of effective address can be changed
Base with Index and Offset Mode
• X(Ri, Rj)
• EA = X + [Ri] + [Rj]
• EA = offset + contents of base register + contents of index register
• Can be used to represent 3-D array
Relative Addressing Mode
• Similar to base register mode
• The effective address is determined using the program counter PC in place of
the general purpose register Ri
• Represented as X(PC)
• EA = [PC] + X
• Since the addressed – location is relative to the PC, the name Relative mode
• Commonly used in conditional branch instructions
Relative Addressing Mode
Auto increment and decrement mode
(Another variant of register indirect mode)
• Auto increment mode • Auto decrement mode
• EA of the operand is the contents of a • Contents of a register specified in the
register specified in the instruction instruction are first automatically
• After accessing the operand, contents decremented and then used as the
of the register are automatically effective address of the operand
incremented to point to next item in • Written as -(Ri)
the list
• Written as (Ri)+
• In both the cases, the increment/decrement amount is implicit
• 1 for byte sized operands, 2 for 16-bit and 4 for 32-bit operands
• Both the modes are generally used to implement stack operations
Instruction Encoding
Q. A processor has 40 distinct instructions and 24 general purpose
registers. A 32-bit instruction word has an opcode, two register
operands and an immediate operand. How many bits are available for
the immediate operand field ?
Instruction Cycle
