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The document details the design and simulation of a 16-bit Arithmetic Logic Unit (ALU) using Verilog HDL. It outlines the various operations the ALU can perform, such as addition, subtraction, and logical operations, and describes the methodology used for its development and testing. The project successfully verified the ALU's functionality and correctness using Active-HDL.

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5 views1 page

APoster PDF

The document details the design and simulation of a 16-bit Arithmetic Logic Unit (ALU) using Verilog HDL. It outlines the various operations the ALU can perform, such as addition, subtraction, and logical operations, and describes the methodology used for its development and testing. The project successfully verified the ALU's functionality and correctness using Active-HDL.

Uploaded by

deenablink
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DESIGN AND SIMULATION OF A 16-BIT

ARITHMETIC LOGIC UNIT (ALU) USING


VERILOG HDL
BY: DEENA ALJERAUWI, RAGHAD ALMUBARAK,
RAND ALSHAREEF, ABRAR ALKHATHAMI, LAYAN MOQBIL ALOTAIBI

ALU VERILOG CODE


INTRODUCTION: OPRATION:
An Arithmetic Logic Unit (ALU) is a
fundamental part of digital 4 'b0000: ALUResult = A + B; //addition
4 'b0001: ALUResult = A - B; //subtraction
systems. It performs arithmetic 4'b0010: ALUResult = A * B; //Multiplication
4 'b0011: ALUResult = A / B; //division
and logic operations. 4 'b0100: ALUResult = A << 1; //Shift Left
4'b0101: ALUResult = A >> 1; //shift right
In this project, we built a 16-bit ALU 4'b1000: ALUResult = A & B; //And
using Verilog and tested it with 4 'b1001: ALUResult = A | B; //OR
4 'b1010: ALUResult = A ^ B; //XOR
Active-HDL to ensure its 4 'b1101: ALUResult = ~(A ^ B); //XNOR
4 'b1110: ALUResult = (A > B) ? 16'd1 : 16'd0; //greater then
correctness and efficiency. 4 'b1111: ALUResult = (A == B) ? 16'd1 : 16'd0; //equality

MATHOOLGY:
ALU DIAGRAM:
Defined the required operations
Wrote Verilog code
Selected operations: add, sub, mul,
div, AND, OR, XOR, XNOR, shifts,
comparisons
Simulated using Active-HDL
Verified correctness with test
cases

CONCLUSION:
We successfully designed and
tested a 16-bit ALU using Verilog.
The Carry and Zero flags helped us
check for special results like ALU OPERATIONS TABLE:
overflow or zero

REFERENCE:
Aarti Jagtap et al., “Design and
Implementation of 8-Bit ALU using
Verilog,” Int. J. of Engineering Applied
Sciences, 2018.

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