The Shunt Active Power Filter with Better

Dynamic Performance
Krzysztof Piotr Sozanski, Member, IEEE

This distortion causes an increase of harmonic content in the

Abstract— This paper describes the proposed active power line current, which is dependent on a time constant. The APF
filter (APF) with a modified output inverter. When the value of compensating current dynamics is dependent on the inverter
load current changes rapidly, the APF transient response is too output time constant consisting of APF output inductance and
slow the line current suffers from dynamic distortion. This
distortion causes an increase of harmonic content in the line
resultant impedance of load and mains. In the APF shown in
current, which is dependent on a time constant. The APF control Fig. 1 the THD ratio is increased by about 10%.
current dynamics is dependent on the inverter output time
a)
constant consisting of APF output inductance and resultant
impedance of load and mains. According to this modification the
APF dynamics are improved. The Matlab simulation results of
the modified APF are also presented in the paper.

Index Terms— active power filters, power system harmonics,

pulse width modulated inverters, sliding DFT.

I. INTRODUCTION

T HE mains power nonlinear loads can be divided into two

main categories: predictable loads and noise-like loads.
Most loads belong to the first category. The parallel (shunt)
active power filter (APF) permits compensation of the
harmonics and asymmetries of the line currents caused by
nonlinear loads.
For predictable loads it is possible to predict current values
in subsequent periods, after a few periods of observation. It is
possible to use a circuit with non-causal current compensation b)
as shown in [2], [3], [4]. This compensation is dependent on
the inverter output time constant. Current samples are stored
in DSP memory and in subsequent periods of mains current
are compared with present samples, then if respective sample
differences are less than assumed values the non-causal
current compensation algorithm is switched on, sending to the
output non-causal samples. For noise-like loads this technique
is ineffective.
The APF control current dynamic is dependent on the inverter
output time constant, itself resulting from APF output
inductance and resultant impedance of load and mains power
line (Fig. 1a).
When the value of load current changes rapidly, as in
current iL in Fig. 1b, the APF transient response is too slow
[3], [4] the line current iS suffers from dynamic distortion.

Krzysztof Piotr Sozański, University of Zielona Góra, Faculty of Electrical Fig. 1. Classical three-phase shunt active power filter: a) tests circuit, b)
Engineering, Computer Science and Telecommunications, Institute of experimental waveforms of active power filter in steady-state with the
Electrical Engineering, ul. Podgórna 50, 65-246 Zielona Góra, Poland, tel.: resistive load: load current iL1 (green), compensating current iC1 (red), line
+4868-3282567, fax: +4868-3254615, (e-mail: K.Sozanski@iee.uz.zgora.pl, current iS1 (orange).
www: http://hook.uz.zgora.pl/~ksozansk/).
 Presented in this paper is a modified output inverter for u DCp − uS (t 0 ) − u DCn − uS (t 0 )
decreasing dynamic distortions in such kind of loads. Δ iC (t ) = t1 = t2 . (3)
LC LC
II. INVERTER OUTPUT STAGE MODEL
A diagram of a simple model of power inverter connected to
the mains power is shown in Fig. 2, where: ZS - represents the
mains power line impedance, ZL - nonlinear load, LC - output
inductance, RC – resultant output resistance, CC - output filter
capacitance, for dumping modulation components, uS - mains
power line voltage, uDCp, uDCn - capacitor C1 and C2 voltage, S1
and S2 – switches represent the inverter transistors.
In this circuit the time constant is mainly dependent on
inductor LC value.

Fig. 4. Time diagram of idealized compensating current iC.

The voltage value at capacitors C1 and C2 is stabilized by a

voltage controller and is equal to uDC; that is why it is possible
to describe uDC = uDCp = uDCn. To achieve low dynamic
distortion output current iC slew rate must be high. The slew
rate can be calculated by formula

Fig. 2. Diagram of inverter model connected to the mains power. d iC (t ) ± u DC − uS (t )

= . (4)
dt LC
In respect of the biggest influence of LC for output time
constant it is possible to simplify circuit Fig. 2 to the circuit Currently IGBT transistors are mostly used as switching
shown in Fig 3. elements in the inverters. For the ordinary IGBT the maximum
switching frequency is equal to 20 kHz and around 60 kHz for
fast IGBT. The transistor switching power losses can be
approximately described by formula
uS
uDCp
Ptot ≈ f k Ek + P on .
S1
LC iC (5)

uDCn S2 where:
Ek – energy lost in single switching cycle,
Pon – power losses in switched-on state.
So it is possible to assume that transistor power losses are
Fig. 3. Simplified diagram of the inverter model connected to the mains proportionally dependent to switching frequency.
power, used for current ripple calculation. According to the above-mentioned problems choosing the
right value of inductor LC is difficult. For a higher LC value,
If it is assumed that switching frequency fs is constant, that the time constant is higher and dynamic distortion is bigger,
during the switching period Ts=1/fs voltages: uS , uDCp, uDCn are while for a lower LC value, circuit dynamic distortions are
constant and that average current iC is constant too, then the smaller but value of compensating current ripple iC is higher.
output current can be calculated by equations One of the ways to decrease the dynamic distortion and keep
current ripple at reasonable value is to increase transistor
u DCp − uS (t 0 )
iC (t1 ) = t1 + iCn , (1)
switching frequency, but in this case there are increased
switching losses and influence from the switching transition.
LC
− u DCn − uS (t0 )
iC (t 2 ) = iCp + t2 . (2) III. PROPOSED SOLUTION
LC
Given that high dynamic performance is necessary only for
where: t1–t0 switch-on time for S1, t2-t1 switch-on time for S2.
approximately 10% of the time in the mains power period,
A time diagram of idealized compensating current iC is
increasing the switching time to 60 kHz seems to be
shown in Fig. 4. Output ripple can be calculated by the
ineffective. Therefore the author is proposing an inverter
equation
output stage with two sets of transistors and inductors. The
simplified version of this proposition is shown in Fig. 5. The
circuit consists of two output stages: one with switches Ss1, Ss2
and inductor LCs, and a second with switches Sf1, Sf2 and therefore during future investigations other modulator control
inductor LCf. The first works continuously with the slowest algorithms will be designed and implemented.
switching frequency fp1. The value of inductor LCs is designed
to achieve a low iC current ripple. In the second, switches Sf1, IV. APF TEST CIRCUIT
Sf2 work with several-times higher frequency only in the case
when output current changes very quickly (typically 10% of Using the above simulation parameters there was designed a
mains power period). The value of inductor LCf was designed single-phase active power filter as shown in Fig. 7. For the
simulation experiments the parallel APF without feedback was
to achieve a fast response in the output current.
used, because of its greater stability.
ZS iS iL ZL
Slow Fast

Ss1 Sf1 uS u1
iC
uDCp LCf iCf uS
LCs iCs iC

uDCn iCs iCf

Ss2 Sf2
Qs1 Qf1
C1 LCs LCf
uDCp

fp1 fp2
Fig. 5. Simplified diagram of modified inverter model connected to the mains
C2 Qs2 Qf2
power. uDCn

At the beginning a hysteresis digital modulator was designed

for controlling the modified inverter. Taken into consideration Slow Fast
during the simulation analysis were the modified inverter and
classical inverter. The simulation parameters are: Fig. 7. Single-phase active power filter with modified inverter, test circuit.
LCf = 0,5 mH, LCs = 2,5 mH, uDC = 390 V, fp2= 51200 kHz,
fp1= 25600 kHz. Step responses for modified inverter and A block diagram of the control circuit for the considered
classic inverter are shown in Fig. 6. The classic inverter APF is presented in Fig. 8. The control algorithm uses sliding
response time is about 200 μs and is near 30 μs for the DFT for the load current first harmonic detection [4]. In
modified inverter. respect to sliding DFT characteristics [4] control circuits have
For assumed simulation parameters current ripples are to be synchronized to line voltages u1(t), u2(t), u3(t). This is
higher when the fastest part of the inverter is switched-on, but why the synchronization unit is one of the most important
the resultant value of THD is less if compared to the classical parts of the control circuit. The digital control circuit is
inverter. synchronized with the mains voltage by a synchronization
a) unit. It consists of a low-pass filter and phase locked loop
40
circuit (PLL).
30 Figures 9 and 10 show the simulation waveforms in the
20 same steady-state conditions, for classical circuit (Fig. 9) and
10 for circuit with modified inverter (Fig. 10). Depicted are the
0
following waveforms: load currents iL, compensating currents
0 1 2 3 4 5
-4
iC, line currents iS. Using the modified inverter it is possible to
x 10
b) decrease the harmonic contents in power line currents from
40
about THD=15% to about THD=5%.
30
The results of the simulation analysis confirm good
20 dynamic performance of the modified inverter used in a shunt
10 active power filter. Currently at our Institute there is being
0
built a three-phase modified inverter for a 75 kVA shunt
0 1 2
t [s]
3 4 5
-4 active filter (Fig. 11). The presented solution will be
x 10
employed together with a non-causal algorithm described by
Fig. 6. Simulation waveforms of inverter output currents for step response
the author in [3], [4], while for predictable loads there will be
with the resistive load: a) modified circuit, b) classical circuit. used only a working non-causal algorithm, but for
unpredictable rapid change of load current the fastest part of
The hysteresis digital modulator is one of the simplest and the modified inverter will be working.
safest, especially at the early experimental stage, but it has a
lot of disadvantages, especially for digital implementation [1],
Fig. 8. Block diagram of control algorithm.

d)
a) 25
50
i (t) [A]

0
L

20
-50
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
b)
50 15
|I (f)| [A]
i (t) [A]

0
S
C

-50 10
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
c)
50
5
i (t) [A]

0
S

-50
0
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12 0 500 1000 1500 2000 2500 3000
t [s] f [Hz]

Fig. 9. Simulation waveforms of single-phase active power filter in steady-state with the resistive load, classical inverter: a) load current iL, b) compensating
current iC, c) line current iS, d) frequency spectrum of line current iS.

a) d)
25
50
I (t) [A]

0
L

20
-50
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
b)
50 15
|I (f)| [A]
I (t) [A]

0
S
C

-50 10
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
c)
50
5
I (t) [A]

0
S

-50
0
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12 0 500 1000 1500 2000 2500 3000
t [s] f [Hz]

Fig. 10. Simulation waveforms of single-phase active power filter with modified output inverter in steady-state with the resistive load, modified inverter: a) load
current iL, b) compensating current iC, c) line current iS, d) frequency spectrum of line current iS.
 REFERENCES
DC
DC bus [1] M. Kazimierkowski, L. Malesani, “Current Control Techniques for
capacitors Three-Phase Voltage-Source Converters: A Survey,” IEEE Transactions
on Industrial Electronics, vol.45 N0 5, October, 1998.
[2] S. Mariethoz, A. Rufer, “Open Loop and Closed Loop Spectral
Frequency Active Filtering,” IEEE Transactions on Power Electronics,
vol.17, N0 4, July, 2002
[3] K. Sozanski, “Harmonic Compensation Using the Sliding DFT
Algorithm,” 35rd Annual IEEE Power Electronics Specialists
Conference - PESC '04, Aachen, Germany, 2004.
[4] K. Sozanski, “Sliding DFT Control Algorithm for Three-Phase Active
Power Filter,” 21rd Annual IEEE Applied Power Electronics Conference
- APEC '06, Dallas, Texas, USA, 2006.

Krzysztof Piotr Sozański (M’1997) was

born in Czerwieńsk in Poland, on July 25,
1957. In 1981 he was awarded an MSc
degree in electrical engineering, specializing
in the field of automation and electric
metrology, from the Electrical Engineering
Department at the Zielona Góra University
of Technology, in Zielona Góra, Poland. In
1999 he received his PhD degree in
Inductors for high Inductors for low telecommunications from the Institute of
frequency switches frequency switches Electronics and Telecommunications at
Poznań University of Technology, in
Poznań, Poland. He is an Associate Professor at the Institute of Electrical
Fig. 11. Three-phase active power filter modified inverter (in build).
Engineering, University of Zielona Góra. His current research interests are in
digital signal processing, implementation of digital signal processing methods
V. CONCLUSION in digital signal processors, power electronics, and active power filters. He is
author or coauthor of more than 70 conference and periodical papers and
For predictable nonlinear loads which vary slowly 1 patent.
compared to line voltage period (rectifiers, motors etc.) it is
easier to predict current changes. For such loads shunt active
power filter with non-causal algorithm is possible to decrease
harmonic contents. However, for noise type nonlinear loads
(like in arc furnace) the load currents are non periodic and
stochastic, proposed APF with improved dynamic
performance is good solution.

ACKNOWLEDGMENT
Special thanks for Mr. Marek Szymanek for his work on
APF hardware.