INPUT FILES

To Physical design
Inputs for Block level Physical Design

▪ Gate level Netlist (.v /.vhd)

▪ Constrains file (SDC) (.sdc)

▪ Timing Libraries (.lib/.db)

▪ Physical Libraries (.lef )

▪ Technology files (.tf/.techlef)

▪ Cap tables (Tlu+ files) (.tlup)

▪ Power Specification File (.cpf / .upf )

Gate level Netlist (.v /.vhd)
 Gate level Netlist (.v /.vhd)

▪ The Netlist file contains the logical connectivity information of standard cells
and macros which are present in our design .

▪ This file is the output file of logical synthesis stage ,which is the previous stage
of physical design, so we got this file from synthesis stage .

▪ DC , RC are two commonly used tools to convert RTL design into gate level
netlist basically a .v or .vhdl file
Contents of Gate level Netlist
▪ Module Information
- name of a module and ports of that module will be present
Ex :

▪ Input And Output Port Information

- Name and Direction of the port will be present
Ex :
Contents of Gate level Netlist
▪ Design Name

- Name Of The Entire Design Will Be Present In The Netlist File

Ex : Leon

▪ Net Names
- The Information Of Inter Connect Wires Will Be Present In Netlist File
Ex :
Example Format of Gate level Netlist
Constrains File (SDC) (.Sdc)
 Constrains File (SDC) (.Sdc)

▪ In SDC File Timing Constraints Which Are To Be Used To Meet Timing

Requirements In The Design Are Provided .

▪ SDC Is A Tcl-based Format. All Commands In An SDC File Conform To The

Tcl Syntax Rules.

▪ This File Is Input For Synthesis Stage Also ,So This File Is Got From Synthesis
Stage With Some Modified Constrains
 Contents Of SDC File
▪ Main Clocks Definitions

- The Main Clocks Are Created With Clock Name, Time Period And
Source Port Name

Ex :
▪ Generated Clock Definitions
- The Generated Clock Is Defined By Using Source Clock.

Ex :
▪ Virtual Clock Definitions
- To Fix The Timing Violations At In To Reg, Reg To Out Some Virtual
Clocks Are Defined Without Source Pin ,These Are Physically Not Exist
Ex :
Contents Of SDC File
▪ Input And Output Delays
- Time Taken By The In Put Signal To Reach Our Block And Time Taken
By The Output Signal To Reach Other Block Are Called Input And Output Delays
.

Ex :

▪ Max And Min Delays

- Max
Ex : And Min Delays For The Paths Are Defined In Sdc File.
 Contents Of SDC File
▪ I/0 Constrains
- Input Transition/Load And Output Capacitance/Drive Of Input And Output Ports
Also Present In Sdc File.
Ex :

▪ Drv’s
- Drv’s Max Input Transition, Max Output Capacitance And Max Fan Out Also
Defined In The Sdc File.
Ex :
Contents Of SDC File
▪ Path Exceptions
-The Path Exceptions Like False Path, Multi Cycle Path And Half Cycle Paths Are
Defined In The Sdc

Ex :

▪ Clock Uncertainty
- We Add Certain Uncertainties In Clock To Over Fix The Setup .This Uncertainty
Also Defined In The Sdc File.
Ex :
 Contents Of SDC File

▪ Case Analysis

- To Define The Mode Either Scan Mode Or Functional Mode This Case
Analysis Is Defined In The Sdc File
Ex :
Example Format Of SDC File
Timing Libraries (.lib/.db)
 Timing Libraries (.lib/.db)

▪ The Timing Libraries (.lib/.db) contains the functionality Information ,Timing

and power information of standard cells and also contains the Timing and power
Information of macros.

▪ These Timing Library files are different for all three corners as slow lib , typical
lib and fast lib.

▪ In These File Timing information and some other parameters are presented in
lookup table format

▪ These files are given by the vendors as a .lib / .db files .

 Contents of Timing Library file
▪ Functionality Information Of Standard Cells

- At Output Pin Of The Standard Cell The Functionality Is Defined As Below

Ex:

▪ Power Information
- Leakage Power Ex:

- Internal power Ex:

 Contents of Timing Library file
Ex:-
▪ Timing Information
- Library Setup
- Library Hold
- Recovery Time
- Removal Time
- Rise Time
- Fall Time
- Cell Delay In Lookup Table Format As A Function
Of Input Transition And Output Capacitance
 Contents of Timing Library file
▪ Default Design rules

- max transition
- max capacitance
- max fanout
Ex :

▪ PVT Conditions
- PVT conditions for all the corners will be present
Ex :
 Contents of Timing Library file

▪ Pin Information Ex :

- Pin Name
- Pin Direction
- Pin Capacitance

▪ Unateness

- At Output Pin Of The Standard Cell The Unateness Of The Cell Is

Present
Ex :
 Contents of Timing Library file

▪ Wire Load Models

- To Estimate The Net Delays Wire Load Models Also Present

Ex :
 Contents of Timing Library file

▪ Operating conditions and units

Ex :
Example format of Timing Library file
Physical Libraries (.lef )
 Physical Libraries (.lef )

▪ These files contain physical about standard cells, macros and I/O pads,
necessary for placement and routing.

▪ These Physical Libraries (.lef ) files are different for Standard cells and Macros
as Cell lef and macro lef.

▪ These files are given by the vendors as a .lef files .

 Contents of Physical Library (.lef )file
Name Of The Standard Cell/Macro
▪ Size Of The Cell/Macro Ex : Standard Cell :
-Height And Width Of The Standard Cell/Macro Is Present

▪ Symmetry Of Cell/Macro

- On Which Axis These Standard Cell/Macros Are

Symmetrical

▪ Class Of Standard Cell/Macro Macro :

- Which Class Standard Cell / Macro Are Belongs To Either
Core Or Block

▪ Site Of Standard Cell/Macro

- Information about Which Site The Standard Cell / Macro .

 Contents of Physical Library (.lef )file
▪ Pin Information
- Pin Name
- Pin Direction Either Input Or Output
Ex :
- Pin Area
- On Which Layer Pin Is Present
- Pin Dimensions
- Pin Usage Either Signal Or Power Or Ground
▪ Site information
-it sis the smallest size of a standard cell that can be placed in our design
standard cell size is multiples of site
Ex :
Example Format of Physical Library (.lef )file
Technology files (.tf/.techlef)
 Technology files (.tf/.techlef)

▪ Technology files (.tf/.techlef) contains information about the metal layers and
vias and design rules

▪ These files are different for each technology nodes .

▪ These files are given by the foundries as a .techlef/.tf files .

Contents of Technology Files (.tf/.techlef)
▪ Metal Layers Information

- Metal Layer Name

- Metal Layer Type Route Or Cut
- Metal Layer Direction Horizontal Or Vertical
- Metal Layer Pitch ,It Is The Center To Center Distance Of Between The Metals
Having Minimum Width And
Minimum Spacing.
- Metal Layer Width
- Metal Layer Area
Contents of Technology files (.tf/.techlef)

- Metal Layer Spacing Table

- Metal Layer Resistance Per Square
- Metal Layer Capacitance Per Square Distance
- Metal Layer Thickness
- Metal Layer Edge Capacitance
- Metal Layer Min Density And Max Density
- Metal Layer Antenna Ratio
Antenna Ratio = Metal Area / Gate Area
- Metal Layer Current Density Average
Example Format of Technology files (.tf/.techlef)

Ex :
Contents of Technology Files (.tf/.techlef)

▪ Via Information
Ex :
- Via Name
- Via Type Cut/Route
- Via Spacing
- Via Width
- Via Enclose Area
- Via Antenna Ratio
- Via Current Density Average
 Contents of Technology Files (.tf/.techlef)
▪ Information about Non Default Rule (NDR)
- When we need extra Spacing and Extra Width There We can use these Non
Default Rules (NDR)
Ex :
Example Format of Technology Library File (.tf/.techlef)
Cap Tables (Tlu+ Files) (.Tlup)
 Cap Tables (Tlu+ Files) (.Tlup)

▪ TLU Stands For Table Look Up It Is A Table Containing Wire Capacitance At

Different Net Lengths And Spacing's. It Is Calculated And Pre Stored In A File.

▪ Tluplus Is A Binary Table Format That Stores The Rc Coefficients. The Tluplus
Models Enable Accurate RC Extraction Results By Including The Effects Of
Width, Space, Density, And Temperature On The Resistance Coefficients.

▪ This File Is Give By The Foundries As .Tlup File , This File Is Used In Parasitic
Extraction.
Example Format of Cap Tables (Tlu+ Files) (.Tlup)
Example Format of Cap Tables (Tlu+ Files) (.Tlup)
Power Specification File (.cpf / .upf )
 Power Specification File (.cpf / .upf )

▪ UPF/CPF Is A IEEE Standard For Specifying Power Intent In Electronic Design

Automation.

▪ This Upf/Cpf Files Are Used In The Low Power Technologies

▪ These Files Are Provided By The Vendors As .Upf/.Cpf

▪ This File Contains The Information About All The Power Gating Cells
Contents Power Specification File (.cpf / .upf )

▪ Power Supplies-supply Nets, Power States

- Information About The Power And Ground Nets Is Present
▪ Power Control-power Switches
- When Switchable Domine Is Present These Power Switches Are Used
▪ Protection-level Shifters And Isolation Strategies
- When Two Different Operating Powers Are Used This Are Used
▪ Memory Retention During Times Of Limited Power(retention Strategies)
- When Switchable Domine Is Present To Keep The Previous Data When It In
Off State This Cells Are Used
Example Format of UPF/CPF File
THANK YOU