INSTITUTE OF PHYSICS PUBLISHING SEMICONDUCTOR SCIENCE AND TECHNOLOGY

Semicond. Sci. Technol. 17 (2002) 1149–1156 PII: S0268-1242(02)37808-8

Numerical and experimental study of a

0.25 µm fully-depleted silicon-on-
insulator MOSFET: static and dynamic
radio-frequency behaviour
R Rengel1, J Mateos1, D Pardo1, T González1, M J Martı́n1,
G Dambrine2, F Danneville2 and J-P Raskin3
1
Departamento de Fı́sica Aplicada, Universidad de Salamanca, Plaza de la Merced s/n.
37008 Salamanca, Spain
2
Département Hyperfréquences et Semiconducteurs, IEMN, F-59652 Villeneuve d’Asq
Cedex, France
3
Microwave Laboratory, Université catholique de Louvain, Maxwell Building,
B-1348 Louvain-la-Neuve, Belgium
E-mail: raulr@gugu.usal.es

Received 7 June 2002, in final form 9 September 2002

Published 4 October 2002
Online at stacks.iop.org/SST/17/1149
Abstract
We investigate the static and dynamic characteristics of a 0.25 µm
gate-length fully-depleted silicon-on-insulator metal–oxide–semiconductor
field effect transistor. Considering properly the physical topology of the
transistor with its accesses, numerical simulations are performed using a
two-dimensional ensemble Monte Carlo simulator and these are compared
with experimental results. Moreover, in the simulation we include important
effects that appear in real transistors, such as surface charges, contact
resistances, impact ionization phenomena and extrinsic parasitic
capacitances. The appearance of a velocity overshoot region near the drain,
together with the presence of hot carriers in the channel, is observed in the
saturation regime. The dynamic behaviour of the device is described through
significant small signal equivalent circuit parameters, which are examined
by means of internal quantities (such as profiles of the internal electron
concentration), provided by numerical simulations. In general, the device
shows excellent performance in terms of important design parameters, such
as transconductance-to-current ratio, transconductance and cut-off
frequency together with a reduced capacitive coupling to the substrate. The
results of the Monte Carlo simulations show an exceptional agreement with
the experimental data, thus confirming the validity of the simulator as a
reliable tool for the analysis of the influence of geometrical and electrical
parameters on the static and dynamic performance of the device.

1. Introduction accomplish this objective. With this purpose, many efforts

have been made to advance the progressive reduction of the
The enormous advance in mobile communications achieved dimensions of bulk silicon metal–oxide–semiconductor field
in the last few years has made it necessary to develop effect transistors (MOSFETs) [1]. Nevertheless, although rf
radio-frequency (rf) front-ends at a low cost with the lowest CMOS circuits have been already demonstrated [2], and they
level of noise. When the reduced cost is a major concern, are undoubtedly a promising technology, the shrinkage in bulk
silicon-based technologies seem to be the most adequate to device geometries to the deep-submicrometre scale presents

0268-1242/02/111149+08$30.00 © 2002 IOP Publishing Ltd Printed in the UK 1149

R Rengel et al

many technological problems [1], mainly due to strong short Finally, the extrinsic experimental parasitics, such as parasitic
channel effects. At this point, when bulk devices begin to face resistances and capacitances associated with the feed lines,
significant limitations, silicon-on-insulator (SOI) technology should be taken into account in the EMC results to perform
becomes a key solution [3]. the comparison between simulation and experimental results.
Although the SOI idea is not new at all, the possibilities In this way, the EMC method can be reliably used to
of SOI MOSFETs have been fully explored only in these last analyse both the static and dynamic behaviours of the
few years thanks to the advances in the fabrication process. devices, the bias dependence of small-signal equivalent circuit
Especially in the case of fully-depleted (FD) SOI MOSFETs, (SSEC) parameters and complementarily to investigate the
many advantages can be seen over traditional bulk devices influence of geometrical factors or surface charges, with the
[3, 4]: the absence of latch-up, higher soft-error immunity, advantage of providing a microscopic physical interpretation
shorter and easier CMOS processing, sharper subthreshold in terms of quantities such as velocity, energy or concentration
slope, and reduced electric fields, parasitic capacitances, and of carriers. Thus, once the simulator has confirmed its
short-channel effects together with a higher transconductance reliability, ‘computer experiments’ can be performed, and
and lower threshold voltage. As a consequence, a very many questions raised by the experimental measurements can
good high-frequency performance is obtained and the devices be addressed [9].
may operate at lower voltages, thus reducing the power The paper is organized as follows. In section 2, the
consumption. Furthermore, front-end processing is cheaper FD SOI structure under analysis and the main features
in SOI than in bulk CMOS, and a higher packing density is of our EMC simulator are presented. In section 3, the
also achieved [3]. experimental and simulated static characteristics are studied,
For these many reasons, FD SOI technology has including important parameters such as the transconductance-
attracted extraordinary interest in recent years, and it can be to-drain current ratio, and internal quantities such as electron
affirmed that it has fully joined the microelectronics roadmap. concentration, velocity and energy. The dynamic response of
Therefore, in order to accelerate the development of future the device is analysed in section 4, paying special attention to
generations of SOI devices and their applications, it has the SSEC capacitances. The majority of the results shown in
become necessary not only to accurately characterize and this paper correspond to saturation bias conditions, since this
study the high-frequency performance, but also to obtain a is the operation region of main interest in these devices for
good comprehension of the inner physics of these devices. analogue applications. Finally, the main conclusions of our
To reach this goal, the aid of computer simulation is of work are presented.
primary importance. Traditional simulation methods, such
as drift–diffusion or hydrodynamic models, present critical 2. Structure under analysis and Monte Carlo
restrictions when applied to the study of MOSFETs with procedure
small dimensions, where short channel effects such as velocity
overshoot or the appearance of hot carriers become important. A CMOS-compatible process on 200 mm UNIBOND
R
wafers
The ensemble Monte Carlo (EMC) method [5] is the most was employed for the fabrication of the FD SOI MOSFETs
adequate simulation technique to deal with this problem, since under analysis in this paper. The thickness of the buried oxide
it is based on a microscopic approach and, as a consequence, is 0.4 µm and the thickness of the active silicon is thinned
it includes in a natural way the main effects associated with down to 30 nm in order to ensure completely the depletion
small devices. of holes in the active layer, thus eliminating floating body
The purpose of this work is to analyse the static and effects. The transistors have a gate length of 0.25 µm, and are
dynamic characteristics of 0.25 µm gate-length FD SOI composed of eight gate fingers in parallel of 6.25 µm and
n-MOSFETs. The devices studied in this paper have already 12.5 µm each. In order to lower the contact resistances,
been used for designing various classical analogue and digital a titanium salicide process was used. A more complete
circuits: operational transconductance amplifiers, base band description of the device topology and fabrication process can
circuits (a sigma-delta modulator, a rf quadrature generator, be found in [7].
low pass filters, etc), microwave oscillators at 6 and 12 GHz For the numerical calculations, we use a two-dimensional
[6] and a 2 GHz GSM receiver [7], showing an exceptional (2D) semi-classical bipolar EMC simulator self-consistently
dynamic behaviour and one of the best noise microwave coupled with a Poisson solver. This method has been
performances reported in the literature [8]. Due to the lack successfully applied to the study of several Si and SiGe
of simulation tools, the topology of the circuits is not fully devices, such as heterojunction bipolar transistors (HBTs) and
optimized nor are the devices themselves. To investigate bipolar junction transistors (BJTs) [10] or MOSFETs [11].
in depth the physical behaviour of deep sub-micrometre FD Both electron and holes are simulated as particles, which
SOI devices and to draw some optimization directions for allows us to properly evaluate the influence of each type
future MOSFET generations, EMC simulations are carried of carrier. The simulation of holes is justified by the fact
out. Several requirements have to be fulfilled to assure that holes in the substrate may play an important role in the
the validity of the calculations. First of all, the doping dynamic behaviour of the device [11], and also by the possible
profiles and geometry (oxide thickness, length of the overlap appearance of impact ionization phenomena in the active layer.
regions, etc) of the different layers of the fabricated device The size of the mesh ranges from 10 to 250 Å in order to solve
under analysis must be reproduced as accurately as possible. accurately the Poisson equation. The time step is 1 fs.
Secondly, important real effects also have to be considered, Figure 1 shows the geometry of the simulated structure.
such as surface charges or impact ionization phenomena. Important experimental parameters, such as overlap length

1150
 Numerical and experimental study of a 0.25 µm FD SOI MOSFET

Source Drain ext

Cgd
overlap overlap
Lov Gate G LG RG RD LD D
Cgd
Lsp 0.25µm
Cds Cpd
Source Drain Cpg
Cgs
Gate oxide tox
tsi gm gds
n+ p-channel n+ 30 nm ext ext
Cgs Ri Cds

Buried Oxide
RS jωτ
gm=gm0e

LS

p-silicon substrate S

Figure 2. Small-signal equivalent circuit of the device. The shaded

area represents the intrinsic elements obtained by the EMC
Substrate contact simulation. The ‘intrinsic’ device from the point of view of
experimental measurements is enclosed in the dotted box; this
Figure 1. Schematic diagram of the simulated FD SOI device. The includes the effect of parasitic extrinsic capacitances and excludes
diagram is not scaled. contacts parasitics.

(Lov), spacer oxide length (Lsp), oxide thickness (tox), doping electric field normal to the surface, whereas indexes 1 and 2
profiles, etc, take their real values, in an attempt to reproduce represent the oxide and the semiconductor, respectively. σ 12
the geometry of the fabricated devices. The device is is the surface charge associated with the oxide–semiconductor
considered to operate in common-source configuration, with interface. Different surface charges are placed in the channel,
source and substrate contacts short-circuited. Since our the spacer and the overlap regions, since they correspond to
simulator is bi-dimensional, the width of the devices (W ) different materials (p-doped Si in the channel and n-doped Si in
corresponds to the non-simulated dimension. Accordingly, the overlap and spacer regions). The values for these charges
the majority of the results shown in this paper are properly can be adjusted (within the range given by experimental
normalized by the total width. To compare with experimental studies) in order to achieve a good fit of the EMC results
results, we focus on the devices with the largest width W(8 × to the measured current–voltage (I–V) characteristics [9].
12.5 µm) in order to reduce the possible influence of parasitic Dirichlet conditions are applied in the four terminals, and the
effects associated with a short device width, such as fringing von Neumann condition (Ei = 0) is taken into account at the
capacitances at the end of the gate fingers. Nevertheless, it has limits of the simulation domain. The contacts are considered
to be stressed that the comparison of the EMC calculations to be ohmic. More details about the EMC simulator are given
with the experimental results for the devices with a shorter in [11].
width is very similar to that reported here for the FD SOI For the treatment of impact ionization processes, we
MOSFETs with a larger W, which indicates that no significant adopt a Kane model [13], fitting the free parameters in
additional parasitic effects appear when the finger width is order to reproduce the experimental data of bulk ionization
reduced from 12.5 µm to 6.25 µm. coefficients [14, 15]. The threshold energy is 1.3 eV.
The effect of external series resistances in the drain and Interesting phenomena such as parasitic bipolar action could
source terminals can be taken into account by considering self- be analysed if necessary, since our simulator allows us to
consistently the voltage drop due to these resistances [12] for follow the dynamics of possible holes generated in the active
each time step layer.
To determine the SSEC parameters by means of an EMC
VGS
int
= VGS − RS ID (1) simulator, the intrinsic admittance (Y ) parameters must be
calculated as a previous step. The Y parameters are evaluated
VDS
int
= VDS − (RS + RD )ID (2)
through the Fourier analysis of the transient response of the
where VDS and VGS are the external potentials applied in device to voltage steps applied separately in the gate and drain
contacts, VDS
int
and VGS
int
are the voltages applied to the intrinsic contacts. The complete procedure is described in [16]. Once
device, RS and RD are the source and drain contact resistances, the Y parameters are determined, the elements of the SSEC
and ID is the drain current. can be calculated [17, 18].
Real effects appearing in the fabricated devices, such as The SSEC circuit considered in this work is shown in
surface charges [9] or impact ionization processes have also figure 2. The shaded area represents the intrinsic device,
been taken into account. In the case of surface charges, we and corresponds to the parameters directly calculated by the
consider a static surface charge at the oxide–semiconductor EMC simulation. To represent the parasitic capacitive effects
boundaries [9]. The boundary condition for the Poisson solver associated with the topology of the device, the extrinsic
at these surfaces is capacitances Cgs ext
, Cgd
ext
and Cds
ext
(which are considered to
be bias-independent) have been added to the SSEC scheme.
ε1 E1 − ε2 E2 = σ12 , (3) Their values have been determined as the difference between
where εi and Ei are, respectively, the permittivity and the the experimental data and the intrinsic EMC results at zero

1151
R Rengel et al

400 20

ID (A m-1)
300
500 MC simulation 200
Experimental
15
Drain current (Am )

100 VDS = 1.0

gm / ID ratio (V-1)
Experimental
-1

EMC simulation
0
400 0.0 0.5 1.0 1.5
VGS (V)
10
300 VGS = 1.25 V

VGS = 1.0 V 5
200
VGS = 0.75 V
0
100 0 100 200 300
VGS = 0.5 V -1
Drain current (Am )
0
0.0 0.5 1.0 1.5 2.0 Figure 4. The ratio gm/ID as a function of ID.
VDS (V)

Figure 3. Drain current as a function of drain-to-source voltage for

VGS ranging from 0.5 to 1.25 V. The inset shows the transfer transconductance. Thus, the surface charge value that allows
characteristic for a drain voltage of 1.0 V. the best fit of the simulations to the experimental data has
been found to be 2 × 1016 m−2 in the overlap and spacer
regions. With regard to multiplication phenomena, it must be
current, where only the effect of geometric capacitances, both mentioned that impact ionization processes were not observed
intrinsic and extrinsic, remains. For the FD SOI MOSFET in the VDS range considered. Since we are interested in
device under analysis, these values were found to be Cgs ext
= studying the behaviour of the device in the saturation regime,
214 fF mm , Cgd = 126 fF mm , and Cds ≈ 0 fF mm−1.
−1 ext −1 ext
the majority of the results shown in this work correspond to
Since these parasitic effects cannot be directly simulated in VDS = 1.0 V.
a 2D model, we must add these capacitances to the EMC The ratio between extrinsic transconductance (gm) and
results in a post-processing stage [9] in order to enable a direct drain current (ID) is an important figure of merit in analogue
comparison between EMC results and experimental data. The designs [20, 21]. The transconductance represents the
dotted box in figure 2 encloses the ‘intrinsic’ equivalent circuit amplification delivered by the device, whereas the drain
from the point of view of experimental measurements, which current represents the power dissipated to obtain such an
includes Cgsext
, Cgd
ext
and Cds ext
, and excludes the effect of contact amplification. Therefore, the gm/ID ratio is a quality factor
resistances, capacitances and inductances [19]. Therefore,
 the that can be interpreted as a measure of the ‘transconductance
Y parameters directly obtained by the MC method YijMC are generation efficiency’ [20]. In the case of the FD SOI devices
modified by means of the following relationships [9] to provide under study, experimental measurements for this parameter
the final intrinsic Y parameters (Yij ): in the saturation regime have shown a significantly improved
  performance compared to that of partially-depleted (PD) SOI
Y11 = Y11MC
+ jω Cgs ext
+ Cgd
ext
Y12 = Y12MC
− jωCgdext
and bulk MOSFETs [7]. As can be seen in figure 4, an

ext  (4) excellent agreement is obtained between the MC results and
Y21 = Y21MC
− jωCgd ext
Y22 = Y22MC
+ jω Cds + Cgd
ext
.
the experimental data.
These can be strictly compared with the ‘intrinsic’ At this point, the EMC method can provide useful
experimental data (extracted from measured S parameters information to understand the underlying physics of the device
taking away the effect of contact parasitics). by means of several quantities. This information is also very
helpful for the analysis of the SSEC parameters, as we show in
3. Static characteristics section 4. Figure 5 presents the electron concentration under
the gate oxide for three different values of VGS, 0.25, 0.75
The experimental measurements (curves) and the EMC results and 1.25 V, for a drain voltage of 1.0 V. For the lowest value
(symbols) of the I–V characteristics are shown in figure 3. The of VGS, the inversion layer begins to appear, showing a peak
transfer characteristic for VDS = 1.0 V is shown in the inset. in the part of the channel nearest to the source region. The
The EMC output characteristics show a very good agreement device operates in the weak inversion regime, where it is still
with the experimental results. In particular, it must be pointed under cut-off conditions. Over this gate potential, the electron
out that the value of the threshold voltage (approximately concentration in the inversion layer progressively increases
0.25 V) is quite well reproduced. Once the main topology (and so does the length of that inversion layer), and it is able to
parameters of the structure (tsi, tox, Lov, doping profiles, etc) supply the necessary number of carriers to have a significant
are considered in their real values, the surface oxide charge flux of current, thus operating in the saturation regime. It must
in the overlap and spacer regions is found to be an important be pointed out that a significant carrier density appears in the
factor in achieving an accurate fit of the simulation results source overlap, whereas in the drain side it is practically null,
to the experimental extrinsic transconductance (that reaches corresponding to a MOSFET device biased in the saturation
a maximum value of around 350 S m−1 at VDS = 1.0 V), condition (see figure 3). Nevertheless, for the case of the
whereas the surface charge in the p-doped layer mainly affects highest VGS a small concentration appears in the drain side,
the threshold voltage, having a very small influence on the and the inversion layer extends over the whole channel,

1152
 Numerical and experimental study of a 0.25 µm FD SOI MOSFET

Source Drain
overlap Gate contact overlap
(a )
-3
)

3 5 V
tion (10 cm

0.2
19

V GS VGS = 0.5 V VGS = 1.0 V

Gate
VGS = 1.25 V

Velocity (10 ms )
Source 4 VGS = 0.75 V

-1
2 overlap Drain
tra

3 (a)

5
Gate overlap
Electron concen

on oxide
gi
1 re 2
ce
ur vsat = 1.2·105 m s-1
So

n
1

gio
re
0

ain
Burie

Electron energy (eV)

d oxid
e Dr
0.4 (b )
0.3
0.2
-3
)

3 5 V (b )
tration (10 cm

0.7 0.1
19

V GS 0.0
Gate
Source
2 overlap 0.25 µm
Drain
Gate overlap
on Figure 6. Profiles of velocity (a) and energy (b) of inversion carriers
Electron concen

oxide
gi
1 re under the gate oxide for VDS = 1.0 V and different gate voltages.
ce
ur
So
n
gio

velocity and energy of carriers in that region. It must be

re

0
ain

Burie remarked that for the lowest gate voltages, values of energy
d oxid
Dr

e near 0.4 eV are obtained. The presence of these hot electrons

can affect the noise behaviour of the device [11] and could
even damage the gate oxide at the drain end of the channel,
(c ) leading to the appearance of traps or surface states at the oxide
)

V
-3

3 5
tration (10 cm

1.2 [3]. Nevertheless, the maximum values of average energy are

19

V GS clearly much lower than the impact ionization threshold energy

Gate
Source (1.3 eV), which explains the absence of impact ionization
2 overlap Drain
overlap
processes in the range of drain voltages considered in our
Gate
on experiments and simulations (below 1.5 V). This absence of
Electron concen

oxide
gi
1 re impact ionization phenomena, together with the total depletion
ce
ur of holes in the active layer due to the reduced value of the active
So
n
gio

layer thickness (30 nm) on the FD SOI devices studied, are

re

0
indicative of a total absence of floating body effects in the bias
ain

Burie
d oxid
Dr

e range considered. This was experimentally confirmed by the

fact that the threshold voltage dependence on back gate voltage
Figure 5. Electron concentration under the gate oxide for three reaches an almost ideal behaviour [7]. Moreover, experimental
different gate voltages: (a) 0.25 V; (b) 0.75 V; (c) 1.25 V. results of 1/f noise show a kink-free noise behaviour at
low frequencies, indicating also the absence of body effects
which indicates that the device begins to approach the triode [7, 24].
region.
Figure 6 shows the electron velocity (figure 6(a)) and the
electron energy (figure 6(b)) for VDS = 1.0 V and VGS ranging 4. Dynamic response
from 0.5 V to 1.25 V. The profile of electron velocity in the
channel is of primary importance in order to analyse non-local The knowledge of the SSEC of electronic devices is very
effects such as velocity overshoot, which is a well-known helpful in analogue circuitry design. Not only does it
short-channel effect in bulk [22] and SOI MOSFETs [23]. allow us to evaluate the dynamic response, but it is also an
For the FD SOI MOSFET under study, an overshoot region important step in the calculation of noise parameters. With
is present near the drain end of the channel. The overshoot the aid of EMC numerical simulations, a microscopic physical
is less pronounced as the gate voltage is increased. A similar interpretation of the results can be provided in terms of the
behaviour is detected for the electron energy, a result that has spatial profiles of several quantities of interest.
been previously observed in bulk MOSFET devices [11]. This Figure 7 shows the experimental (curves) and simulated
effect is explained by the fact that, for higher gate voltages, values (symbols) for the gate-to-source (Cgs), gate-to-drain
the difference between the gate and drain potentials is less (Cgd) and drain-to-source (Cds) capacitances as a function of
significant. As a consequence, there is a reduced electric VGS. A notable agreement between the EMC results and
field at the drain end of the channel, thus lowering both the the experimental data is observed, not only in the range

1153
R Rengel et al

VDS 1.0 V

Cgd (10-10 F m-1)

VDS 1.5 V 4 VDS = 1.0 V 6 Experimental
25
3
Cgs MC Cgs exp.
MC

Cgs/Cgd
Fm )

4
-1

2
Cgd MC Cgs exp.
20
0.5 1.0 Cds MC Cds exp.
-10

VGS (V)
2
Capacitance (10

15
VDS = 1.0 V
10
0
0.0 0.5 1.0
5
VGS (V)
Figure 8. The ratio Cgs/Cgd versus gate voltage.
0
0.00 0.25 0.50 0.75 1.00 1.25 Source Drain
VGS (V) overlap Gate contact overlap
Figure 7. Small-signal equivalent circuit capacitances as a function
of gate voltage for VDS = 1.0 V. The curves represent the data 5

Increase of charge (arbitrary units)

extracted from experimental measurements, whereas symbols
correspond to EMC results. The inset shows the experimental values VDS 1.0 V
of Cgd as a function of VGS for two different VDS (1.0 and 1.5 V). 4
VDS 1.5 V
of values but also in the bias dependence. The gate-to-
3
source capacitance takes the highest values among the three
capacitances in the VGS range considered. For the lowest
values of VGS, the concentration of carriers in the inversion 2
layer is not very important yet (the device operates in the
depletion regime or in the weak inversion regime; see figure 5),
and the capacitance corresponds mainly to the depletion 1
capacitance. As the gate voltage becomes higher, the length
of the inversion layer increases notably (and also the number of
carriers in that inversion layer, especially near the source end of 0
the channel). As a consequence, Cgs also increases. It must be Figure 9. Increase of charge under the gate for two different drain
stressed that, from a gate voltage of around 0.75 V, the increase voltages, 1.0 and 1.5 V, and VGS = 1.0 V.
of charge in the source side of the inversion layer is practically
linear with VGS. The inversion layer covers the main part of the The Cgs/Cgd ratio is a figure of merit of a device. It
channel length, and therefore Cgs reaches a saturation value. expresses the ratio between the control capacitance of the
An important result is that a high electron concentration is active channel (Cgs) and the parasitic Miller capacitance
observed at the overlap region near the source (see figure 5), (feedback gate-to-drain-capacitance, Cgd). High values of
thus indicating an important weight of the overlap capacitance this parameter may be indicative of an elevated maximum
over the total Cgs in this range. frequency of oscillation. Figure 8 shows the experimental
The values of Cgd are rather constant with VGS in the and simulation results for this parameter as a function of gate
whole range considered; only for the highest VGS (from 1.0 V) voltage. A good agreement is obtained between both. The
a tendency to increase is observed. The reason for this slight highest value for the Cgs/Cgd ratio, 3.5, is obtained for a gate
increment is the appearance of the inversion layer at the drain voltage of around 0.7 V.
end of the channel (see figure 5); the depletion in the pinch-off With regard to the dependence of the SSEC capacitances
region begins to disappear, and consequently the device would on VDS, we have observed that in saturation the bias
leave the saturation regime for higher gate voltages. dependence and the values of Cgs hardly change with VGS
In a bulk MOSFET device, the drain-to-source when VDS increases (the maximum EMC values obtained
capacitance may take significant values compared with other for this capacitance for VDS = 1.0 V and VDS = 1.5 V are
SSEC capacitances, which indicates a strong influence of the 1290 fF mm−1 and 1310 fF mm−1, respectively). This
substrate on the dynamic behaviour of the device [11]. For indicates that the Cgs capacitance is practically controlled by
the FD SOI MOSFET under study, extremely low values for the gate voltage, provided the device is in the saturation regime.
Cds as compared to Cgd and Cgs are achieved, as figure 7 In contrast, the values of Cgd decrease when VDS increases, as
shows. Therefore, it can be affirmed that by using the FD SOI can be seen in the inset of figure 7, and the dependence with
technology, thanks to the thick buried oxide, the capacitive the gate voltage has a lower slope in the case of VDS = 1.5 V.
coupling to the substrate is substantially reduced compared to To explain this effect, in figure 9 we show the increase of
bulk MOSFETs. This constitutes a key advance in improving charge under the gate oxide calculated by means of the EMC
the high-frequency behaviour of the device. simulator for VGS = 1.0 V and two different drain voltages,

1154
 Numerical and experimental study of a 0.25 µm FD SOI MOSFET

gmi exp. gmi EMC obtained for the simulated devices are in very good agreement
gdsi exp. gdsi EMC with the experimental measurements, which confirms the
100
fT exp. validity of the simulator. In particular, we obtain a good

Cut-off frequency (GHz)

fT EMC
600
description of important design parameters, such as the gm/ID
gmi, gdsi (S m )

80
-1

VDS = 1.0 V
ratio.
400 60 The velocity overshoot of electrons and the appearance
of hot carriers at the drain end of the channel are observed,
40 which are well-known short-channel effects. For a given drain
200 voltage in saturation, the width of the overshoot region and
20 the maximum electron energy decrease as the gate voltage is
increased. Impact ionization phenomena were not detected in
0 0
0.00 0.25 0.50 0.75 1.00 1.25 the studied bias range. This result, together with the complete
VGS (V) full depletion of holes in the active layer due to the reduced
value of the silicon active film thickness, ensures the absence
Figure 10. Intrinsic transconductance, output conductance and of floating body effects in the devices under study.
cut-off frequency as a function of VGS for a drain-to-source voltage The dependence of the dynamic parameters on the biasing
of 1.0 V.
has been analysed by means of the spatial profiles of several
relevant quantities, such as local electron concentration,
1.0 and 1.5 V, when an increment of 0.1 V is applied at the provided by the EMC simulation. With regard to the
gate. The decrease in Cgd with VDS can be associated with capacitances, the extremely reduced influence of the capacitive
the lower increase of charge near the drain for the case of coupling to the substrate that has been found is remarkable, and
VDS = 1.5 V, compared to the case of the lower drain voltage. this is of great interest for high-frequency analogue designs.
Therefore, it can be affirmed that in saturation Cgd has an The Cgs/Cgd ratio has been also studied, showing the highest
important dependence on VDS due to its strong impact on the values for high VDS in saturation.
In general, the FD SOI MOSFETs studied show a great
evolution of the charge at the drain side of the channel, as
performance in terms of elevated transconductance and cut-
shown in figure 9.
off frequency, which makes them an excellent candidate for
The experimental data and the simulation results for
rf analogue applications. With regard to the EMC simulator,
the intrinsic transconductance, gmi, the intrinsic output
once it has been validated it constitutes an enormously valuable
conductance, gdsi, and the cut-off frequency, fT = gmi/2π(Cgs +
tool for the optimization of geometrical parameters and the
Cgd) [12], are plotted as a function of gate voltage in figure 10
analysis of the static, dynamic, and noise device performance
for VDS = 1.0 V. The simulation results reproduce accurately
when the gate length is scaled down. This will be the subject
the bias dependence of the experimental data for the three
of forthcoming works.
parameters, although at high VGS the EMC values of gmi
are slightly lower than the experimental measurements, while
those of gdsi are, in general, underestimated due to the lower Acknowledgments
slope of the ID–VDS EMC characteristics compared to the
experimental one. The maximum experimental value for gmi This work was funded by the research projects TIC2001-1754
(475 S m−1) is reached for a gate voltage of approximately from the Ministerio de Ciencia y Tecnologı́a and SA057/02
from the Consejerı́a de Educación y Cultura de la Junta de
1.0 V, but even for VGS = 0.5 V a high value (over
Castilla y León.
300 S m−1) is achieved, which would indicate the capability
of the transistor to give a high gain-bandwidth product even
for low gate voltages. The maximum value of the cut-off References
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