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Module 5-2 - mod5

Analog Circuits (APJ Abdul Kalam Technological University)

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Module 5:
Voltage Regulators: Fixed and Adjustable voltage regulators, IC 723 – Low voltage and high voltage
configurations, Current boosting, Current limiting, Short circuit and Fold-back protection. Data Converters:
Digital to Analog converters, Specifications, Weighted resistor type and R-2R Ladder type. Analog to Digital
Converters: Specifications, Flash type and Successive approximation type.

VOLTAGE REGULATORS: FIXED AND ADJUSTABLE VOLTAGE REGULATORS

The function of a voltage regulator is to maintain a constant DC voltage at the output irrespective of voltage
fluctuations at the input and (or) variations in the load current. In other words, voltage regulator produces a
regulated DC output voltage.

Voltage regulators are also available in Integrated Circuits (IC) forms. These are called as voltage regulator
ICs.

Types of Voltage Regulators

There are two types of voltage regulators −

 Fixed voltage regulator

 Adjustable voltage regulator

Fixed voltage regulator

A fixed voltage regulator produces a fixed DC output voltage, which is either positive or negative. In other
words, some fixed voltage regulators produce positive fixed DC voltage values, while others produce negative
fixed DC voltage values.

78xx voltage regulator ICs produce positive fixed DC voltage values, whereas, 79xx voltage regulator ICs
produce negative fixed DC voltage values.

The following points are to be noted while working with 78xx and 79xx voltage regulator ICs −

 “xx” corresponds to a two-digit number and represents the amount (magnitude) of voltage that voltage
regulator IC produces.
 Both 78xx and 79xx voltage regulator ICs have 3 pins each and the third pin is used for collecting the
output from them.
 The purpose of the first and second pins of these two types of ICs is different −
o The first and second pins of 78xx voltage regulator ICs are used for connecting the input and
ground respectively.
o The first and second pins of 79xx voltage regulator ICs are used for connecting the ground and
input respectively.

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ADJUSTABLE VOLTAGE REGULATOR

An adjustable voltage regulator produces a DC output voltage, which can be adjusted to any other value of
certain voltage range. Hence, adjustable voltage regulator is also called as a variable voltage regulator. The DC
output voltage value of an adjustable voltage regulator can be either positive or negative.

LM317 voltage regulator IC

LM317 voltage regulator IC can be used for producing a desired positive fixed DC voltage value of the
available voltage range. LM317 voltage regulator IC has 3 pins. The first pin is used for adjusting the output
voltage, second pin is used for collecting the output and third pin is used for connecting the input. The
adjustable pin (terminal) is provided with a variable resistor which lets the output to vary between a wide range.

The above figure shows an unregulated power supply driving a LM 317 voltage regulator IC, which is
commonly used. This IC can supply a load current of 1.5A over an adjustable output range of 1.25 V to 37 V.

IC 723 – LOW VOLTAGE AND HIGH VOLTAGE CONFIGURATIONS

The popular general purpose precision regulator is IC 723.

Internal Structure of IC 723

The functional block diagram of IC 723 can be divided into four major blocks

1) Temperature compensated voltage reference source, which is zener diode.

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2) An op-amp circuit used as an error amplifier.

3) A series pass transistor capable of a 150 mA output current.

4) Transistor used to limit output current.

The functioning of the above blocks can be explained with the help of a simplified functional block diagram of
IC 723 as shown in the Fig. 5.8.2.

Temperature compensated zener diode, constant current source and reference amplifier constitutes the reference
element.

Output voltage is compared with this temperature compensated reference potential of the order of 7 volts. For
this, Vref is connected to the non-inverting input of the error amplifier.

This error amplifier is high gain differential amplifier. It's inverting input is connected to the either whole
regulated output voltage or part of that from outside. For later case a potential divider of two scaling resistors is
used. Scaling resistors help in getting multiplied reference voltage or scaled up reference voltage.

Error amplifier controls the series pass transistor Q1 which acts as variable resistor. The series pass transistor is
a small power transistor having about 800 mW dissipation. The unregulated power supply source (< 36 V d.c.)
is connected to collector of series pass transistor.

Transistor Q2 acts as current limiter in case of short circuit condition. It senses drop across Rsc placed in series
with regulated output voltage externally.

The frequency compensation terminal controls the frequency response of the error amplifier. The required roll-
off is obtained by connecting a small capacitor of 100 pF between frequency compensation and inverting input
terminals.

The internal structure can be represented in more simplified form as shown in the Fig. 5.8.3.

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Both non-inverting and inverting terminals of the error amplifier are available on outside pins of IC 723. Due to
this, device becomes versatile and flexible to use. Only restriction is that internal reference voltage is 7 volts
and therefore we have to use two different circuits for getting regulated outputs of below 7 volts and above 7
volts.

Applications of IC 723

The various regular circuits as per the requirement can be achieved using IC 723. Some of them are discussed
below :

a. Basic Low Voltage Regulator (Vo = 2 to 7 volts)

The resistor, Rsc is connected between CL and CS pins. The current limit transistor remains non-conductive
unless drops across Rsc is 0.6 V (equal to VBE drop). The value of Rsc can be found out by following equation

Rsc = Vsense / Ilimit = 0.6 / Ilimit …. (5.8.1)

Ilimit can be selected as 1.2 to 1.5 times the maximum load circuit. Potential divider made up of R1 and R2 is
connected between Vref and non-inverting terminals.

Vnon –inverting = Vref × R2 / R1 + R2 ... (5.8.2)

As the series pass transistor is working as emitter follower.

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BASIC POSITIVE HIGH VOLTAGE REGULATOR

For this type, output voltage varies from +7 V to +37 V and IL ≤ 150 mA.

The non-inverting terminal connected to Vref through R3. Due to this arrangement the error amplifier acts as
non-inverting amplifier.

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This is also called basic high voltage low current regulator.

CURRENT BOOSTING IN VOLTAGE REGULATOR

Current Boosting in Voltage Regulator – IC723 regulator is limited to provide a maximum current of 140 mA.
To increase its current capacity, we add a transistor Q by connecting its collector to pin 11, base to pin 10, and
emitter to pin 2, as shown in Fig. 43.38.

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Thus, the collector current of transistor Q comes from unregulated dc supply. The pin 10, or say output current
from Vout is into the base of the transistor, so that

Thus, the maximum current handling capacity of IC723 gets increased by factor current gain β of the connected
transistor.

1. Constant Current Limiting Circuit

A block of series regulation using simple current limiting circuit is shown in the Fig. 5.9.1. It is also called short
circuit protection circuit as it provides protection against short circuiting. The resistance R4 is added m series
with the pass transistor Q1 and the load which is called current sensing resistor.

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The drop across the current sensing resistance R4 is applied to the base-emitter of Q3. Under normal working
condition and rated load current, this drop is insufficient to turn on the transistor Q3 and hence pass transistor
Q1 continues to supply the rated load current.

When current increases due to over loading or short circuit conditions then drop across R4 increases more than
0.6 V. The 0.6 V is sufficient to turn on the transistor Q3. The collector current of Q3 flows through R3 and
decreases the base voltage of Q1. This decreases the load voltage. This decrease in output voltage prevents the
large load current.

The value of R4 can be selected to adjust the rated current of the circuit. As drop across R4 should be less than
0.6 V under normal working condition, for rated current of 1 A, R4 can be selected as 0.7 9. For a rated current
of 7 A, R4 must be selected as 0.1 2 and so on.

Let us study the variation of load current against load voltage with simple current limiting.

When R1 = ∞ i.e. output terminals open, the output voltage is Vo current is zero.

When load increases, the load resistance decreases and the load current increases. The load current can increase
till the drop across R4 is not equal to 0.6 V. This load resistance at which drop across R4 is 0.6 V is say Rmin.
When load current further increases and R1 becomes zero (short circuit), the load voltage decreases and the load
current gets maintained at a value less than rated current. After RL = Rmin the regulation is lost and load voltage
decreases as RL decreases. This is shown in the 5.9.2.

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Let ISL = Load current when load terminals shorted.

In such a case, drop across R4 is equal to VBE to turn on the transistor Q3.

VBE = ISL R4

ISL = VBE / R4 ... (5.9.1)

The minimum load resistance Rmin below which regulation is lost can be calculated as,

Rmin = Vreg / ISL ... (5.9.2)

The practical value of Rmin will be slightly greater or less than this.

Foldback Current Limiting

The disadvantage of constant current limit is relatively large power dissipation in the series pass transistor when
the load terminals are shorted. Thus a large power rating transistor is required. The foldback limiting technique
allows us to provide the necessary load current at rated voltage but reducing the short circuit current. Thus the
series pass transistor gets utilised efficiently. The basic circuit for foldback limiting is shown in the Fig. 5.9.3.

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All the voltages are measured with respect to a common point.

Let the voltage at point A be VA and the current flowing through R4 is almost IL.

VA = IL R4 + Vo ... (5.9.4)

Neglecting the base current of Q3, the cmrent flowing through R5 and R6 is same as I = VA / R5 + R6 ... (5.9.5)

Hence the voltage at the base of Q3 is the voltage across R6

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Thus if the output terminals are shorted, the output voltage Vo reduce to zero.

Hence we get from the equation (5.9.9)

The rated load current IL is also called Iknee known as knee current.

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It can be observed from the equation (5.9.11) that the rated load current is more than the short circuit current.

DATA CONVERTERS:
D/A CONVERTERS:

A DAC (Digital to Analog Converter) accepts an n-bit input word b1, b2, b3, ... bn in binary and produce an
analog signal proportional to it. Fig. 3.25.1 shows circuit symbol and input-output characteristics of a 4-bit
DAC. There are four digital inputs, indicating 4-bit DAC. Each digital input requires an electrical signal
representing either a logic 1 or a logic 0. The bn is the least significant bit, LSB, whereas b 1 is the most
significant bit, MSB.

PERFORMANCE PARAMETERS OF DAC:

The various performance parameters of DAC are,

a. Resolution

Resolution is defined in two ways.

• Resolution is the number of different analog output values that can be provided by a DAC. For an n-bit DAC

Resolution = 2n ... (3.25.1)

• Resolution is also defined as the ratio of a change in output voltage resulting from a change of 1 LSB at the
digital inputs. For an n-bit DAC it can be given as

Resolution = VoFS / 2n – 1 ... (3.25.2)

where, VoFS = Full scale output voltage

From equation (3.25.1), we can say that, the resolution can be determined by the number of bits in the input
binary word. For an 8-bit DAC resolution can be given as

Resolution = 2n = 28

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= 256

If the full scale output voltage is 10.2 V then by second definition the resolution for an 8-bit DAC can be given
as

Therefore, we can say that an input change of 1 LSB causes the output to change by 40 mV.

From the resolution, we can obtain the input-output equation for a DAC.

Thus Vo = Resolution × D

where D = Decimal value of the digital input

and Vo = Output voltage

The resolution takes care of changes in the input.

b. Accuracy

It is a comparison of actual output voltage with expected output. It is expressed in percentage. Ideally, the
accuracy of DAC should be, at worst, ± 1/2 its LSB. If the full scale output voltage is 10.2 V then for an 8-bit
DAC accuracy can be given as

Accuracy = VoFS / (2n – 1)2 …. (3.25.3)

= 10.2 / 255 × 2 = 20mV

c. Monotonicity

A converter is said to have good monotonicity if it does not miss any step backward when stepped through its
entire range by a counter.

d. Conversion Time

It is a time required for conversion of analog signal into its digital equivalent. It is also called setting time. It
depends on the response time of the switches and the output of the amplifier.

e. Settling Time

This is the time required for the output of the DAC to settle to within ±1/2 LSB of the final value for a given
digital input i.e. zero to full scale.

f. Stability

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The performance of converter changes with temperature, age and power supply variations. So all the relevant
parameters such as offset, gain, linearity error and monotonicity must be specified over the full temperature and
power supply ranges. These parameters represent the stability of the converter.

TYPES OF D/A CONVERTER:

There are mainly two techniques used for analog to digital conversion

• Binary weighted resistor D/A converter

• R/2R ladder D/A converter

In these techniques, the shunt resistors are used to generate n binary weighted currents. These currents are
added according to switch positions controlled by the digital input and then converted into voltage to give
analog voltage equivalent to the digital input. Therefore, such digital to analog converters are called current
driven DACs.

a. Binary Weighted Resistor D/A Converter

The binary weighted resistor DAC uses an op-amp to sum n binary weighted currents derived from a reference
voltage VR via current scaling resistors 2R, 4R, 8R, ..., 2n R, as shown in the Fig. 3.25.2

As shown in the Fig. 3.25.2, switch positions are controlled by the digital inputs. When digital input is logic 1, it
connects the corresponding resistance to the reference voltage VR; otherwise it leaves resistor open. Therefore,

For ON-switch, I = VR / R and

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For OFF-switch, I = 0

Here, operational amplifier is used as a summing amplifier. Due to high input impedance of op-amp, summing
current will flow through Rf. Hence the total current through Rf can be given as

IT = I0 +I1 + I2 + … + In

The output voltage is the voltage across Rf and it is given as

The equation (3.25.4) indicates that the analog output voltage is proportional to the input digital word.

The simplicity of the binary weighted DAC is offset by drawbacks associated with it.

Drawbacks :

1. Wide range of resistor values are required. For 8-bit DAC, the resistors required are 21 R, 22 R, 23 R,... and 28
R. Therefore, the largest resistor is 128 times the smallest one.

2. This wide range of resistor values has restrictions on both, higher and lower ends. It is impracticable to
fabricate large values of resistor in IC, and voltage drop across such a large resistor due to the bias current also
affects the accuracy. For smaller values of resistors, the loading effect may occur.

3. The finite resistance of the switches disturbs the binary-weighted relationship among the various currents,
particularly in the most significant bit positions, where the current setting resistances are smaller.

All these drawbacks, especially the requirement of wide range of resistors restricts the use of binary weighted
resistor DACs below 8-bits.

R-2R Ladder DAC

The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As the name suggests,
R-2R Ladder DAC produces an analog output, which is almost equal to the digital (binary) input by using a R-
2R ladder network in the inverting adder circuit.

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Thecircuit diagramof a 3-bit R-2R Ladder DAC is shown in the following figure −

Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit
binary input is b2b1b0b2b1b0. Here, the bits b2b2 and b0b0 denote the Most Significant Bit (MSB) and Least
Significant Bit (LSB) respectively.

The digital switches shown in the above figure will be connected to ground, when the corresponding input bits
are equal to „0‟. Similarly, the digital switches shown in above figure will be connected to the negative
reference voltage, −VR−VR when the corresponding input bits are equal to „1‟.

It is difficult to get the generalized output voltage equation of a R-2R Ladder DAC. But, we can find the analog
output voltage values of R-2R Ladder DAC for individual binary input combinations easily.

The advantages of a R-2R Ladder DAC are as follows −

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 R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is easy to select and design
more accurate resistors.
 If more number of bits are present in the digital input, then we have to include required number of R-2R
sections additionally.

Due to the above advantages, R-2R Ladder DAC is preferable over binary weighted resistor DAC.

A/D CONVERTERS

The A/D conversion is a quantizing process whereby an analog signal is converted into equivalent binary word.
Thus the A/D converter is exactly opposite function that of the D/A converter.

The A/D conversion is a quantizing process whereby an analog signal is converted into equivalent binary word.
Thus the A/D converter is exactly opposite function that of the D/A converter.

Fig. 3.26.1 shows symbol for A/D converter.

1. Performance Parameters of ADC

The Fig. 3.26.2 shows the digital output of an ideal 3 bit ADC plotted against the analog input voltage.

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a. Resolution

Fig. 3.26.2 shows eight (23) discrete output states from 0002 to 1112, each step being 1/8 V apart. Therefore, we
can say that expression of ADC resolution is the same as for 8 the DAC and is repeated here :

Resolution = 2n ... (3.26.1)

Resolution is also defined as the ratio of a change in value of input voltage, V,-, needed to change the digital
output by 1 LSB. If the full scale input voltage required to cause a digital output of all l's is ViFS, then resolution
can be given as

b. Quantization Error

Fig. 3.26.2 shows that the binary output is 011 for all values of Vi between 1/4 and 1/2 Vi. There is an
unavoidable uncertainty about the exact value of Vi when the output is 011 This uncertainty is specified as
quantization error. Its value is ± 1/2 LSB.

It is given as, QE = ViFS / (2n – 1)2 …. (3.26.3)

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Increasing the number of bits results in a finer resolution and a smaller quantization error. The quantization
error can be observed by continuously sampling a time-varying analog signal with an ADC, converting it back
to analog with a DAC, and taking the difference between the two. The resulting sawtooth-like signal, called
quantization noise.

The root mean square value of such signal, En can be given as

En = VFS / 2n √12

This is related to the resolution of the system. For each additional bit of resolution En is cut in half, that is
reduced by 6 dB.

c. Accuracy

Absolute accuracy is the maximum deviation between the actual ADC output and the ideal ADC output. The
relative accuracy is the maximum deviation after gain and offset errors have been removed. The data sheet of
ADC includes the relative accuracy.

d. Linearity

It is an important parameter of the accuracy of ADC. It indicates how close the ADC output is to its ideal
transfer characteristics.

e. Settling Time

It is the time taken by the output of ADC to settle within a specified band ±(1/2)

LSB of its final value following a code change at the input (generally a full scale change).

f. Specifications of Sample and Hold Circuit

For accurate analog to digital conversion the analog input voltage should be held constant during the conversion
cycle. The sample and hold circuit does this task. The specifications of sample and hold circuit are explained
below with the help of waveform of sample and hold circuit.

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1. Acquisition time (tac)

It is the time required for the holding capacitor CH to charge up to a level close to the input voltage during
sampling. It depends on three factors :

• RC time constant

• Maximum output current of op-amp

• Slew rate of op-amp

2. Aperture time (tap)

Because of propagation delays through the driver and switch, Vo will keep tracking Vi some time after the
inception of the hold command. This is the aperture time. To get the precise timing, it is necessary to advance
hold command by this amount.

3. Aperture uncertainty (Δ tap)

It is the variation in aperture time from sample to sample. Due to aperture uncertainty it is difficult to
compensate aperture time by advancing hold command.

4. Code width

The code width is the change in input voltage that occurs between the output code transitions expressed in LSBs
of full scale. Code width uncertainty is the dynamic variation or jitter in the code width causing noise.

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Successive Approximation ADC

In this technique, the basic idea is to adjust the DAC's input code such that its output is within ± 1/ 2 LSB of the
analog input Vi to be A/D converted. The code that achieves this represents the desired ADC output.

The successive approximation method uses very efficient code searching strategy called binary search. It
completes searching process for n-bit conversion in just n clock periods.

Fig. 3.26.6 shows the block diagram of successive approximation A/D converter. It consists of a DAC, a
comparator, and a successive approximation register (SAR).

The external clock input sets the internal timing parameters. The control signal start of conversion (SOC)
initiates an A/ conversion process and end of conversion signal is activated when the conversion is completed.

Operation :

The searching code process in successive approximation method is similar to weighing an unknown material
with a balance scale and a set of standard weights. Let us assume that we have 1 kg, 2 kg and 4 kg weights
(SAR) plus a balance scale (comparator and DAC). Now we will see the successive approximation analogy for
3-bit ADC.

Refer Fig. 3.26.6 and 3.26.7. The analog voltage Vin is applied at one input of comparator. On receiving start of
conversion signal (SOC) successive approximation register sets 3-bit binary code 1002 (b2 =1) as an input of
DAC. This is similar process of placing the unknown weight on one platform of the balance and 4 kg weight on
the other. The DAC converts the digital word 100 and applies it equivalent analog output at the second input of
the comparator. The comparator then compares two voltages just like comparing unknown weight with 4 kg
weight with the help of balance scale. If the input voltage is greater than the analog output of DAC, successive

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approximation register keeps b2 = 1 and makes b1 = 1 (addition of 2 kg weight to have total 6 kg weight)
otherwise it resets b2 = 0 and makes b1 = 1 (replacing 2 kg weight). The same process is repeated for b1 and bo.
The status of b0, b1 and b2 bits gives the digital equivalent of the analog input. Fig. 3.26.7 illustrates the process
we have just discussed.

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The dark lines in the Fig. 3.26.7 shows setting and resetting actions of bits for input voltage 5.2 V, on the basis
of comparison. It can be seen from the Fig. 3.26.7 that one clock pulse is required for the successive
approximation regsiter to compare each bit. However an additional clock pulse is usually required to reset the
register prior to performing a conversion.

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The time for one analog to digital conversion must depend on both the clock's period T and number of bits n. It
is given as,

TC = T (n + 1) ...(3.26.8)

where TC = Conversion time, T = Clock period, n = Number of bits

c. Flash ADC

When system designs call for the highest speed available, flash-type A/D converters (ADCs) are likely to be the
right choice. They get their names from their ability to do the conversion very rapidly. Flash A/D converters,
also known as a simultaneous or parallel comparator ADC, because the fast conversion speed is accomplished
by providing 2n - 1 comparators and simultaneously comparing the input signal with unique reference levels
spaced 1 LSB apart.

Fig. 3.26.8 shows 3-bit flash A/D converter. For this ADC, seven (23 -1) comparators are required. As shown in
the Fig. 3.26.8, one input of each comparator is connected to the input signal and other input to the reference
voltage level generated by the reference voltage divider. The reference voltage (V REF) is equal to the full scale
input signal voltage. The manner in which the flash A/D converter performs a quantization is relatively simple.

The comparators give output "1" or "0" state depending on whether the input signal is above or below the
reference level at that instant. Those comparators referred above the input signal, remain tumed-off,
representing a "0" state. The comparators at or below the input signal conversely become a "1" state. The code
resulting from this comparator is converted to a binary code by the encoder.

The number of comparators required for n bit resolution is,

Number of comparators = 2n – 1 ... (3.26.9)

As seen earlier the quantization error is ± 2 LSB. Thus for an ADC, the maximum frequency for a sine wave to
be digitised within an accuracy of ± 2 LSB is,

fmax ≅ 1/ 2π(TC)2n ... (3.26.10)

where fmax = Maximum input frequency

TC = Conversion time and n = Number of bits

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