VLSI DESIGN (22ECC24 )

Dr.P.Anuradha
Associate Professor
ELECTRONICS & COMMUNICATION ENGINEERING
Chaitanya Bharathi Institute of Technology (A)

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 VLSI DESIGN UNIT V Syllabus
UNIT-V : Sub systems Design and Testing:
Memories: 1T, 3T Dynamic RAM Cell, 6T Static RAM Cell. NOR and NAND based ROM Memory
Design. Introduction to CPLD and FPGA.
Testing: Introduction to Testing, Fault models (stuck - at 1 and stuck - at 0). Path sensitization and
D-Algorithm, Controllability, Observability. Introduction to SoC and ASIC design.

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 Semiconductor memories
• Semiconductor memories are most often classified on the basis of access
patterns, memory functionality and the nature of the storage mechanism.
• Based on the access patterns, they can be classified into random access and
serial access memories.
• A random access memory can be accessed for read/write in a random fashion.
• On the other hand, in serial access memories, the data can be accessed only in a
serial fashion.
• FIFO (First In First Out) and LIFO (Last In Last Out) are examples of serial
memories.
• Most of the memories fall under the random access types.

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 Semiconductor memories
• Based on their functionalities, memory can be broadly classified into Read/Write
memories and Read-only memories.
• As the name suggests, Read/Write memory offers both read and write
operations and hence is more flexible.
• RAM allows writing of data bits in the memory array as well as reading of stored
data bits.
• The main characteristic of RAM is that any cell in the memory array can be
accessed with nearly equal access time.
• Based on the operation type of data storage cells, RAMs are classified in to two
main categories: SRAM (Static RAM) and DRAM (Dynamic RAM).
• A Read-only memory on the other hand encodes the information into the circuit
topology. Since the topology is hardwired, the data cannot be modified; it can
only be read.
• However ROM structures belong to the class of the nonvolatile memories.
Removal
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 Random Access Memory

• Static RAMS(SRAM): Stored information depends on the state of

transistor, and it requires continuous power supply. Faster and
consumes more power compared to DRAM. Used in caches and high-
speed registers.
• Dynamic RAMS (DRAM): Stored information depends on charge in
capacitor and it does not require continuous power supply but the
charge in the capacitor must be refreshed after a particular interval of
time).
 Static RAM
• SRAM consists essentially of internal latches that store the binary information.
• The stored information remains valid as long as power is applied to the unit.
• SRAM is easier to use and has shorter read and write cycles.
• Low density,
• low capacity,
• high cost,
• high speed,
• high power consumption.
 Dynamic RAM
• DRAM stores the binary information in the form of electric charges on capacitors.
• The capacitors are provided inside the chip by MOS transistors.
• The capacitors tends to discharge with time and must be periodically recharged by
refreshing the dynamic memory.
• DRAM offers reduced power consumption and larger storage capacity in a single
memory chip.
• High density,
• high capacity,
• low cost,
• low speed,
• low power consumption.
Architecture of a Random Access Memory (RAM)
1.Row Decoder (Left - Blue Block)
1. Takes N input address lines to select one of 2^N rows in the memory array.
2. Activates a specific row by enabling the wordline connected to the RAM cells in that row.
2.RAM Cells (Middle - Green Blocks)
1. Each RAM cell stores one bit of data.
2. Arranged in a matrix of rows and columns.
3.Column Decoder (Bottom - Orange Block)
1. Takes M input address lines to select one of 2^M columns.
2. Helps in reading or writing data to a specific memory cell.
4.Outputs (Right Side - Blue Lines)
1. The selected memory location outputs data.
2. The total number of output lines is 2^M.

•The row decoder selects a row based on the input address.

•The column decoder selects a column based on another part of the address.
•The intersection of the selected row and column determines the RAM cell being accessed.
•The stored data is then sent to the output lines.
 1T DRAM (One-Transistor DRAM)
• In DRAM, the binary data is stored in the parasitic capacitor discharges with time.
• Which In order to retain the stored data, the capacitor must be charged periodically.
• This operation is called Dynamic Refreshing of DRAM.
• DRAM can be implemented using 1T, 3T, 4T.
• Different DRAM architectures use different numbers of transistors (T) per memory cell.
 1T DRAM (One-Transistor DRAM)

• A DRAM memory circuit uses storage on a capacitor to represent binary data values .
• Dynamic RAM gets its name because the charge stored in the capacitor cell leaks off with
time the stored value to be dynamic.
• To prevent loss of data, the voltage on the capacitor must be sampled and restored a specific
time period. This sample and restore operation is called as memory refresh.
A 1T DRAM cell consists of:
•Word Line (WL) → The output of the row decoder. It activates the transistor during
read/write operations.
•Bit Line (BL) → The output of the column decoder. It is used to write data into or read data
from the DRAM cell.
•NMOS Transistor →
•Gate is connected to the word line (WL).
•Drain is connected to the bit line (BL).
•Source is connected to one plate of the storage capacitor.
•Cell Capacitor (Cc) → Stores the charge representing a binary 0 or 1.
•Bit Line Capacitance (CB) → Represents parasitic capacitance of the bitline.

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Write Operation
Activate Word Line (WL) → WL goes high, turning on the NMOS transistor.
Store Charge in Capacitor (Cc):
To write 1: A high voltage is applied to the bitline, and the charge is stored in Cc.
To write 0: A low voltage is applied to the bitline, and Cc is discharged.
Deactivate Word Line (WL) → WL goes low, turning off the NMOS transistor, trapping the charge
in Cc.

Read Operation
Activate Word Line (WL) → WL goes high, turning on the NMOS transistor. Connects the
capacitor to the bit line.
On a read, the bit line CB is first precharged to Vdd/2. When the word line rises the capacitor CC
can shares its voltage v with bit line capacitor CB.
If v>vdd/2 the sense amplifier sense the output voltage and sends bit line output = 1
If v< vdd/2 then bit line output = 0;

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Write Operation
Activate Word Line (WL) → WL goes high, turning on the NMOS transistor.
Store Charge in Capacitor (Cc):
To write 1: A high voltage is applied to the bitline, and the charge is stored in Cc.
To write 0: A low voltage is applied to the bitline, and Cc is discharged.
Deactivate Word Line (WL) → WL goes low, turning off the NMOS transistor, trapping the charge
in Cc.

Read Operation
Activate Word Line (WL) → WL goes high, turning on the NMOS transistor. Connects the
capacitor to the bitline.
On a read the bit line CB is first precharged to Vdd/2. When the word line rises the capacitor CC
can shares its charge with bit line.
Charge Sharing with Bit Line (BL):
If Cc was charged (1) → Some charge flows to the bitline, increasing BL voltage.
If Cc was discharged (0) → No charge flows, and BL remains low.
Sense Amplifier Detects the Voltage → Determines if the stored value was 1 or 0.
Restoration
28 April 2025(Refresh Needed) → Since reading discharges Cc, it must be rewritten if the
15 value
 3T Dynamic RAM Cell

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 6T Static RAM Cell
• Static Random Access Memory (SRAM), is a type of semiconductor memory
frequently employed in electronic, microprocessor, and general computing
applications.
• The memory circuit is said to be static if the stored data can be retained
indefinitely (as long as a sufficient voltage is provided ) without any need for
periodic refresh operation.
• The term ``random access'' means that in an array of SRAM cells each cell can
be read or written in any order, no matter which cell was last accessed.
• Because SRAM does not require periodic refreshment while DRAM does, has
the advantage of providing greater performance.
• SRAM is more expensive and less dense than DRAM.

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 6T Static RAM Cell
The 6T SRAM cell consists of six transistors:
• Two cross-coupled inverters (P1, P2, N1, N2) forming a bistable latch for data storage.
• Two access transistors (N3, N4) controlled by the word line (WL) for read and write
operations.

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 Simplified ckt of 6T SRAM cell

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 Standby Mode (the circuit is idle)
• In standby mode word line is not asserted (word line=0), so
pass transistors N3 and N4 which connect 6T cell from bit lines
are turned off.
• It means that cell cannot be accessed. The two cross coupled
inverters will continue to feed back each other as long as they
are connected to the supply, and data will hold in the latch.

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 Read Mode (the data has been requested)
The read operation retrieves the stored data without altering it.
Step 1: The bit lines (Bit, Bit_bar) are precharged to a HIGH voltage (VDD/2). This ensures that even a small
change in voltage can be easily detected by the sense amplifier.
Step 2: The word line (WL) is activated (HIGH), enabling access transistors (N3 and N4). This connects the
internal nodes (Q and Q') to the Bit and Bit_bar lines.
Step 3: Depending on the stored value:
Case 1: Stored Value Q = 1 (VDD), Q' = 0 (GND)
Stored state:
Q = 1, meaning N1 is OFF, and P1 is ON (P1 pulls Q to VDD).
Q' = 0, meaning N2 is ON, and P2 is OFF (N2 pulls Q' to GND).
When WL = HIGH (Word Line Activated):
Access transistor N3 (connected to Bit) turns ON.
Access transistor N4 (connected to Bit_bar) turns ON.
Effect on Bit and Bit_bar lines:
Since Q = VDD, and N3 is ON, the Bit line remains HIGH (VDD) or slightly increases.
Since Q' = GND, and N4 is ON, N2 provides a discharge path to GND, causing Bit_bar to drop slightly.
Final Outcome:
Bit remains HIGH (or slightly increases).
Bit_bar discharges slightly.
The sense amplifier detects this difference and reads Q = 1.
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 Read Mode (the data has been requested)
Case 2: Stored Value Q = 0 (GND), Q' = 1 (VDD)
Stored state:
Q = 0, meaning N1 is ON, and P1 is OFF (N1 pulls Q to GND).
Q' = 1, meaning N2 is OFF, and P2 is ON (P2 pulls Q' to VDD).
When WL = HIGH (Word Line Activated):
Access transistor N3 (connected to Bit) turns ON.
Access transistor N4 (connected to Bit_bar) turns ON.
Effect on Bit and Bit_bar lines:
Since Q = GND, and N3 is ON, N1 provides a discharge path to GND, causing Bit to drop
slightly.
Since Q' = VDD, and N4 is ON, the Bit_bar remains HIGH (VDD) or slightly increases.
Final Outcome:
Bit discharges slightly.
Bit_bar remains HIGH (or slightly increases).
The sense amplifier detects this difference and reads Q = 0.
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 Write Mode (updating the contents)
The write operation in a 6T SRAM cell involves forcing the desired data (0 or 1) into the storage nodes (Q and Q').
This is achieved by overpowering the cross-coupled inverters through the bit-lines (Bit, Bit_bar) and access
transistors (N3, N4).
Initial State (Before Write)
Case1: the cell was previously storing '0' (Q = 0, Q' = 1).
This means:
N1 is ON (pulling Q to GND), P1 is OFF
N2 is OFF, P2 is ON (pulling Q' to VDD)
During Write '1' (WL = HIGH, Bit = VDD, Bit_bar = 0V)
Access transistors (N3, N4) turn ON, connecting:
Bit (VDD) to Q (through N3)
Bit_bar (0V) to Q' (through N4)
Q is forced to VDD, which turns ON N2 and turns OFF P2.
Q' is pulled to 0V, which turns ON P1 and turns OFF N1.
After Write (WL = LOW, Data Stored)
The cell is now in the new stable state: Q = 1, Q' = 0.
The cross-coupled inverters reinforce this state:
P1 remains ON, keeping Q at VDD
N2 remains ON, keeping Q' at GND
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 Write Mode (updating the contents)
Case2: the cell was previously storing '1' (Q = 1, Q' = 0).
This means:
N1 is OFF, P1 is ON (pulling Q to VDD)
N2 is ON (pulling Q' to GND), P2 is OFF
During Write '0' (WL = HIGH, Bit = 0V, Bit_bar = VDD)
Access transistors (N3, N4) turn ON, connecting:
Bit (0V) to Q (through N3)
Bit_bar (VDD) to Q' (through N4)
Q is forced to 0V, which turns ON N1 and turns OFF P1.
Q' is pulled to VDD, which turns ON P2 and turns OFF N2.
After Write (WL = LOW, Data Stored)
The cell is now in the new stable state: Q = 0, Q' = 1.
The cross-coupled inverters reinforce this state:
N1 remains ON, keeping Q at GND
P2 28remains
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ON, keeping Q' at VDD 27
 Semiconductor ROM
• Read only memories are used to store constants, control information and program
instructions in digital systems.
• They may also be thought of as components that provide a fixed, specified binary output for
every binary input.
• The read only memory can also be seen as a simple combinational Boolean network, which
produces a specified output value for each input combination, i.e. for each address.
• Thus storing binary information at a particular address location can be achieved by the
presence or absence of a data path from the selected row (word line) to the selected column
(bit line), which is equivalent to the presence or absence of a device at that particular
location.
• The two different types of implementations of ROM array are:
• NOR-based ROM array
• NAND-based ROM array

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 NOR based ROW Decoder
•A NOR-based row decoder is used in ROM (Read-Only Memory) to activate specific word
lines based on address inputs.
•It utilizes NOR gates to generate the output word lines, which then select the corresponding
row in the ROM array.
•Inputs: Two address bits, A₁ and A₂.
•Outputs: Four word lines, R₁, R₂, R₃, and R₄, each corresponding to a different address.
•Logic Used: Each word line is generated using the NOR function of the address inputs.

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 4bit x 4bit NOR based ROM Array
Each column consists of a pseudo-nMOS
NOR gate driven by some of the row
signals, i.e., the word lines.

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 4bit x 4bit NOR based ROM Array

One word line “Ri” is activated by

raising its voltage to VDD
Logic “1” is stored: Absent transistor
Logic “0” is stored: Present transistor
To reduce static power consumption, the
pMOS can be driven by a periodic pre-charge
signal.

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 4bit x 4bit NOR based ROM Array

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 4bit x 4bit NOR based ROM Array

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 NAND based ROM Array
• In this types of ROM array which is shown in Figure, each bit line consists of a depletion-load
NAND gate, driven by some of the row signals, i.e. the word lines.
• In normal operation, all word lines are held at the logic HIGH voltage level except for the
selected line, which is pulled down to logic LOW level.
• If a transistor exists at the cross point of a column and the selected row, that transistor is
turned off and column voltage is pulled HIGH by the load device.
• On the other hand, if no transistor exists (shorted) at that particular cross point, the column
voltage is pulled LOW by the other nMOS transistors in the multi-input NAND structure.
• Thus, a logic "1"-bit is stored by the presence of a transistor that can be deactivated, while a
logic "0"-bit is stored by a shorted or normally ON transistor at the cross point.

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 4bit x 4bit NAND based ROM Array
• All word lines
are kept at logic
“1” level, except
the selected line
pulled down by
“0” level.
• Logic “0” is stored:
Absent transistor
Logic “1” is stored:
Present transistor

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 Introduction: Programmable Logic Device
An IC that contains large numbers of gates, flip-flops, etc. that can be configured
by the user to perform different functions is called a Programmable Logic Device
(PLD).
(OR)
PLDs are semiconductor devices that can be programmed to obtain required
logic function ( The internal logic gates and/or connections of PLDs can be
changed/configured by a programming process)
Because of the advantage of re-programmability, they have replaced special
purpose logic devices like logic gates, flip flops, counters and multiplexers in
many semicustom applications.
PLDs reduces design time and thus reduces time for the product to reach the
market. It consists of arrays of AND and OR gates, which can be programmed to
realize required logic function.
Device programmer blows fuses on the PLD to control each gate operation.
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 PLDs Classification
• PLDs can be broadly classified into Simple Programmable Logic Devices (SPLDs), Complex
Programmable Logic Devices (CPLDs), and Field-Programmable Gate Arrays (FPGAs).
• These classifications are based on the complexity, number of logic elements, and the
architecture of the device.
SPLDs (Simple Programmable Logic Devices):
• SPLDs are the simplest form of PLDs, designed to implement relatively straightforward logic
functions. Examples: Programmable Logic Arrays (PLAs), Programmable Array Logic (PAL).
CPLDs (Complex Programmable Logic Devices):
• CPLDs are more advanced than SPLDs, offering a higher number of logic gates and more
complex logic functions. Examples: Xilinx CoolRunner, Altera MAX series.
FPGAs (Field-Programmable Gate Arrays):
• FPGAs are the most powerful and flexible form of PLD, consisting of a large number of logic
blocks and programmable interconnections.
• Examples: Xilinx Spartan, Altera Cyclone, Intel Arria.
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 PLA
• The PLA consists of two programmable planes AND and OR (see Figure 1.13). The
AND plane consists of programmable interconnect along with AND gates. The OR
plane consists of programmable interconnect along with OR gates
 PAL
• The PAL is similar to the PLA architecture, but now there is only one programmable
plane, the AND plane, and the AND gate programmable plane is retained (see Figure
1.14). This architecture is simpler than the PLA and removes the time delays
associated with the programmable OR gate plane interconnect, hence producing a
faster design.
 PROM architecture
PROM is a type of ROM, where the data can be stored and the stored data can be
changed by reprogramming the device. This is done either by the PROM programmer
or by simply burning the fuses in the PROM.
PROM consists of fixed AND array and programmable OR array. The block diagram of
PROM is shown below. It has n inputs and m outputs. For n input variables, there are
2n distinct addresses. In simple words, we can say that the fixed AND array acts as a
decoder(n:2n).
 Complex Programmable Logic Devices (CPLDs)
• As integrated circuit technology continues to improve, more and more gates can be placed
on a single chip. This has allowed the development of complex programmable logic devices .
• Instead of a single PAL or PLA on a chip, many PALs or PLAs can be placed on a single CPLD
chip and interconnected.
• When storage elements such as flip-flops are also included on the same IC, a small digital
system can be implemented with a single CPLD.
The basic architecture of a Xilinx XCR3064XL CPLD
1. This CPLD has four function blocks, and each block has 16 associated macrocells (MC1, MC2,
. . .).
2. Each function block is a programmable AND-OR array that is configured as a PLA. Each
macrocell contains a flip-flop and multiplexers that route signals from the function block to
the input-output (I/O) block or to the interconnect array (IA).
3. The IA selects signals from the macrocell outputs or I/O blocks and connects them back to
function block inputs. Thus, a signal generated in one function block can be used as an input
to any other function block.
4. The I/O blocks provide an interface between the bi-directional I/O pins on the IC and the
interior of the CPLD.
CPLD Function Block and Macrocell
(A Simplified Version of XCR3064XL)
5. A signal generated in the PLA is routed to an I/O pin through a macrocell. Any of the 36
outputs from the IA (or their complements) can be connected to any inputs of the 48 AND
gates. Each OR gate can accept up to 48 product term inputs from the AND array.
6. The macrocell logic in this diagram is a simplified version of the actual logic. The first MUX
(1) can be programmed to select the OR-gate output or its complement. The MUX (2) at the
output of the macrocell can be programmed to select either the combinational output (G)
or the flip-flop output (Q).
7. This output goes to the interconnect array and to the output cell. The output cell includes a
three-state buffer (3) to drive the I/O pin. The buffer enable input can be programmed from
several sources.
8. When the I/O pin is used as an input, the buffer must be disabled.
 Field-Programmable Gate Array (FPGA)
• An FPGA is an IC that contains an array of identical logic cells with programmable
interconnections.
• The user can program the functions realized by each logic cell and the connections between
the cells.
• The interior of the FPGA consists of an array of logic cells, also called configurable logic blocks
(CLBs).
• The array of CLBs is surrounded by a ring of input-output interface blocks.
• These I/O blocks connect the CLB signals to IC pins. The space between the CLBs is used to
route connections between the CLB outputs and inputs.
Structure of an FPGA
Simplified Configurable Logic Block (CLB)
1. This CLB contains two function generators, two flip-flops, and various multiplexers for
routing signals within the CLB.
2. Each function generator has four inputs and can implement any function of up to four
variables.
3. The function generators are implemented as lookup tables (LUTs). A four input LUT is
essentially a reprogrammable ROM with 16 1-bit words.
4. This ROM stores the truth table for the function being generated.
5. The H multiplexer selects either F or G depending on the value of H1. The CLB has two
combinational outputs (X and Y) and two flip-flop outputs (XQ and YQ).
6. The X and Y outputs and the flipflop inputs are selected by programmable multiplexers.
7. The select inputs to these MUXes are programmed when the FPGA is configured. For
example, the X output can come from the F function generator, and the Y output from the H
multiplexer.
 CMOS Testing
• A die, in the context of integrated circuits, is a small block of semiconducting material on
which a given functional circuit is fabricated.
• A chip with no manufacturing defect is called a good chip
• Fraction (or percentage) of good chips produced in a manufacturing process is called the
yield.
• Yield is denoted by symbol Y
• Cost of a chip= Cost of fabricating and testing a wafer/(Yield x Number of chip sites on the
wafer)
 Need for testing
• Due to complexity of the manufacturing process not all die on a wafer correctly operate.
• Small imperfections in starting material, processing steps, or in photo masking may result in
bridged connections or missing features.
• Testing a die can occur at
– Wafer : Die is tested at wafer level/Production Test
– Packaged chip: Die is separated out from the wafer and packaged and again tested with test vectors. →
Final test/Packaged level test
– Board: At the customer end, the chip is placed in board and board is tested→ Board level test
– System: If any malfunctions sent back to manufacturer. In System level test, board is placed in the
system and checked if system works as specified
– Field: last stage of testing is done at field level, when an end-user tests the system while using a system.
• Cost to detect a fault (per chip)
– Wafer: $0.01-$0.1
– Packaged chip: $0.1-$1
– Board: $1-$10
– System: $10-$100
– Field: $100-1000
 Test Principles
1. A critical factor in all LSI & VLSI designs is the in to incorporate method of
Testing circuits. For testing a circuit exhaustively large number of test
vectors are needed, which is not feasible even at very high speed.
2. Fortunately the number of non-functional nodes on a chip is smaller than
the number of states.
3. A manufacturing test engineer must be able to detect any defects node
with out requiring so many patterns.
4. Figure 1 , show's a combinational circuit within inputs. To do this circuit
exhaustively a sequence of inputs (test vectors must be applied &
observed to fully exercise the circuit.
5. This combinational circuit is converted into a sequential circuit with
adding of m-stage elements as shown in fig 2. The state of the circuit is
determined by the inputs & the previous state. A minimum of 2^(m+n)
test vectors are required to be applied to test the circuit.
 Test Principles
Fault model
 Observability and Controllability
Automatic Test Pattern Generation (ATPG)
Delay fault modeling
Fault coverage
 Fault models
Fault model is a model for how faults occur and their impact on
circuits
Types of fault models
Stuck-at fault
 Stuck-at-1 (s-a-1)
Stuck-at-0 (s-a-0)
Physical fault
Short circuit fault
Open circuit fault
 Stuck-at fault
• A faulty gate input is modeled as a “stuck at zero” or “stuck at one”.
• The given line has a constant value (0/1) independent of other signal values in the circuit (
or The faulty line is permanently set to 0 or 1 “stuck-at”)
• Nodes “stuck-at” 0 or 1, i.e. shorted to GND or VDD
Stuck -Line model
 Open circuit fault and Short circuit fault
MOS transistor is considered an ideal switch and two types of faults are modelled:
Stuck-open -- a single transistor is permanently stuck in the open state.
Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.
Open circuit fault and Short circuit fault
 Observability and Controllability
Two terms are used in digital testing:
These terms were defined with an attempt to quantify the ease (or
difficulty) of testing a digital circuit.
• Controllability: it is a measure of how easily any node in the circuit
can be controlled : by setting it to 0 or 1 through primary inputs.
• Observability: it is a measure of how easily the state at any node can
be determined through primary outputs.
Observability
• Ease of observing a node by watching external output pins of the chip
• This metric is relevant when you want to measure the output of a gate within a larger
circuit to check that it operates correctly.
• Given the limited number of nodes that can be directly observed, it is the aim of good
chip designers to have easily observed gate outputs.
• Adoption of some basic design for test techniques can aid tremendously in this
respect.
• Ideally, you should be able to observe directly or with moderate indirection (i.e., you
may have to wait a few cycles) every gate output within an integrated circuit.
• While at one time this aim was hindered by the expense of extra test circuitry and a
lack of design methodology.
Controllability: ease of setting a node to 0 or 1 by driving input pins of the chip.
• This metric is of importance when assessing the degree of difficulty of testing a particular
signal within a circuit.
• An easily controllable node would be directly settable via an input pad.
• A node with little controllability, such as the most significant bit of a counter, might require
many hundreds or thousands of cycles to get it to the right state.
• Often, you will find it impossible to generate a test sequence to set a number of poorly
controllable nodes into the right state. It should be the aim of good chip designers to make all
nodes easily controllable.
• In common with observability, the adoption of some simple design for test techniques can aid
in this respect tremendously.
• Making all flip-flops resettable via a global reset signal is one step toward good controllability.
• Combinational logic is usually easy to observe and control.
• Finite state machines can be very difficult, requiring many cycles to enter desired state
Especially if state transition diagram is not known to the test engineer.
 Fault coverage
• A measure of goodness of a test program is the amount of fault
coverage it achieves
• The total number of nodes found fault, when set to 1 or 0, do result in
the detection of the fault, divided by the total number of nodes in the
circuit, is called the percentage-fault coverage.
 ATPG
• Automatic Test Pattern Generation (ATPG) tools produce a good
set of vectors for each block of combinational logic.
• Scan chains are used to control and observe the blocks.
• Complete coverage requires a large number of vectors, raising the
cost of test
 Path sensitization Method
• The aim of this method is to generate a Test Vector.
• It is based on the fact that, to detect a stuck at fault, we need to
induce a value opposite to that of line which is suspected to be
stuck at line.
• Then propagate the error to one of the output line.
• If the output is different from the expected output in a fault free
case, then we say that fault is present.
 Path sensitization Method
Three steps are required to find test vectors through this method
a) Fault Excitation : Apply value opposite to the stuck value
b) Fault propagation : Sensitize a path to observe the effect at the
output.
c) Back tracking : By seeing the output predict the inputs
What is Fault Excitation?
Fault Excitation means applying an input to the circuit such that a fault (stuck-at-1 or stuck-
at-0) shows a difference in behavior from the fault-free (normal) circuit.
s-a-1 (stuck-at-1):
A line or node is permanently stuck at logic 1, regardless of the intended signal.
To detect this:
We must apply logic 0 (non-faulty case) to the node.
If we observe logic 1 (faulty case) instead, the fault is detected.
s-a-0 (stuck-at-0):
A line or node is permanently stuck at logic 0.
To detect this:
We apply logic 1 (non-faulty case).
If we observe logic 0 (faulty case), the fault is detected.
Fault is excited because we applied logic 1 to B, but it’s stuck at 0
What Is Path Sensitization?
a fault propagation technique helps detect faults by sensitizing (activating) and observing them
at the output.
To detect a fault, need to:
Excite the fault (apply the opposite value of the stuck fault)
Sensitize the path from the fault location to the output
Observe the effect at the output
Example 1
Fault excitation
Fault propagation
Back tracking
Back tracking
Example 2
Fault excitation
Fault propagation
Back tracking
Back tracking
Back tracking
 Deterministic Test Pattern Generation ( D-Algorithm of ATPG)

D-Algorithm is formal version of path sensitization method.

Fewer terms need to be known, to solve the question through D-Algorithm.
1. Singular Cover (SC)
2. Propagation D-Cube (PDC)
3. Primitive D-Cube of a fault (PDCF)
 Singular Cover
• Singular Cover of logic gate is the compact form of truth table.
• This is done using don’t cares (x). Each row in the singular cover is
termed as "Singular Cube".

The above singular cover of the

AND gate has three singular
cubes.
 Primitive D-cube of a Fault
• D-cubes represent the input-output behavior of the good and faulty
circuits.
• Primitive D-cube of a Fault (PDCF) is used to specify the minimum
input conditions required at inputs of a gate to produce an error at its
output. This is used for fault activation.
• PDCF can be derived from the intersection of singular covers of gates
in faulty and non-faulty conditions having different outputs.
• For faulty AND gate, the output is always stuck-at-0 independent of its input; hence its
singular cover has only one row with inputs (a, b) as don’t cares.
• Now, we intersect the singular cubes of the non-faulty and faulty circuits.
• For PDCF we need to intersect only those columns for which output is different for non-
faulty and faulty circuits.
• Since for faulty circuits, we only have one singular cube {x, x, 0}; we need to intersect it
with a singular cube of the non-faulty circuit having the opposite output value (i.e. logic-
1). The singular cube {1, 1, 1} perfectly fits this criterion.
• {x, x, 0} ∩{1, 1, 1} = {1, 1, D’}

• Finally, PDCF of this faulty AND gate is {a, b, out} = {1, 1, D’}.
 Propagation D-Cube
• Propagation D-cubes (PDCs) of a gate causes the output of the gate to depend upon the
minimum number of its specified inputs.
• It is used to propagate D or D’ from a specified input to the output. Propagation D-Cubes can
be derived from the intersection of singular cubes of gates of opposite output values.
Example:
• Here’s the truth table of an OR gate. To generate the PDC, we find the singular cover for the
OR gate.
Now, we intersect the singular cubes of every possible combination(s) with opposite output
values. Intersecting the singular cubes of row1 and row2, also row1 and row3 serves the
purpose.
{0, 0, 0} ∩ {1, x, 1} = {D’, 0, D’}
{0, 0, 0} ∩ {x, 1, 1} = {0, D’, D’}
 Introduction to SoC and ASIC design
• An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a
particular use, rather than intended for general-purpose use. For example, a chip designed
solely to run a cell phone is an ASIC.
• Modern ASICs often include entire 32-bit processors, memory blocks
including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often
termed a SoC (system-on-a-chip).
• Designers of digital ASICs use a hardware description language (HDL), such
as Verilog or VHDL, to describe the functionality of ASICs.
• SoC is a collection of components and/or subsystems (designed as IPs, ASICs) interconnected
to perform the specified functions. Entire system is built on a single piece of silicon.
• SoC includes a processor, memory, DSP Cores, IO devices, interfaces to external circuitry, and
custom IPs as Verilog or VHDL modules.
• SoC consists of Very large transistor counts on a single IC. Mixed technologies, mixed design
on the same chip are commonly used.
• They include – Digital, analog, FPGA, full custom, semi-custom, etc. A SoC usually contains
one or more processors and co-processors, internal memory and memory controllers for
external memory, buses/interconnect architectures such as AMBA, peripherals (timer,
interrupt controller, etc.), I/O channels and many more.
• Thus SoC is essentially a mixture of ASIC, including full-custom and semi-custom (standard
cells), reusable Intellectual Property (IP) blocks (also called macro, hard macro, cores) as
shown in below diagram.
• IP core based design approach mainly intended for reducing design complexity and time to
market.
• There are different IP cores supplied by different vendors in different technologies of different
specifications. Customizable soft cores provides essential set of preverified parameters to
configure according to the customer requirement Interface logic generally support standard
buses to ease integration.
• Bus-based architectures such as IBM core-connect, Motorola IP-bus, ARM's advanced
microcontroller bus architecture (AMBA), etc. that facilitate core-based SoC design.
 Difference between FPGA and ASICs
• ASIC is customized for a specific application’s need and is suited for bulk production
whereas FPGA can be programmed in the field and is not suited for bulk production.
FPGA ASIC

Field Programmable Gate

Full Form Application-Specific Integrated Circuit
Array
Design Process Simple design process. Long and complex design process.
Faster “time-to-market”
Production Time Longer “time-to-market” product.
product.
Speed Slower than ASIC. Fast.
Reusability and Flexibility Reusable and flexible. Not reusable and not flexible.
Wastage Un-avoidable No wastage of hardware.
When the required numbers
Best suited When the required numbers are large.
are less.
 Types of ASICs
• ASICs (Application-Specific Integrated Circuits) can be broadly classified into two types:
full custom ASICs and semi-custom ASICs.
• Full custom ASICs: These are ASICs that are designed from scratch for a specific
application.
• Every aspect of the chip, from the logic gates to the layout of the circuit, is custom-made
to meet the precise requirements of the intended application.
• Full custom ASICs offer the highest performance and the lowest power consumption, but
they are also the most expensive and time-consuming to design and manufacture.
• They are typically used in applications where the volume is high enough or the
performance requirements are strict enough to justify the additional cost and effort.
 Types of ASICs
• Semi-custom ASICs: These are ASICs that use pre-designed building blocks called
“intellectual property” (IP) cores, which can be customized to fit the requirements of a
specific application.
• These ASICs are less complex and time-consuming to design than full custom ASICs, and
they are also more cost-effective.
• However, they may not provide the same level of performance and power efficiency as
full custom ASICs.