VLSI DESIGN (22ECC24)

Dr.P.Anuradha
Associate Professor
ELECTRONICS & COMMUNICATION ENGINEERING
Chaitanya Bharathi Institute of Technology (A)

10 February 2025 1
VLSI DESIGN Syllabus
UNIT-I : Advanced Verilog HDL: Review of behavioral modelling. Functions and tasks. Switch
level Modelling, User Define Primitives (UDP), Design of Mealy and Moore state models using
Verilog, Logic Synthesis, RTL to GDS flow, Synthesis Design flow, Gate level Netlist.

UNIT-II : IC fabrication Steps: Process steps in IC fabrication. Crystal growth and wafer
preparation - Czochralski process –apparatus silicon shaping, slicing and polishing- Diffusion, Ion
implantation - Annealing process - Oxidation process - Lithography - Photolithography, electron
beam and xray lithography - Chemical Vapour Deposition (CVD) - epitaxial growth-reactors-
metallization and packaging.

UNIT-III : MOS and CMOS Circuits and Design Process: Introduction to MOS Technology, Basic
MOS Transistor action: Enhancement and Depletion Modes. Basic electrical properties of MOS,
Threshold voltage and Body Effect. Design of MOS inverters with different loads. Basic Logic
Gates with CMOS: INVERTER, NAND, NOR, AOI and OAI gates.
Scaling of Technology, MOS Layers, Stick diagrams, Lambda based Design rules and Layout
diagrams. 2
UNIT-IV: Designing of CMOS Circuits:
Sub system design Principles, Dynamic logic, BiCMOS inverter, pass transistors, Latch-up in
CMOS Circuits, Domino logic, Transmission gate logic circuits, Multiplexer and D flip flop using
Transmission gates. Design of complex circuits using AOI and OAI.

UNIT-V : Sub systems Design and Testing:

Memories: 1T, 3T Dynamic RAM Cell, 6T Static RAM Cell. NOR and NAND based ROM Memory
Design. Introduction to CPLD and FPGA.
Testing: Introduction to Testing, Fault models (stuck - at 1 and stuck - at 0). Path sensitization and
D-Algorithm, Controllability, Observability. Introduction to SoC and ASIC design.

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Text Books:
1. Samir Palnitkar,“Verilog HDL:A guide to Digital design and synthesis”, 2/e, Pearson
Education, 2008.
2. Kamran Eshraghian, Douglas A. Pucknell, Sholeh Eshraghian, “Essentials of VLSI circuits
and systems”, PHI, 2011.
3. Neil HEWeste, David Harris, Ayan Banerjee, “CMOS VLSI Design–A circuit and System
Perspective”, 3/e, Pearson Education,2006.
4. Parag K Lal, “ Fault Tolerant and Fault Testable Hardware Design ” , BS Publications, 2020
5. S.M. Sze, VLSI Technology, McGraw-Hill, 2nd Edition, 1988.
Suggested Reading:
1. Michael D. Ciletti, “Advanced Digital Design with Verilog HDL”, PHI, 2005.
2. John P. Uyemura, “Introduction to VLSI Circuits and systems”, John Wiley & Sons, 2011.
3. Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design,
McGraw-Hill, 1998.
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Course Outcomes:
Upon completion of this course, students will be able to:
1. Model a digital design using Advanced Verilog HDL constructs.
2. Analyze the characteristic behavior of MOSFET and discuss CMOS circuit Design Process
3. Explain various process steps involved in IC fabrication.
4. Design various NMOS and CMOS based logic circuits.
5. Discuss the concepts of subsystem designs and Testing.

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 Introduction to Verilog HDL
• Verilog is a Hardware Description Language (HDL).
• It enables engineers to describe hardware at various abstraction levels, such as
behavioral, structural, and gate-level, and is widely used in designing ASICs, FPGAs, and
digital circuits.
• Designs, which are described in HDL are independent of technology, very easy for
designing and debugging, and are normally more useful than schematics, particularly
for large circuits.
• It is similar in syntax to the C programming language. Designers with C programming
experience will find it easy to learn Verilog HDL.
• Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus,
a designer can define a hardware model in terms of switches, gates, RTL, or behavioral
code. Also, a designer needs to learn only one language for stimulus and hierarchical
design.
• Most popular logic synthesis tools support Verilog HDL. This makes it the language of
choice for designers.
7
 Basic Concepts of Verilog HDL
Lexical Conventions
The basic lexical conventions used by Verilog HDL are similar to those in the C
programming language. Verilog contains a stream of tokens. Tokens can be
comments, delimiters, numbers, strings, identifiers, and keywords. Verilog HDL is
a case-sensitive language. All keywords are in lowercase.
Whitespace
Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the whitespace.
Whitespace is ignored by Verilog except when it separates tokens.
Whitespace is not ignored in strings.
Comments
Comments can be inserted in the code for readability and documentation. There
are two ways to write comments.
A one-line comment starts with "//". Verilog skips from that point to the end of
line.
A multiple-line comment starts with "/*" and ends with "*/".
Multiple-line comments cannot be nested.
However, one-line comments can be embedded in multiple-line comments.
a = b && c; // This is a one-line comment
/* This is a multiple line comment */
/* This is /* an illegal */ comment */
/* This is //a legal comment */
Operators
Operators are of three types: unary, binary, and ternary.
Unary operators precede the operand. Binary operators appear between two
operands. Ternary operators have two separate operators that separate three
operands.
a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands
Number Specification
There are two types of number specification in Verilog: sized and unsized.
Sized numbers
Sized numbers are represented as <size> '<base format> <number>.
<size> is written only in decimal and specifies the number of bits in the number.
Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or 'B)
and octal ('o or 'O).
The number is specified as consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b,c,
d, e, f.
Only a subset of these digits is legal for a particular base. Uppercase letters are
legal for number specification.
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.
Unsized numbers
Numbers that are specified without a <base format> specification are decimal
numbers by default.
Numbers that are written without a <size> specification have a default number of
bits that is simulator and machine specific (must be at least 32).
23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number
• X or Z values
Verilog has two symbols for unknown and high impedance values.
These values are very important for modeling real circuits. An unknown value is
denoted by an x. A high impedance value is denoted by z.
12'h13x // This is a 12-bit hex number; 4 least significant bits unknown
6'hx // This is a 6-bit hex number
32'bz // This is a 32-bit high impedance number
An x or z sets four bits for a number in the hexadecimal base, three bits for a
number in the octal base, and one bit for a number in the binary base.
If the most significant bit of a number is 0, x, or z, the number is automatically
extended to fill the most significant bits, respectively, with 0, x, or z.
This makes it easy to assign x or z to whole vector. If the most significant digit is 1,
then it is also zero extended.
• Negative numbers
Negative numbers can be specified by putting a minus sign before the size for a
constant number.
Size constants are always positive. It is illegal to have a minus sign between <base
format> and <number>.
An optional signed specifier can be added for signed arithmetic.
-6'd3
4'd-2 // Illegal specification
• Underscore characters and question marks
An underscore character "_" is allowed anywhere in a number except the first
character.
Underscore characters are allowed only to improve readability of numbers and
are ignored by Verilog.
A question mark "?" is the Verilog HDL alternative for z in the context of
numbers.
The ? is used to enhance readability in the casex and casez statements
4'b10?? // Equivalent of a 4'b10zz
Strings
• A string is a sequence of characters that are enclosed by double quotes.
• The restriction on a string is that it must be contained on a single line, that is,
without a carriage return.
• It cannot be on multiple lines. Strings are treated as a sequence of one-byte ASCII
values.
"Hello Verilog World" // is a string
"a / b" // is a string
Identifiers and Keywords
• Keywords are special identifiers reserved to define the language constructs.
• Keywords are in lowercase.
• Identifiers are names given to objects so that they can be referenced in the
design.
• Identifiers are made up of alphanumeric characters, the underscore ( _ ), or the
dollar sign ( $ ).
• Identifiers are case sensitive. Identifiers start with an alphabetic character or an
underscore.
• They cannot start with a digit or a $ sign (The $ sign as the first character is
reserved for system tasks, which are explained later in the book).
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier
 Data Types
Value Set
Verilog supports four values to model the functionality of real hardware.
Nets
• Nets represent connections between hardware elements. Just as in real circuits, nets
have values continuously driven on them by the outputs of devices that they are
connected to.
• In Figure 3-1 net a is connected to the output of and gate g1. Net a will continuously
assume the value computed at the output of gate g1, which is b & c.
• Nets are declared primarily with the keyword wire. Nets are one-bit values by default
unless they are declared explicitly as vectors.
• The terms wire and net are often used interchangeably. The default value of a net is z
(except the trireg net, which defaults to x ).
• Nets get the output value of their drivers. If a net has no driver, it gets the value z.
wire a; // Declare net a for the above circuit
wire b,c; // Declare two wires b,c for the below circuit
wire d = 1'b0; // Net d is fixed to logic value 0 at declaration.
Registers
• Registers represent data storage elements. Registers retain value until another
value is placed onto them. Do not confuse the term registers in Verilog with
hardware registers built from edge-triggered flipflops in real circuits.
• In Verilog, the term register merely means a variable that can hold a value. Unlike
a net, a register does not need a driver.
• Verilog registers do not need a clock as hardware registers do.
• Values of registers can be changed anytime in a simulation by assigning a new
value to the register.
• Register data types are commonly declared by the keyword reg
Example 3-1 Example of Register
reg reset; // declare a variable reset that can hold its value
initial
begin
reset = 1'b1; //initialize reset to 1 to reset the digital circuit.
#100 reset = 1'b0; // after 100 time units reset is deasserted.
end

Registers can also be declared as signed variables. Such registers can be used for signed
arithmetic.
Example 3-2 shows the declaration of a signed register.

Example 3-2 Signed Register Declaration

reg signed [63:0] m; // 64 bit signed value
integer i; // 32 bit signed value
Vectors
Nets or reg data types can be declared as vectors (multiple bit widths). If bit width
is not specified, the default is scalar (1-bit).
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
reg clock; // scalar register, default
reg [0:40] virtual_addr; // Vector register, virtual address 41 bits wide

Vectors can be declared at [high# : low#] or [low# : high#], but the left number in
the squared brackets is always the most significant bit of the vector.
In the example shown above, bit 0 is the most significant bit of vector virtual_addr.
Parameters
Verilog allows constants to be defined in a module by the keyword parameter.
Parameters cannot be used as variables.
Parameter values for each module instance can be overridden individually at
compile time. This allows the module instances to be customized.
Parameter types and sizes can also be defined.
parameter port_id = 5; // Defines a constant port_id parameter
cache_line_width = 256; // Constant defines width of cache line parameter
signed [15:0] WIDTH; // Fixed sign and range for parameter
 Types of modeling
• Verilog HDL supports four kinds of modeling styles:
❖ Gate-level
❖ Structural
❖ Dataflow
❖ Behavioral
 Gate-Level Modeling
At gate level, the circuit is described in terms of gates (e.g., and, nand). Hardware design at
this level is intuitive for a user with a basic knowledge of digital logic design because it is
possible to see a one-to-one correspondence between the logic circuit diagram and the
Verilog description.
Gate Types
A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates as
predefined primitives. These primitives are instantiated like modules except that they are
predefined in Verilog and do not need a module definition. All logic circuits can be designed by
using basic gates. There are two classes of basic gates: and/or gates and buf/not gates.
26
 Gatelevel Modeling Example1: Combinational Logic (2-to-1 Multiplexer)

module mux2to1_gate ( input a, b, sel, output y);

wire not_sel, and1_out, and2_out;
not (not_sel, sel);
and (and1_out, a, not_sel);
and (and2_out, b, sel);
or (y, and1_out, and2_out);
endmodule
28
 Gate Delays
• In real circuits, logic gates have delays associated with them. Gate
delays allow the Verilog user to specify delays through the logic
circuits.

29
Turn-off delay
• The turn-off delay is associated with a gate output transition to the

high impedance value (z) from another value.

• If the value changes to x, the minimum of the three delays is

considered

30
Delay Example

31
Delay Example

32
33
 Structural Modeling
• Represents the design by interconnecting pre-defined modules (including gates or higher-
level modules).
• Defines circuits by instantiating and connecting existing modules.
• Focuses on the netlist and instantiation of lower-level modules.
• Mirrors the hardware implementation.
• Uses module instances, which can include gates, flip-flops, or even other structural blocks.
 Structural Modeling Example2: Combinational Logic (4-to-1 Multiplexer)

module mux4to1_struct ( input [3:0] in, input [1:0] sel, output y );

wire mux1_out, mux2_out; // Intermediate outputs
// Instantiate two 2-to-1 multiplexers
mux2to1_gate M1 (.a(in[0]), .b(in[1]), .sel(sel[0]), .y(mux1_out));
mux2to1_gate M2 (.a(in[2]), .b(in[3]), .sel(sel[0]), .y(mux2_out));
// Instantiate a final 2-to-1 multiplexer
mux2to1_gate M3 (.a(mux1_out), .b(mux2_out), .sel(sel[1]), .y(y));
endmodule
 Dataflow Modeling
• Dataflow Modeling is a method of representing a digital system in terms of data movement
between functional units and transformations applied to the data.
• Describes the design in terms of the flow of data between registers.
• Focuses on the logical behavior using continuous assignments.
• Uses the assign statement for continuous assignments.
• Often utilizes logical and bitwise operators.
 Data Modeling Example3: Combinational Logic (2-to-1 Multiplexer)

module mux2to1_dataflow ( input a, b, sel, output y );

assign y = (sel) ? b : a;
endmodule
 Delays in Data flow Modeling
• Delay values control the time between the change in a right-hand-side
operand and when the new value is assigned to the left-hand side.
• Three ways of specifying delays in continuous assignment statements are
regular assignment delay, implicit continuous assignment delay, and net
declaration delay.

40
 Regular Assignment Delay
• The first method is to assign a delay value in a continuous assignment statement.
• The delay value is specified after the keyword assign. Any change in values of in1 or in2 will result in
a delay of 10 time units before recomputation of the expression in1 & in2, and the result will be
assigned to out.
• If in1 or in2 changes value again before 10 time units when the result propagates to out, the values
of in1 and in2 at the time of recomputation are considered.
• This property is called inertial delay. An input pulse that is shorter than the delay of the assignment
statement does not propagate to the output.
• Ex: assign #10 out = in1 & in2; // Delay in a continuous assign
• When signals in1 and in2 go high at time 20, out goes to a high 10 time units later (time = 30)

41
 Implicit Continuous Assignment Delay
• An equivalent method is to use an implicit continuous assignment to specify both a delay and an
assignment on the net.

42
 Net Declaration Delay
• A delay can be specified on a net when it is declared without putting a
continuous assignment on the net. If a delay is specified on a net out,
then any value change applied to the net out is delayed accordingly.
Net declaration delays can also be used in gate-level modeling.

43
Dataflow model Example

44
Dataflow model Example

45
 Behavioral Modeling
• Behavioral modeling describes the behavior of the system using high-level constructs,
algorithmic way without specifying hardware details.
• Suited for testbenches and high-level design descriptions.
• Uses constructs like if-else, case, loops (for, while), always, initial and procedural blocks.
• always block: Key feature for sequential and combinational logic.
• Sensitivity list (@(...)) defines the conditions under which the block is executed.
• Useful for designing synchronous circuits where behavior depends on clock edges or reset
signals.
• During simulation of behavioral model, all the flows defined by the ‘always’ and ‘initial’
statements start together at simulation time ‘zero’.
• The initial statements are executed once, and the always statements are executed
repetitively. In this model, the register variables a and b are initialized to binary 1 and 0
respectively at simulation time ‘zero’.
• The initial statement is then completed and is not executed again during that simulation
run.
• This initial statement is containing a begin-end block (also called a sequential block) of
statements. In this begin-end type block, a is initialized first followed by b.
 Behavioral Modeling Syntax

1. always Block
The always block is the foundation of behavioral modeling. It executes based on its sensitivity
list.
2. Sequential Logic (Flip-Flops, Registers)
Synchronous behavior is modeled using clock signals.
3. Case Statement
Simplifies logic with multiple conditions.
4. Loops
Useful for describing iterative or repetitive logic.
 Behavioral Modeling Example4: Combinational Logic (2-to-1 Multiplexer)

module mux2to1 ( input a, b, sel, output reg y);

always @(*)
begin
if (sel)
y = b;
else
y = a;
end
endmodule

•@(*): Automatically includes all input signals in the sensitivity list.

 Behavioral Modeling Example5: D Flip-Flop

module d_flip_flop ( input d, clk, output reg q);

always @(posedge clk)
begin
q <= d;
end
endmodule

•@(posedge clk): Triggers the block on the positive edge of the clock.
•<=: Non-blocking assignment used for sequential logic.
 Behavioral Modeling Example6: 4-to-1 Multiplexer

module mux4to1 ( input [3:0] in, input [1:0] sel, output reg y);
always @(*)
begin
case (sel)
2'b00: y = in[0];
2'b01: y = in[1];
2'b10: y = in[2];
2'b11: y = in[3];
default: y = 0;
endcase •always block describes behavior and is executed whenever any signal
end in its sensitivity list changes.
endmodule •The @(*) syntax automatically includes all input signals (in, sel) in
the sensitivity list, ensuring proper updates.
Four bit Asynchronous Counter

51
 Behavioral Modeling Example6: Four bit Asynchronous Counter
module AsyncCounter4Bit ( input clk, input reset, output reg [3:0] Q );

// Always block to model the counter behaviour

always @(posedge clk or posedge reset) begin

if (reset) begin
Q <= 4'b0000; // Reset all outputs to 0
end
else begin
Q[0] <= ~Q[0]; // Toggle Q0 on every clock pulse
Q[1] <= Q[0] ? ~Q[1] : Q[1]; // Toggle Q1 when Q0 goes high
Q[2] <= (Q[0] & Q[1]) ? ~Q[2] : Q[2]; // Toggle Q2 when Q0 & Q1 are high
Q[3] <= (Q[0] & Q[1] & Q[2]) ? ~Q[3] : Q[3]; // Toggle Q3 when Q0, Q1 & Q2 are high
end
end

endmodule
 Behavioral Modeling Example6: Four bit Asynchronous Counter Testbench
module AsyncCounter4Bit_tb;
reg clk;
reg reset;
wire [3:0] Q;

// Instantiate the counter

AsyncCounter4Bit uut (
.clk(clk),
.reset(reset),
.Q(Q)
);

// Clock generation
initial begin
clk = 0;
forever #10 clk = ~clk; // Clock period of 20 time units
end
 Behavioral Modeling Example6: Four bit Asynchronous Counter Testbench
// Test sequence
initial begin
reset = 1; #15; // Apply reset
reset = 0; #200; // Release reset and observe counting
reset = 1; #10; // Reset again
reset = 0; #100; // Observe counting again
$stop;
end
endmodule
Four bit Asynchronous upcounter Simulation output
 Behavioral Modeling Example7: 4-to-2 Priority Encoder
module priority_encoder ( input wire [3:0] in, output reg [1:0] out,
output reg valid); // Indicates if any input is active
integer i; // Loop variable
always @(*)
begin
valid = 0; // Default: no active input
out = 2'b00; // Default: output position is 0
// Priority logic using a for loop
for (i = 3; i >= 0; i = i - 1) begin
if (in[i]) begin
out = i[1:0]; // Assign the index of the active input
valid = 1; // Indicate that a valid input was found
break; // Exit loop after the highest-priority input is found
end
end
end
endmodule
 Behavioral Modeling Example7: 4-to-2 Priority Encoder
`timescale 1ns / 1ps
module priority_encoder_tb;
// Testbench signals
reg [3:0] in; // 4-bit input
wire [1:0] out; // 2-bit output
wire valid; // Valid flag

// Instantiate the priority encoder module

priority_encoder uut (
.in(in),
.out(out),
.valid(valid)
);
 Behavioral Modeling Example7: 4-to-2 Priority Encoder
// Test sequence
initial begin
// Test case 1: No inputs active
in = 4'b0000;
#10; // Wait for 10 time units
$display("Test 1: in=%b, out=%b, valid=%b", in, out, valid);

// Test case 2: Lowest-priority input active

in = 4'b0001;
#10;
$display("Test 2: in=%b, out=%b, valid=%b", in, out, valid);

// Test case 3: Middle-priority input active

in = 4'b0010;
#10;
$display("Test 3: in=%b, out=%b, valid=%b", in, out, valid);
 Behavioral Modeling Example7: 4-to-2 Priority Encoder
// Test case 4: Highest-priority input active
in = 4'b1000;
#10;
$display("Test 4: in=%b, out=%b, valid=%b", in, out, valid);

// Test case 5: Multiple inputs active

in = 4'b1010; // Inputs 3 and 1 active, priority 3 should dominate
#10;
$display("Test 5: in=%b, out=%b, valid=%b", in, out, valid);

// Test case 6: Multiple inputs active, different priorities

in = 4'b0110; // Inputs 2 and 1 active, priority 2 should dominate
#10;
$display("Test 6: in=%b, out=%b, valid=%b", in, out, valid);
// End simulation
$stop; end
endmodule
60
 Procedural Assignments
• Procedural assignments update values of reg, integer, real, or time variables.
• The value placed on a variable will remain unchanged until another procedural
assignment updates the variable with a different value.
• The left-hand side of a procedural assignment can be one of the following:
• A reg, integer, real, or time register variable or a memory element
• A bit select of these variables (e.g., addr[0])
• A part select of these variables (e.g., addr[31:16])
• A concatenation of any of the above.
• There are two types of procedural assignment statements: blocking and
nonblocking.
Blocking Assignments
• Blocking assignment statements are executed in the order they are specified in a
sequential block.
• A blocking assignment will not block execution of statements that follow in a
parallel block.
In Example 7-6, the statement y = 1 is executed only after x = 0 is executed. The behavior in a
particular block is sequential in a begin-end block if blocking statements are used, because the
statements can execute only in sequence. The statement count = count + 1 is executed last. The
simulation times at which the statements are executed are as follows:
 Nonblocking Assignments
• Nonblocking assignments allow scheduling of assignments without blocking
execution of the statements that follow in a sequential block.
• A <= operator is used to specify nonblocking assignments.
• Note that this operator has the same symbol as a relational operator,
less_than_equal_to.
• The operator <= is interpreted as a relational operator in an expression and as an
assignment operator in the context of a nonblocking assignment.
 Switch-Level Modeling in Verilog
• Switch-level modeling is a type of modeling used to describe the behavior of digital
circuits at the transistor level, focusing on the operation of MOSFETs (Metal-Oxide-
Semiconductor Field-Effect Transistors).
• In switch-level modeling, the focus is on the transistors themselves and their
switching behavior, such as whether they are conducting or not.
• This type of modeling is more detailed and closely resembles the actual physical
behavior of a circuit at the transistor level.
Characteristics of Switch-Level Modeling
• Transistor Level Representation: Switch-level modeling uses transistors (MOSFETs) as
the basic building blocks of the circuit. The behavior of these transistors is modeled
using switches that can either be open or closed, representing the ON or OFF state of
the transistors.
• Switching Behavior: The core idea is to model the circuit using ideal switches
(transistors) that turn ON and OFF depending on the input conditions.
• Detailed Circuit Behavior: Switch-level modeling simulates the behavior of the
transistors and their interactions with other components like wires, gates, and other
transistors.
 Switch-Level Modeling in Verilog

Components in Switch-Level Modeling

• nMOS and pMOS Transistors: The basic building blocks are nMOS (negative-channel MOS)
and pMOS (positive-channel MOS) transistors. These transistors can be modeled as switches.
• nMOS: Conducts when the gate voltage is high relative to the source.
• pMOS: Conducts when the gate voltage is low relative to the source.
• Resistors and Capacitors: These may be included in the modeling of real-world behavior of
circuits.
• Wire Resistance and Capacitance: In more complex models, wire resistance and capacitance
are also taken into account, affecting the delay and signal propagation.
 Tasks and functions
• A designer is frequently required to implement the same functionality at many
places in a behavioral design.
• This means that the commonly used parts should be abstracted into routines and
the routines must be invoked instead of repeating the code.
• Most programming languages provide procedures or subroutines to accomplish
this.
• Verilog provides tasks and functions to break up large behavioral designs into
smaller pieces.
• Tasks and functions allow the designer to abstract Verilog code that is used at
many places in the design.
 Tasks and functions
• Both tasks and functions must be defined in a module and are local to the
module.
• A function is used to perform a specific operation or computation and return a
value. It is generally used for small, non-blocking operations.
• Functions are used when common Verilog code is purely combinational, executes
in zero simulation time, and provides exactly one output.
• Functions are typically used for conversions and commonly used calculations.
• Tasks can have input, output, and inout arguments; functions can have input
arguments. In addition, they can have local variables, registers, time variables,
integers, real, or events.
• Tasks or functions cannot have wires. Tasks and functions contain behavioral
statements only.
• Tasks and functions do not contain always or initial statements but are called from
always blocks, initial blocks, or other tasks and functions.
 Tasks
• Tasks are declared with the keywords task and endtask.
• Tasks must be used if any one of the following conditions is true for the
procedure:
• There are delay, timing, or event control constructs in the procedure.
• The procedure has zero or more than one output arguments.
• The procedure has no input arguments.
 Functions
• Functions are declared with the keywords function and endfunction.
• Functions are used if all of the following conditions are true for the procedure:
• There are no delay, timing, or event control constructs in the procedure.
• The procedure returns a single value.
• There is at least one input argument.
• There are no output or inout arguments.
• There are no nonblocking assignments.
Function Example
module adder_with_function(a,b,sum);
input [7:0] a, b;
output reg [7:0] sum;

// Function definition
function [7:0] add_two_numbers;
input [7:0] a, b;
begin
add_two_numbers = a + b; // Return the sum
end
endfunction

// Continuous assignment using the function

assign sum = add_two_numbers(a, b);

initial begin
a = 8'h15; // Example values
b = 8'h20;
#1; // Wait for combinational logic
$display("Function: Sum of %h and %h is %h", a, b, sum);
end
endmodule
task Example
module adder_with_task(a,b,sum);
input [7:0] a, b;
output reg [7:0] sum;
// Task definition
task add_two_numbers;
input [7:0] a, b;
output [7:0] result;
begin
result = a + b; // Perform addition
end
endtask

initial begin
a = 8'h15; // Example values
b = 8'h20;
add_two_numbers(a, b, sum); // Call the task
$display("Task: Sum of %h and %h is %h", a, b, sum);
end
endmodule
 PARITY GENERATION USING FUNCTIONS
module parity(addr,parity);
input [3:0] addr;
output reg parity;

// Compute new parity whenever the address value changes

always @(addr) begin
parity = calc_parity(addr); // First invocation of calc_parity
end

// Define the parity calculation function

function calc_parity;
input [3:0] address;
begin
calc_parity = ^address; // Return the XOR of all address bits
end
endfunction

endmodule
 Function Example
(Testbench)
module parity_tb;
reg [3:0] addr;
wire parity;
parity uut ( . addr(addr), .parity(parity) );
initial begin
$monitor($time," Input: addr =%4b output: Parity=%b," addr,parity);
// Initialize Inputs
addr = 0;
#10 addr =4'b 1111 ;
#10 addr =4'b 1000;
#10 addr =4'b 1110 ;
#10 addr =4'b 1010 ;
#10 addr =4'b 1011 ;
#10 addr=4'b 1010;
#20 $stop
end
endmodule
 Simulation Output

0 Input: addr = 0000 output: Parity=0

10 Input: addr = 1111 output: Parity=0
20 Input: addr = 1000 output: Parity=1
30 Input: addr = 1110 output: Parity=1
40 Input: addr = 1010 output: Parity=0
50 Input: addr = 1011 output: Parity=1
60 Input: addr = 1010 output: Parity=0
 BITWISE OPERATORS USING TASK
Define a module called operation that contains the task bitwise-operation
module operation(A, B, AB_AND, AB_OR, AB_XOR);
parameter delay = 10;
input [15:0] A, B;
ouput reg [15:0] AB_AND, AB_OR, AB_XOR;
always @(A or B) begin // Always block to invoke the task whenever A or B changes
bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); // Call the task
end
// Define the task bitwise-oper
task bitwise_oper;
output [15:0] ab_and, ab_or, ab_xor; // Outputs from the task
input [15:0] a, b; // Inputs to the task
begin
#delay ab_and = a & b; // Perform AND operation with delay
ab_or = a | b; // Perform OR operation
ab_xor = a ^ b; // Perform XOR operation
end
endtask

endmodule
 // Testbench for the operation module
module tb_operation;
reg [15:0] A, B; wire [15:0] AB_AND, AB_OR, AB_XOR;
// Instantiate the operation module
operation uut ( .A(A),.B(B),.AB_AND(AB_AND),.AB_OR(AB_OR),
.AB_XOR(AB_XOR) );

initial begin
// Initialize inputs
A = 16'h0000; B = 16'h0000;
#10;
// Apply first set of inputs
A = 16'hF0F0; B = 16'h0F0F;
#10;
// Apply second set of inputs
A = 16'hAAAA; B = 16'h5555;
#10;
// Apply third set of inputs
A = 16'hFFFF; B = 16'h0000;
#10;
// Apply fourth set of inputs
A = 16'h1234; B = 16'h5678;
#10;
// Apply fifth set of inputs
A = 16'hFFFF; B = 16'hFFFF;
#10;
initial begin
$monitor("Time = %0t | A = %h, B = %h | AB_AND = %h, AB_OR = %h, AB_XOR =
%h", $time, A, B, AB_AND, AB_OR, AB_XOR);
end

endmodule
 Simulation Output

Time = 0 | A = 0000, B = 0000 | AB_AND = 0000, AB_OR = 0000, AB_XOR = 0000

Time = 10 | A = F0F0, B = 0F0F | AB_AND = 0000, AB_OR = FFFF, AB_XOR = FFFF

Time = 20 | A = AAAA, B = 5555 | AB_AND = 0000, AB_OR = FFFF, AB_XOR = FFFF

Time = 30 | A = FFFF, B = 0000 | AB_AND = 0000, AB_OR = FFFF, AB_XOR = FFFF

Time = 40 | A = 1234, B = 5678 | AB_AND = 1230, AB_OR = 567C, AB_XOR = 444C

Time = 50 | A = FFFF, B = FFFF | AB_AND = FFFF, AB_OR = FFFF, AB_XOR = 0000

 Example2: Generate Asymmetric Clock Sequence Using Tasks
module sequence;

reg clock;

initial
init_sequence(); // Invoke the task init_sequence

always begin
asymmetric_sequence(); // Invoke the task asymmetric_sequence
end
 Example2: Generate Asymmetric Clock Sequence Using Tasks

// Task to initialize the clock

task init_sequence;
begin
clock = 1'b0; // Initialize clock to 0
end
endtask

// Task to generate asymmetric clock sequence

// Operate directly on the clock defined in the module
task asymmetric_sequence;
begin
#12 clock = 1'b0; // Delay of 12 time units, set clock to 0
#5 clock = 1'b1; // Delay of 5 time units, set clock to 1
#3 clock = 1'b0; // Delay of 3 time units, set clock to 0
#10 clock = 1'b1; // Delay of 10 time units, set clock to 1
end
endtask

endmodule
Example2: Generate Asymmetric Clock Sequence Using Tasks (Test bench program)

module sequence_tb;
wire clock;
sequence uut ( .clock(clock));
initial begin
$monitor("Time = %0t, Clock = %b", $time, clock);
end
initial begin
#100 $finish;
end
endmodule
 Example2: Generate Asymmetric Clock Sequence Using Tasks (Result)

Time = 0, Clock = 0
Time = 12, Clock = 0
Time = 17, Clock = 1
Time = 20, Clock = 0
Time = 30, Clock = 1
98
 User Define Primitives (UDP)
• Verilog provides a standard set of primitives, such as and, nand, or, nor, and not, as a part of
the language.
• These are also commonly known as built-in primitives. However, designers occasionally like to
use their own custom-built primitives when developing a design.
• Verilog provides the ability to define User-Defined Primitives (UDP).
• These primitives are self-contained and do not instantiate other modules or primitives.
• UDPs are instantiated exactly like gate-level primitives.

There are two types of UDPs: combinational and sequential.

• Combinational UDPs are defined where the output is solely determined by a logical
combination of the inputs. A good example is a 4-to-1 multiplexer.
• Sequential UDPs take the value of the current inputs and the current output to determine the
value of the next output. The value of the output is also the internal state of the UDP. Good
examples of sequential UDPs are latches and flipflops.
• A UDP definition starts with the keyword primitive. The primitive name, output terminal, and
input terminals are specified.
• Terminals are declared as output or input in the terminal declarations section. For a sequential
UDP, the output terminal is declared as a reg.
• For sequential UDPs, there is an optional initial statement that initializes the output terminal
of the UDP. The UDP state table is most important part of the UDP.
• It begins with the keyword table and ends with the keyword endtable.
• The table defines how the output will be computed from the inputs and current state.
• The table is modeled as a lookup table and the table entries resemble entries in a logic truth
table.
• Primitive definition is completed with the keyword endprimitive.
UDP Rules: UDP definitions follow certain rules:
1. UDPs can take only scalar input terminals (1 bit). Multiple input terminals are permitted.
2. UDPs can have only one scalar output terminal (1 bit). The output terminal must always
appear first in the terminal list. Multiple output terminals are not allowed.
3. In the declarations section, the output terminal is declared with the keyword output. Since
sequential UDPs store state, the output terminal must also be declared as a reg.
4. The inputs are declared with the keyword input.
5. The state in a sequential UDP can be initialized with an initial statement. This statement is
optional. A 1-bit value is assigned to the output, which is declared as reg.
6. The state table entries can contain values 0, 1, or x. UDPs do not handle z values.
z values passed to a UDP are treated as x values.
7. UDPs are defined at the same level as modules. UDPs cannot be defined inside modules. They
can be instantiated only inside modules. UDPs are instantiated exactly like gate primitives.
8. UDPs do not support inout ports.
Combinational UDPs
Combinational UDPs
Combinational UDPs using Don't Cares
Instantiating UDP Primitives
4-to-1 Multiplexer with UDP

107
 4-to-1 Multiplexer with UDP
primitive mux4_to_1 ( output out, input i0, i1, i2, i3, s1, s0);
table
// i0 i1 i2 i3, s1 s0 : out
1???00:1;
0???00:0;
?1??01:1;
?0??01:0;
??1?10:1;
??0?10:0;
???111:1;
???011:0;
????x?:x;
?????x:x;
endtable
108
endprimitive
 4-to-1 Multiplexer
// Stimulate the inputs
with UDP:// Stimulate the inputs
initial
begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);
// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end
endmodule
109
The output of the simulation is shown below.

IN0= 1, IN1= 0, IN2= 1, IN3= 0

S1 = 0, S0 = 0, OUTPUT = 1
S1 = 0, S0 = 1, OUTPUT = 0
S1 = 1, S0 = 0, OUTPUT = 1
S1 = 1, S0 = 1, OUTPUT = 0

110
 Sequential UDPs
Sequential UDPs differ from combinational UDPs in their definition and behavior.
Sequential UDPs have the following differences:
• The output of a sequential UDP is always declared as a reg.
• An initial statement can be used to initialize output of sequential UDPs.
• The format of a state table entry is slightly different.
• <input1> <input2> ..... <inputN> : <current_state> :<next_state>;
• There are three sections in a state table entry: inputs, current state, and next state.
The three sections are separated by a colon (:) symbol.
• The input specification of state table entries can be in terms of input levels or edge transitions.
• The current state is the current value of the output register.
• The next state is computed based on inputs and the current state. The next state becomes the
new value of the output register.
• All possible combinations of inputs must be specified to avoid unknown output values.
 Level-Sensitive Sequential UDPs
Level-sensitive UDPs change state based on input levels. Latches are the most common example of level-sensitive UDPs.
113
Edge-Sensitive Sequential UDPs
 Finite-State machine
A Finite-State Machine (FSM) is abstract model of describing sequential logic circuits and
software systems.
Each FSM has a set of inputs and outputs and a finite set of internal states.
It represents a system that can be in one of a finite number of states at any given time and
transitions between states based on inputs and logic.
We have 2 FSM models depending on how output is generated .
Melay machine and Moore Machine.
 Finite-State machine
Types of FSM
1. Moore Machine:
The output depends only on the current state.
Outputs are updated at state transitions.
Output Function: Output=f(State)
State Diagram: Each state has associated outputs.

2. Mealy Machine:
The output depends on both the current state and the inputs.
Outputs can change without a state transition.
Output Function: Output=f(State, Input)
State Diagram: Transitions between states include outputs.
Mealy State Machine
• A Finite State Machine is said to be Mealy state machine, if outputs
depend on both present inputs & present states.
• The block diagram of Mealy circuit model is shown in the following
figure.
Moore State Machine
• A Finite State Machine is said to be Moore state machine, if outputs depend
only on present states. The block diagram of Moore state machine is shown in
the following figure.
 Finite-State machine
The behavior of the machine can be represented in 3 different ways.
1. State transition diagram: Pictorial way of representing the behavior of the FSM.
2. State table : represents same information in tabular form.
3. State equation: the algebraic way of representing same information.
 Sequence Detector
• It is a sequential machine which produces an o/p 1 every time the desired
sequence is detected and an o/p 0 at all other times.
• Sequence detector is a good example to describe FSMs. It produces a pulse
output whenever it detects a predefined sequence.
• The sequence detectors can be of two types: with overlapping and without
overlapping.
• We have considered a 4-bit sequence “1010”.
• For example, consider the input sequence as “11010101011”.
• Then in ‘without overlapping’ style, the output y will be “00001000100” and the
output y in ‘with overlapping’ style will be “00001010100”. The ‘with
overlapping’ style also considers the overlapping sequences.
 Design a sequence detector to detect a sequence
“1010” for an overlapping case using Mealy machine
• The first step of an FSM design is to draw the state diagram.
• State table
• Transition and output table
• Excitation table
• Logic diagram after simplification with K map
To detect the sequence 1010: overlapping is permitted if the input sequence is 01101010 and the output
sequence is 00000101.
State table Transition Table
Excitation Table
Logic Diagram
Verilog code of sequence detector to detect a sequence
“1010” for an overlapping case using Mealy machine
module sequence_detector_mealy( input clk, input reset, input in_bit,
output reg detected );
// State encoding
parameter S0 = 2'b00, // Initial state
S1 = 2'b01, // "1" detected
S2 = 2'b10, // "10" detected
S3 = 2'b11; // "101" detected

reg [1:0] current_state, next_state; // State registers

135
// State transition logic (sequential)
always @(posedge clk or posedge reset) begin
if (reset)
current_state <= S0; // Reset to initial state
else
current_state <= next_state; // Update to next state
end
// Next state and output logic (combinational)
always @(*) begin
// Default values
next_state = S0;
detected = 0;
136
case (current_state)
S0: begin
if (in_bit)
next_state = S1; // Move to S1 on input 1
else
next_state = S0; // Stay in S0 on input 0
end
S1: begin
if (in_bit)
next_state = S1; // Stay in S1 on input 1
else
next_state = S2; // Move to S2 on input 0
end 137
S2: begin
if (in_bit)
next_state = S3; // Move to S3 on input 1
else
next_state = S0; // Go back to S0 on input 0
end
S3: begin
if (in_bit)
next_state = S1; // Restart to S1 on input 1
else begin
next_state = S2; // Move to S2 on input 0
detected = 1; // Sequence "1010" detected
end end 138
 default: next_state = S0; // Default case
endcase
end

endmodule

139
TestBench Program
module tb_sequence_detector_mealy;

// Testbench signals
reg clk;
reg reset;
reg in_bit;
wire detected;

// Instantiate the sequence detector

sequence_detector_mealy uut ( .clk(clk), .reset(reset),
.in_bit(in_bit), .detected(detected) );
140
TestBench Program
// Clock generation
always #5 clk = ~clk; // 10ns clock period

// Test sequence
initial begin
// Initialize inputs
clk = 0;
reset = 1;
in_bit = 0;

// Reset the system

#10 reset = 0; 141
TestBench Program

// Apply test sequence: "101010"

#10 in_bit = 1; // Input "1"
#10 in_bit = 0; // Input "0"
#10 in_bit = 1; // Input "1"
#10 in_bit = 0; // Input "0" (detected = 1)
#10 in_bit = 1; // Input "1" (overlapping sequence)
#10 in_bit = 0; // Input "0" (detected = 1 again)
#10 in_bit = 1; // Input "1" (start of new sequence)
#10 in_bit = 1; // Input "1" (wrong sequence)
#10 in_bit = 0; // Input "0"
142
TestBench Program
// Hold the simulation for observation
#20 $stop;
end

// Monitor outputs
initial begin
$monitor("Time = %0d | Reset = %b | Input = %b | Detected = %b",
$time, reset, in_bit, detected);
end

endmodule
143
144
145
 1010 Overlapping Moore Sequence Detector (Verilog Code)

module sequence_detector_1010_moore ( input clk, input rst, input din, output reg dout );
// State encoding using parameters
parameter A = 3'b000, // Initial state
B = 3'b001, // Detected '1'
C = 3'b010, // Detected '10'
D = 3'b011, // Detected '101'
E = 3'b100; // Detected '1010'

reg [2:0] state, next_state;

// State transition logic

always @(posedge clk or posedge rst) begin
if (rst) state <= A; // Reset to initial state
else state <= next_state; // Transition to the next state end
// Next state logic
always @(*) begin
case (state)
A: next_state = (din == 1) ? B : A; // Starting with '1'
B: next_state = (din == 0) ? C : B; // After '1', detect '10'
C: next_state = (din == 1) ? D : A; // After '10', detect '101'
D: next_state = (din == 0) ? E : B; // After '101', detect '1010'
E: next_state = (din == 1) ? D : A;
default: next_state = A; // Default state
endcase
end
// Output logic (Moore machine output depends only on state)
always @(state) begin
dout = (state == E); // Output '1' when '1010' is detected
end
endmodule
 Testbench program
module tb_sequence_detector_1010_moore;
reg clk; reg rst; reg din; wire dout;
uut ( .clk(clk), .rst(rst), .din(din), .dout(dout) );
// Clock generation
always begin #5 clk = ~clk; // Toggle clock every 5 time units
end
// Test sequence
initial begin
clk = 0; rst = 0;
din = 0;
rst = 1; #10;
rst = 0;
 Testbench program
// Apply input sequence: 1, 0, 1, 0, 1, 0, 1, 0 (overlapping 1010)
din = 1; #10;
din = 0; #10;
din = 1; #10;
din = 0; #10;
din = 1; #10;
din = 0; #10;
din = 1; #10;
din = 0; #10;
// Check final state (output should be '1' when '1010' detected)
$stop;
end
Testbench program
// Monitor the signals
initial begin
$monitor("Time = %0t, din = %b, dout = %b", $time, din, dout); end
endmodule
 1010 Overlapping Mealy Sequence Detector (Verilog Code)
module sequence_detector ( input logic clk, reset, din, output logic detected);

// State encoding using parameters

parameter A = 3'b00, // Initial state
B = 3'b01, // Detected '1'
C = 3'b10, // Detected '10'
D = 3'b11, // Detected '101'

reg [2:0] state, next_state;

// State Transition Logic
always_ff @(posedge clk or posedge reset) begin
if (reset)
state <= A;
else
state <= next_state;
end
always @(*) begin
next_state = state; // Default to remain in the same state
detected = 0; // Default output
case (state)
A: next_state = (din == 1) ? B : A; // Starting with '1'

B: next_state = (din == 0) ? C : B; // '10' sequence

C: next_state = (din == 1) ? D : A; // '101' sequence

D: begin
detected = (din == 0) ? 1 : 0; // '1010' detected
next_state = (din == 0) ? B : C; // Overlapping sequence handling
end
default: next_state = A;
endcase
end
endmodule
 Integrated Circuit (IC)
• Monolithic chips containing several components.
• Monolithic silicon chip: It means that the silicon chip or substrate, consisting of
only single crystal of silicon.
• And over that single crystal of silicon we are integrating multiple components
like transistors, diodes, resisters and so on. It is not that we are putting together
different components them combining or adding them together.
• On the silicon substrate using some technology we are growing transistors or
making transistors, diodes, resisters and so on. And as a result the complete
system is one piece of monolithic silicon chip. And that is what is known as IC.
 VLSI Design Flow
• The VLSI (Very Large Scale Integration) Design Flow is a systematic process for designing and developing
integrated circuits (ICs) or microchips. This methodology employs a divide-and-conquer approach, breaks the
entire chip designing task and manufacturing into multiple sequential steps. Throughout this flow, a design
undergoes numerous transformations, evolving from an initial idea/concept to a finalized chip.
• Initially, the design is represented at the Register Transfer Level (RTL), typically written in hardware description
languages such as VHDL or Verilog. This RTL description serves as the foundation for the design process, which
ultimately culminates in a layout formatted as a Graphical Database System (GDS) file. Thus, two essential
milestones in the journey from concept to chip are identified: RTL and GDS.
• Based on these milestones, the entire design process can be divided into three distinct phases:
• Idea/Concept to RTL: This phase involves translating a high-level idea or product concept into an RTL
representation, effectively capturing the hardware portion of the idea . This stage is often referred to as system-
level design or the “idea/concept to RTL" flow.
• RTL to GDS Flow: In this phase, the RTL description undergoes various stages of logical and physical design,
resulting in a layout represented in GDS format. This comprehensive process includes logic synthesis,
verification, physical design, and testing.
• GDS to Chip: Once the layout is finalized, it is sent to a foundry for fabrication. The foundry utilizes the GDS file
to prepare masks, fabricate the IC, conduct testing, package the chips, and ultimately release the product to the
market.
• Each of these phases is critical in ensuring the successful development and deployment of an integrated circuit,
adhering to the specified design requirements and performance criteria.
 RTL to GDS Flow
• The RTL (Register Transfer Level) to GDS Flow is a
comprehensive process in IC (Integrated Circuit) design that
transforms RTL which is a high-level hardware description into
a manufacturable layout.
• This flow encompasses both front-end and back-end design
stages, ensuring the final product meets all functional,
performance, and physical requirements.
RTL to GDS Flow
• RTL : Develop the design using Hardware Description Languages
(HDLs) like Verilog or VHDL, capturing the desired behavior at the
register-transfer level.
• Logic Synthesis: Convert the verified RTL code into a gate-level netlist
using a standard cell library, optimizing for area, speed, and power.
• Physical Design: Process by which a design in the form of a netlist is
converted to an equivalent design in the form of layout or GDS
(geometrical patterns of masks).
 Logic Synthesis
• Logic Synthesis: process by which RTL is converted to an equivalent
circuit as interconnection of logic gates, which are picked from
technology libraries.
Synthesis Design Flow
•RTL Description:
•The design is written at a high level using RTL constructs in Verilog or VHDL.
•The RTL design consists of registers, combinational logic, and sequential elements.
•Translation:
•The synthesis tool describes the HDL code and converts it into an intermediate representation (IR), which is an
internal format understood by the tool.
•Unoptimized Intermediate Representation:
•This is an internal representation of the design in terms of basic gates and operations, but it is not yet
optimized.
•The synthesis tool represents the design using data structures like Abstract Syntax Trees (ASTs) or Directed
Acyclic Graphs (DAGs).
•Logic Optimization:
•The synthesis tool applies Boolean algebra transformations, redundancy elimination, and logic restructuring to
optimize the design. The goal is to reduce area, power consumption, and timing delay.
•Technology Mapping and Optimization:
•The optimized logic is mapped to the available ASIC standard cells or FPGA lookup tables (LUTs).
•Further optimizations, such as gate resizing, buffer insertion, and multi-VT optimization, may be performed.
 Physical Design
Process by which a design in the form of a netlist is converted to an equivalent design in the form
of layout or GDS (geometrical patterns of masks)

In physical design, all components like macros, cells, gates, transistors, etc with fixed sizes and shapes are placed at the
location in the fabrication layer to perform appropriate routing. Physical design is performed according to DRC (Design Rule
Check) which depends on the capabilities of fabrication technology. For example, wires must be kept at a proper distance
between them. Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield.
VLSI Design Flow
 VLSI Design Flow

1. Specifications
•Define the functionality, performance, area, and power requirements.
•Specify input/output interfaces, technology node, and system constraints.
2. Architectural Design
•Decide the high-level design, including major blocks like processors, memory, and interconnects.
•Perform trade-off analysis for performance, power, and area.
3. Functional Design and Logic Design
•Once the architecture is defined the connectivity and functionality can be defined in this step. That is each module
has an input-output and timing behavior.
•Logic design converts the architectural description into a register-transfer level (RTL) design using hardware
description languages (HDLs) like Verilog or VHDL. Focus on modules, control units, and data path design.
•There are logic synthesis tools that automate the process of converting HDL into low-level circuit elements. That is
by using Verilog or VHDL description and the technology library a logic synthesis tool can map all the functionalities
to the list of signal nets, and specific circuit elements like transistors.
 VLSI Design Flow

4. Circuit Design:
After the automatic conversion of standard cells or higher, there are several critical and low-level elements that must be
designed at the transistor level this is called circuit design.

The circuit design phase is where the RTL description is translated into a circuit-level implementation. This involves the
creation of a gate-level netlist, which is a low-level description of the circuit in terms of logic gates.

The gate-level netlist is then optimized to improve performance, power consumption, and area utilization. This optimization is
done using computer-aided design (CAD) tools, which are software programs that automate the design process.

The gate-level netlist is also verified through simulation to ensure that it functions correctly. This involves the creation of test
benches, which are software programs that generate inputs to the circuit and verify that the outputs are correct.
For example, elements like RAM blocks, I/O, analog circuits, Multipliers, and ESD protection circuits are designed in circuit-
level design. The verification of circuit design is done by the simulation tools like SPICE.
 VLSI Design Flow

5. Physical Design:
In physical design, all components like macros, cells, gates, transistors, etc with fixed sizes and shapes are placed at the
location in the fabrication layer to perform appropriate routing. Physical design is performed according to DRC (Design Rule
Check) which depends on the capabilities of fabrication technology. For example, wires must be kept at a proper distance
between them. Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield.
Due to the high complexity of physical design, it split into several steps as follows-

1) Partitioning
2) Floorplanning
3) Power and Ground Routing
4) Placement
5) Clock Network Synthesis
6) Global Routing
7)Detailed Routing
8) Timing Closure

The physical design phase is a critical step in the VLSI design flow because the physical layout can have a significant impact on
the performance, power consumption, and area utilization of the chip. Therefore, the physical design is optimized using CAD
tools to improve these metrics.
 VLSI Design Flow

6. Physical Verification:
After the physical design, the designed layout must be verified to ensure correct functionality. In this step after verification,
some problems found can be neglected if they cause a nominal impact on performance but if causing a major impact then the
layout needs to be changed. This is done by experienced design engineers. Some types of verifications are performed in this
step as follows-

1) Design Rule Check (DRC)

2) Layout vs Schmatic(LVS)
3) Parasitic Extraction
4) Antenna Rule Checking
5) Electrical Rule Checking (ERC)

7. Fabrication:
The final Layout represented in the GDSII stream format is sent for manufacturing at a dedicated silicon foundry(Fab). The
handoff of the design to the manufacturing process is called tape out. The generation of data for manufacturing is sometimes
referred to as streaming out. At fab, the design pattern is printed on different layers using photolithography. ICs are
manufactured on round silicon wafers of diameter from 200mm to 300mm. The IC must be tested after fabrication and cut
into smaller pieces to get the end chip.

The fabrication process is a complex and expensive process that requires specialized equipment and facilities. Therefore, it is
typically outsourced to semiconductor foundries that specialize in chip manufacturing.
 VLSI Design Flow

8. Packaging and Testing:

After dicing chips are packaged according to the design process. Chip package types like dual in-line packages (DIPs), pin
grid arrays (PGAs), and ball grid arrays (BGA). After the chip is placed in the die cavity the pins are connected to the pins of
the package and then it is sealed.

The testing phase is a critical step in the VLSI design flow because it ensures that the final product meets the design
specifications and is free from defects. Therefore, the testing process is performed rigorously to ensure the quality of the
final product.