Module-4

High Density Interconnection

Through-Silicon Vias Modelling and Testing,

Electrical Modelling,
Thermal Modelling,
Mechanical Modelling
 Outline
❑ The Basics
❑ Signal Integrity
▪ Capacitive Delay
▪ Package Electrical Structures
▪ Transmission Lines
▪ Eye Diagram
▪ Cross Talk
❑ Power Delivery Engineering
▪ What is it?
▪ Core & IO Circuits
▪ Resistance & Inductance
▪ Jitter & Power Supply Noise
▪ Capacitors
❑ Radiation

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 2
 Electrical Aspects of Packaging

❑ Consider a Single Chip Package

❑ Signals from the bare chip needs to be routed on to the Printed Wiring Board (PWB) to be able to connect to other
chips.
❑ Each wire used in the package (and PWB) introduces parasitics.
❑ These parasitics slow the speed of signal propagation.
❑ Electrical package design- functionalities: signal and power distribution with integrity
@ chip – package- board
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 3
 Challenges in High Speed Electrical Signaling
❑ What happens when chips communicate with each other ?

EMI
THERMAL NOISE
SUSCEPTIBILITY RADIATION

ATTENUATION

INTERCONNECT DELAY
Power Supply Noise CROSSTALK
❑ Signals suffer from reflection, crosstalk, delay, attenuation and radiation
❑ Chips suffer from power supply noise which affects performance
Ref: R. Achar, EDAPS Tutorial, Dec 2005
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 4
 Electrical Design Flow of a Package

Power Integrity (PI)

Signal Integrity (SI) - Providing pure DC voltage
- Timing & quality of signal to ICs for high speed data
transmission
Signaling Power Delivery

Signaling + Power Delivery

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 5
 Signaling for Synchronous Digital Systems
Flip-Flop A Flip-Flop B

Combinational
D Q D Q
Logic Delay

Clock

Clock Distribution
Network

• Consists of two very important signals:

– Data (communication between Transistors or ICs)
– Clock (Reference signal for Transistors and ICs)
Courtesy: M. St. Laurent, Intel
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 6
 Clock and Data Signals

Non-Periodic
Signal
Periodic
Signal
T

❑ Latching occurs during rising and falling edge of the clock

Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 7
 Transistors
❑ Devices on the chip are made of transistors
❑ Transistors can be viewed as switches – simplest way to understand their behavior
❑Example: CMOS chips consist of NMOS and PMOS transistors that can be represented as 3 terminal
switches as shown below:
S S

Gate G 3 terminal G 3 terminal

Transistor Transistor
Source
D D
S S Normally
Normally
open closed switch
I
switch Binary 1 at
G Binary 1 at G gate causes
gate switch to
Drain I causes open
D switch to D
close PMOS
NMOS
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 8
 Transistors & Circuits
❑ Two or more transistors are connected together to form a circuit
❑ Consider the most basic circuit – the CMOS inverter
Vdd Vdd
Vdd
I

IN OUT 1 0 0 1

I
Gnd
Gnd Gnd
Inverter IN=1, OUT=0 IN=0, OUT=1
❑ PMOS + NMOS transistor forms an inverter circuit
❑ Logic 1 at input is converted to Logic 0 at output (NMOS turns ON and PMOS is OFF)
❑ Logic 0 at input is converted to Logic 1 at output (PMOS turns ON and NMOS is OFF)
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 9
Transistors & Circuits

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 10
Transistors & Circuits

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 11
 IC to IC Communication
IC 1 Vdd IC 2
Driver Receiver
❑Chip or Package Interconnection
Rec. input provides the communication path for
signals to propagate
IN OUT ❑In this example the charge across the
Package Signal Wire capacitor at the receiver is discharged
through the interconnection causing a
Logic 0 at
the receiver input
Vdd Gnd
Ron

On resistance Wire
of device 1
Cg Input of receiver behaves as a
I capacitor
Current discharges the capacitor
Ron Rec. input = 0
Gnd Gnd
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 12
 Capacitive Delay
❑ Let’s assume that the package wire can be represented as a capacitor.
❑ The receiver capacitance (Cg) is being charged (Logic 1).
❑ The PMOS transistor switch is turned ON at time t=0.
Vdd

Ron Wire Capacitance

I

Wire Ron
0
+ t=0 +

Vdd C Cg Vload
Ron - -

Gnd Gnd
Rec. capacitance

❑ Does the receiver input change to ‘zero’ instantaneously ?

❑ Can the signal truly be treated as 1s and 0s ?
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 13
 Capacitive Delay (cont.)
Vload
Wire Capacitance

Ron Vdd

t=0 +

Vdd C Cg Vload
0.5Vdd VREF

time
Rec. capacitance Delay

❑ Vload rises to Vdd as time progresses.

❑ Depends on the time constant of the circuit.
❑ Circuits have a threshold level (VREF) for switching.
❑ There is a delay to reach the threshold level (0.5Vdd).
❑This is due to the capacitance of the interconnection and load & its interaction with
the on resistance of the transistor.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 14
 Capacitive Delay (cont.)
Wire Capacitance

Ron

t=0 +

Vdd C Cg Vload

Rec. capacitance

Boundary Conditions

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 15
 Capacitive Delay (cont.)
❑ Voltage and time relationship can be derived as

❑ 50% Capacitive delay

T50% = 0.69Ron (C + C g )
Example

Vdd=5V ; Ron=50 Ohms ; C+Cg = 10pF

Ideal Receiver Input
Vdd
Actual Driver Input
t = 0.5ns

Vload requires 0.35ns to reach 2.5V

Delay
Delay = 0.35ns
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 16
 Package Electrical Structures for Signaling
Physical origin of CAPACITANCE

❑ Interconnects carry electrical signals between ICs

❑ Their structure determines their capacitance
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 17
 Microstrip Line & Stripline

Microstrip Signal
E +
V
C
Ground -
Total Capacitance=C

Stripline

Ground
E C
Signal
C
Ground
Total Capacitance=2C
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 18
Time Domain Signal & Frequency

V0 tr
Tw

t
0 T

tr = 0.35/B.W

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 19
Introducing Wavelength & Length Relationship

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 20
Example: Wavelength & Length Relationship

IC1 IC2

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 21
 Transmission Lines (TLines)

IC1 IC2

❑ This means that the interconnect cannot be represented by capacitance alone.

❑ The interconnect inductance also becomes important.

❑ In general, if the resistance of the interconnect is low, the inductance and capacitance
affects of the interconnect dominate the electrical response.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 22
 Capacitance Vs Transmission Lines

Input @ IC1 Output @ IC2

Input @ IC1 Output @ IC2

Additional Delay (Time of Flight)

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 23
Time of Flight Delay (Ttof)

Non-magnetic material

𝜖𝑟 : 𝑟𝑒𝑙𝑎𝑡𝑖𝑣𝑒 𝑝𝑒𝑟𝑚𝑖𝑡𝑡𝑖𝑣𝑖𝑡𝑦
𝑜𝑓 𝑑𝑖𝑒𝑙𝑒𝑐𝑡𝑟𝑖𝑐

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 24
 Time of Flight Delay (Ttof) Calculations

Lower
dielectric
constant is
better

50% more delay

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 25
 Transmission Line Fundamentals

❑ A transmission line enables the propagation of a signal between two points with minimum degradation.
❑ When electricity flows there is physical movement of charge down one conductor and back the other.
❑ Charge has momentum and continues to flow it has started (inductance).
❑ Metal is not a perfect conductor (resistance).
❑ Equal and opposite charge is stored on the conductors (capacitance).
❑ Dielectric is not a perfect conductor (conductance)
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 26
 Transmission Line Equivalent Circuit

❑ Transmission lines have uniform cross section

❑ Transmission lines are defined by per unit length (pul) RLGC parameter
❑ R(ohm/m); L (Henry/m); G(Siemen/m); C (Farad/m)

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 27
 Signal on TLine

I(0) l I(l)
Conductor 1

V(0) V(l)
Signal Dielectric
Conductor 2 z (position)

I(0) I(l)

❑ Signal incurs a delay to travel from the start to the end of the TLine

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 28
 Where does the current flow on Reference Conductor?

❑ Consider a microstrip line

❑ Current returns on the ground plane (reference)
❑ Current on the ground plane is not uniformly distributed
❑ Instead, current crowds in the vicinity of the signal conductor.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 29
 Behavior of a Lossy TLine

❑ A step pulse gets more rounded when it propagates though a lossy TLine. Main source of
losses are the conductor loss and dielectric loss.

❑ How do you account for losses?

Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 30
 Does current flow uniformly in the Conductor?

❑ Current flows uniformly in the conductor at DC.

❑ Current flows on the skin of the conductor as frequency increases.
❑ Depth to which current flows is a function of frequency.
❑ Since current is confined to the skin of the conductor, this is called skin effect.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 31
 Interconnect DC Resistance

w
t
h

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 32
 Conductor Loss (R)
❑ Conductor losses are related to the resistance of the conductor
❑ DC resistance of a conductor is given by:
w
Current
t A

:resistivity (/m)
❑ As frequency increases the current flows only through part of the conductor cross section ()
R1
 w l
Current
R2 A
A

:resistivity (-m)
=1/ (S/m)
:permeability (H/m)

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 33
 Conductor Loss (cont.)

R(f)

w=50um; t=25um; =2u-cm (Cu); =410-9 (H/cm)

❑ Resistance increases as square root of frequency.

❑ Approaches 1.8 Ohm/cm at 10GHz (increase of 1025%).
❑ Each frequency component of the signal gets attenuated differently due to the skin effect resistance.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 34
 Dielectric Loss (G)

❑ Most dielectrics are not ideal and have loss in them

❑ An important parameter that is a measure of dielectric loss is the loss tangent

c: speed of light in vacuum

r: relative permittivity of dielectric

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 35
 Behavior of a Transmission Line in PCB

Linear w/ freq.

Crossover

Sq. root w/ freq.

❑ Copper Loss caused by R (Resistance/length)

❑ Dielectric Loss caused by G (Conductance/length)
❑ Depending on frequency either conductor or dielectric loss dominates
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 36
 Data Rate: Clock Vs Data
0 1 1 0 1 1 0 1
Voltage

Voltage
T time

time
leading edge falling edge

❑ Two problems here: 1) unlike clock the data signal is not periodic, and 2) the quality of the
signal waveform is unaccounted.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 37
 Data Signal
Clock Edge

❑ Bit Period: Width of a pulse (or bit)

❑ Timing Jitter: Uncertainty in the signal
arrival time
❑ Eye Opening: Vertical Height (Volts)
❑ Eye Width: Horizontal distance (secs)

❑ We use eye-diagrams to understand the signal quality of data waveforms

❑ Generated by overlaying streams of data wrt the clock
❑ Vertical axis is Volts and Horizontal axis is Time
❑ Many bits (positive and negative transitions) are superimposed
❑ Resulting diagram is an eye diagram (resembles an eye)
❑ Can be used to determine signal quality effects
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 38
 Eye-Diagram – Simple Example

A B C D
V 0 1 1 1 0 0 0 0 1 1 1 0
Vhigh

Vlow

T (secs)
0 1 2 3 4 5 6 7 8 9 10 11

❑ Eye diagram should contain

❑ All possible bit sequences
❑ From alternating 1s and 0s
❑ To long sequences of 1s and 0s

❑ Voltage and time samples

Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 39
 Eye-Diagram – Simple Example (cont.)
V A V C
Vhigh Vhigh

Vlow Vlow

t t
0 1 2 0 1 2
V V
B D ❑ Example here
Vhigh Vhigh
▪ 011, 100, 001, 110 superimposed
Vlow Vlow here
t
0 1 2 0 1 2 t
V
A+B+C+D
Vhigh
Eye Diagram
Vlow

t
0 1 2
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 40
 Eye-Diagram – Different Scenarios

Measured eye-diagrams of digital signals transmitted through a 40-inch transmission line at data rates of (a) 200 Mbps, (b)
800 Mbps, and (c) 3200 Mbps

❑ When signals are transmitted, non-idealities occur.

❑ These non-idealities occur due to process variations, poor matching, cross talk etc.
❑ Jitter is the uncertainty in the arrival of the leading and falling edge of the signal
❑ Our objective is to obtain a clean eye
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 41
 Crosstalk

❑ Causes coupling between interconnects

❑ Causes false switching of receivers
❑ Induces jitter in the system
❑ Need to estimate cross talk
❑ Eliminate through shielding
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 43
 Interconnect Coupling in Package
Inductive coupling
is important along
w/ capacitive M
coupling.

Cm Cg
Cg

Parameters
L: Self inductance of each interconnect (H/cm)
M (Lm): Mutual inductance between interconnects (H/cm)
Cg: Capacitance to ground plane for each interconnect (F/cm)
Cm: Mutual capacitance between interconnects (F/cm)
C = Cg + Cm (F/cm)
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 43
 Crosstalk Mechanism

❑ Two Lines
❑ Assume 50W impedance
❑ Line lengths matched
❑ All four ends terminated and matched
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 44
 Power Delivery Engineering

We have Need to focus on

focused so Power Integrity (PI)
far on Signal as well
Integrity (SI) ❑ The process of
providing clean DC
voltage with required current to the
switching
transistors is called Power
Delivery or Power Integrity
Engineering

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 45
 Supplying Power to the ICs
Power
Supply

Voltage
❑ Input Regulator
❑ 100V-240V AC
❑ 1.6A 50/60Hz Laptop
Desktop
❑ Output
❑ 15V at 4A DC
❑ 5V at 1A DC

❑ Transistors work using DC voltage.

❑ Power comes from a wall outlet in the form of AC.
❑ Have you wondered how DC voltage and current (power) are supplied to the ICs?
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 46
 Power Delivery Engineering
Vdd

Supply Voltage
DC Offset Max. Voltage
AC Noise Error
Vavg

time

❑ The power supply voltage for the transistors should be at Vdd.

❑ However, when the transistor draws current
▪ the interconnects cause a DC voltage drop due to resistance causing a DC offset.
▪ the interconnects cause AC noise due to inductance causing additional voltage drop.
❑ Any reduction in power supply voltage will cause the transistors to slow down or mal-
function!
❑ Objective of power delivery engineering is to keep the power supply voltage as close to Vdd
as possible.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 47
 Power Delivery Engineering

Power Transistors
Supply

❑ The voltage and current are passed to the transistors through a complicated network
consisting of interconnects in the PCB, Socket, Package and IC before it gets to the
transistors.
❑ The goal of power delivery is to provide DC voltage to the transistors around a
tolerance level when the transistors switch (draw current).
❑ This is called Power Delivery Engineering!
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 48
 Two types of Circuits for Power Delivery
Core Circuits
(Communication within IC)
Vdd I/O Circuits
Active Device (IC) (Communication outside IC)

Signal Wires
Gnd

Current

❑ Core Circuits: Transistors contained with a single IC that communicate with each other.
❑ IO Circuits: Transistors in separate ICs that communicate with each other.
❑ IO Circuits are generally noisy and hence their power delivery has to be kept separate from the core
circuits
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 49
 IC1 to IC2 Communication
Supply Vdd

Vdd
ZV ZV
t Vdd
Charging Tline
t
Power Interconnection

Supply IC1 + IC2

Noise -
Discharging Tline
Vref Gnd
t
Gnd ZG
t
ZG

Supply Gnd
❑ Power is provided through the interconnections.
❑ These interconnections have impedances associated with them (ZV and ZG).
❑ Causes the stable voltage and gnd supply to fluctuate with time.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 50
 Parasitics in Power Distribution
Vdd

R
IVdd ZV
Vdd Vdd L
Chip_Vdd
C
Gnd Gnd Gnd Gnd Chip_Gnd
L
IGnd ZG
R

VR = IR Voltage drop across resistor Gnd

CULPRIT
dI
VL = L Voltage drop across inductor
dt
❑ Interconnects can be represented using resistance R and inductance L (parasitics)
❑ DC Offset and AC Noise are generated by the R & L parasitics of the interconnects.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 51
 1. DC Resistance
VDD
 Charging DC current reduces the
VDD node of the driver by IRVDD
RVDD I (Charging)

VDD-IRVDD  Discharging current increases the

VSS node of the driver by IRVSS
G
 This changes the DC voltage
level of the driver
VSS+IRVSS

RVSS I (Discharging)  Affects the operation of the transistors

VSS Goal is to minimize Resistance between the

Supply & Transistors
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 58
 2. Inductance

G
Power Supply

❑ When the PMOS transistor closes current is drawn from the power supply to charge the
capacitor.
❑ This causes transient current to loop around between the positive (V) and negative (G)
terminal of the power supply.
❑ The transient current flowing through the inductors causes voltage drop across them and
AC noise (noise changes with time).
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 53
 AC Noise Computation – Core Circuits

i(t) t=0 i(t)

L L +
+ vL - + vL -
Ron L
+
Vdd
 RC v(t) tr R
Vdd-vL
R
- C

-
L is the total inductance we calculated
for wirebond, flip chip, and planes

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 54
 AC Noise Computation (cont.)

Example:

❑ Let tr = 0.1ns, L = 0.1nH, R = 1, C = 1nF and Vdd = 1V.

❑ The ratio L/R = 0.1RC and therefore the condition is met.
❑ The maximum voltage drop across the inductor can be obtained as 632mV.
❑ Reduce inductance to L=0.01nH, the maximum voltage drop across the inductor is
100mV.
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 55
 AC Noise Computation Waveforms

v(t)

v = 632mV

v = 100mV

tr

❑ Note that the shape of the noise v becomes square as the inductance reduces!
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 56
Voltage waveform across inductor

v=200mV

v=20mV

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 57
Delay due to 1 Driver and 100 Drivers Switching

1 Driver

100 Drivers

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 58
 Jitter caused by Power Supply Noise

Vdd
PRBS
Varying Voltage Droop
on Power Supply due
to Switching
Output driver waveform

time
Uncertainty in Delay due to Switching causing Jitte r

❑ Random bits generate random power supply noise

❑ Leading to Random Rising/Falling Edge & Ringing
❑ Causing Data Dependent Jitter & Eye Closure
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 59
Two major types of Interconnects in Power Delivery

V G

G
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 60
Resistance Calculations

Example

l Example

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 61
 Inductance Calculations

V G V (Voltage)

V
G (Ground)

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 62
 Inductance Calculations (cont.)
Example 1: Wirebond

V G
Wirebond
Example 2: Wirebond (Importance of mutual inductance)

Key take away

Keep the wires close
to each other to
reduce inductance

Example 3: Flip Chip (Importance of reduced inductance)

Flip Chip
Key take away
Flip Chip has lower
inductance than
wirebond

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 63
 Package Types

Inductance Inductance
Reduces Reduces

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 64
 Capacitors – What is their role in Power Delivery?
High Frequency Capacitors

Mid-frequency Capacitors

Less
Latency
Incurs
Latency

I
Motherboard
t

❑ Capacitors are a Reservoir of charge VRM

❑ Provides charge to the circuits I
❑ Their proximity to the chip is important
❑ Three types: Low, Med and High Frequency t

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 65
 Example: Multilayer Ceramic Capacitor

❑ Leads add (parasitic) resistance called

Equivalent Series Resistance (ESR)
❑ Leads add (parasitic) inductance called
Equivalent Series Inductance (ESL)
❑ A capacitor can therefore be represented as
a Series RLC circuit
Courtesy: WWW
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 66
 Response of a Capacitor
❑ We are interested in the variation of the capacitor impedance with frequency

R=2m,L=1nH,C=22F

R=50m,L=10nH
C=10000F

❑ fr is the resonant frequency of the capacitor

❑ At resonance |Z|=R (ESR)
❑ What is the implication of impedance variation with frequency?
❑ What is the difference between the two capacitors?
Device and Systems Packaging
Fundamentals of Electrical Design Sep. 30, 2023 67
 FCC regulations

EMI
THERMAL NOISE
SUSCEPTIBILITY RADIATION

ATTENUATION
INTERCONNECT DELAY
Power Supply Noise CROSSTALK

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 68
 Radiation Models

r2 Loop antenna model Dipole antenna model

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 69
www.chimes.psu.edu

Device and Systems Packaging

Fundamentals of Electrical Design Sep. 30, 2023 70