Practice Questions (UNIT 4,5,6)
UNIT- 4
1. Signify the role of interrupts in process state transitions.
2. Write a short note on I/O device interfaces – SCSI and USB.
3. Differentiate between programmed I/O and DMA and interrupt initiated I/O.
4. Signify the role of interrupts stating that how it works.
5. With the help of a diagram explain the interrupt cycle.
6. Explain the working of DMA with the help of a diagram.
7. What do you mean by asynchronous data transfer? Explain the strobe control and
handshaking mechanism.
8. Discuss about Memory mapped I/O and Isolated I/O in detail.
9. Discuss about daisy chain and serial interrupt initiated I/O
10. Differentiate between privileged and non-privileged instructions.
Short Questions:
1. Differentiate between burst mode and cycle stealing mode.
2. Differentiate between interrupts and exceptions.
3. What is the need of interfaces in peripheral devices.
4. What are traps.
5. Differentiate between synchronous and asynchronous data transfer.
UNIT-5
1. Explain pipelining in detail with the help of an example.
2. Discuss the various types of pipeline hazards, including their effects.
3. Explain in detail the concept of an arithmetic pipeline with the help of a diagram.
4. Explain instruction pipeline with 4-stages with the help of a diagram.
5. Consider the execution of a program of 20000 instructions by a linear pipeline processor with
a clock cycle rate of 40 MHz. Assume that the instruction pipeline has five stages and that
one instruction is issued per clock cycle. Calculate the speedup of the pipeline over its
equivalent non-pipeline processor along with throughput and efficiency.
6. Discuss memory interleaving.
7. Mention some ways to mitigate control hazards.
Short Questions:
1. Define throughput and speedup in pipelining.
2. What is the importance of Space-Time diagram.
3. Draw a three- segment pipeline.
4. Discuss the performance factors of pipelining.
5. Give the formula for speedup.
6. What is the need for delay-load.
UNIT-6
1. What is the need of memory hierarchy? Also, explain locality of reference principle.
2. Apply three cache replacement policies (FIFO, LRU, Optimal) on the following block
requests considering associative mapping with four number of cache blocks. Find the number
of cache hits in all three policies.
Block requests are as follows: 0,4,8,7,3,7,8,1,2
3. What is cache coherence problem and cache write policies.
4. Explain direct, associative and set-associative and cache mapping organizations.
5. A block set associative cache consists of a total of 64 blocks divided into 4 block sets. The
main memory consists of 4096 blocks, each consisting of 128 words. Compute the bits in
TAG, SET and OFFSET fields.
6. Demonstrate Flynn’s Classification.
7. Explain the method of virtual to physical address translation with the help of diagram.
8. The average memory access time for a machine with cache hit rate of 80% where the cache
access time is 5 ns and memory access time is 100 ns?
(Note - Tavg = H1T1 + (1-H1) (T1+T2) )
9. Calculate the total access time if miss rate is 0.25, miss penalty is 0.78ms and cache access
time is 5 microseconds. (Note here miss penalty time refers the memory access time)
10. A computer employs RAM chips of 128 x 8 and ROM chips of 512 x 8. The computer system
needs 512 bytes of RAM, 512 bytes of ROM. A memory-mapped 1/0 configuration is used.
The two bits of the address bus are passed to decoder for selection of RAM. Draw a memory
connection to CPU.
Short Questions:
1. In what way does cache size play a role in determining the hit rate?
2. What is dirty bit in cache.
3. What is virtual memory.
4. Explain cache size vs. block size.
5. Explain ROM organization with the help of chip diagram.
