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Pete Dice
Quick Boot
ISBN 978-1-5015-1538-5
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© 2018 Pete Dice

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Acknowledgments
The studies, data, results, and guidelines compiled in the book are the result
of many talented engineers at Intel who have a strong passion for BIOS and
firmware. The contributions they have made and the time they have spent,
much of it outside their normal duties, deserve to be acknowledged.
 For significant contributions to this book for analyses, cases studies, and
written content, I’d like to thank these talented engineers:

–Jim Pelner—who crafted the original white paper that echoes the main
themes of this book and for contributing to several chapters early
on.

–Jaben Carsey—who wrote the shell chapter in the book above and
beyond his many contributions to the UEFI shells in general.

–Sam Fleming—who created Appendix A and has been one of my

mentors in BIOS from the beginning.

–Mike Rothman, Anton Cheng, Linda Weyhing, Rob Gough, Siddharth

Shah, and Chee Keong Sim—for their exquisite multiyear
collaboration around the fast boot concept and multiple case studies
over the year.

–BIOS vendor Insyde Software for donating feedback and volunteering

for the foreword.

Thanks to my program manager, Stuart Douglas, for getting me through the

writing phase and then on to the finish line (are we there yet?).
Reviewer comments and suggestions were extremely valuable for both
editions of this work. I deeply appreciate those who took the time to provide
indispensable feedback, including Drew Jensen, Mark Doran, Jeff Griffen,
John Mitkowski, and Dong Wei and at my publisher, Jeff Pepper, Megan
Lester, Mark Watanabe and Angie MacAllister for her work on fixing the art
and tables.
I would also like to acknowledge my peers in the BIOS/FW engineering
and architecture teams within the computer industry for their drive to make
this technology an ever more valuable (and less obtrusive) part of people’s
everyday lives. Lastly, I want to thank my wife, Anita, for her patience and
everything she’s done to allow me time to complete this.

Contents
Chapter 1: System Firmware’s Missing Link

Start by Gathering Data

Initialization Roles and Responsibilities

System Firmware

OS Loader

Operating System

Legacy BIOS Interface, UEFI, and the Conversion

Tiano Benefits

Previous UEFI Challenges

Persistence of Change

The Next Generation

Commercial BIOS Business

Award

General Software

Phoenix Technologies Limited

American Megatrends Inc.

Insyde Software

ByoSoft

Value of BIOS

Proprietary Solutions

Making a Decision on Boot Firmware

Consider Using a BIOS Vendor

Consider Open-Source Alternatives

Consider Creating Something from Scratch

Consider a Native Boot Loader for Intel ® Architecture

Just Add Silicon Initialization

Summary

Chapter 2: Intel Architecture Basics

The Big Blocks of Intel Architecture

The CPU

The Front Side Bus

The North Bridge, PCIset, AGPset, MCH, Uncore, System Agent

The Transparent Link (Hublink, DMI, ESI)

The South Bridge, Also Known as the PIIX, I/O Controller Hub (ICH),
I/O Hub (IOH), Enterprise South Bridge (ESB), and Platform
Controller Hub (PCH)

Data Movement Is Fundamental

It’s a Multiprocessing System Architecture

The Memory Map

I/O Address Range

The Operating System

Summary

Chapter 3: System Firmware Terms and Concepts

Typical PC/Intel® Architecture Overview

Memory Types

Processor Cache
System Memory

Complementary Metal-Oxide Semiconductor (CMOS)

System BIOS Flash Memory (NVRAM, FWH, or SPI)

Real-Time Clock (RTC)

System Memory Map

Legacy Address Range

Main Memory Address Range

PCI Memory Address Range

Splash Screen

Status and Error Messages

Display Messages

Beep Codes

POST Codes

Master Boot Record

GUID Partition Table

Real Mode

Protected Mode
Logical Addressing

Flat Protected Mode

Reset Vector

Programmable Interrupt Controller

Advanced Programmable Interrupt Controller

The I/OxAPIC

The Local APIC

Summary

Chapter 4: Silicon-Specific Initialization

Listen to the Designer, Then Experiment, and Fix It

Chipsets

Processors

Basic Types of Initialization

Simple Bits

Standard Algorithms, Minding the Ps and Qs

Custom Algorithms: It’s All About Me

Option ROMs
Summary

Chapter 5: Industry Standard Initialization

PCI

PCI Device Enumeration

PCI BIOS

PCI IRQ Routing with ACPI Methods

PCI Recommendation

PCI Power Management

USB Enumeration and Initialization

PCI Enumeration and Initialization of USB Controllers

USB Wake from ACPI Sx (S3, S4, S5 to S0)

USB Enumeration

SATA

SATA Controller Initialization

Setting the SATA Controller Mode

Enabling SATA Ports

Setting the Programming Interface

Initializing Registers in AHCI Memory-Mapped Space

RAID Mode Initialization

Additional Programming Requirements During SATA Initialization

External SATA Programming

Compliance with Industry Specifications

Advanced Configuration and Power Interface (ACPI)

ACPI Tables

ACPI Namespace

Summary

Chapter 6: System Firmware Debug Techniques

Host/Target Debugging Techniques

Hardware Capabilities

POST Codes

Audio (Beep) Codes

Serial Port

In-Target Probe (ITP), a Form of JTAG Port

Software Debug Methods

Console Input/Output

Abstraction

Disable Optimization

Where Am I in the Firmware?

When Hardware Isn’t Stable, Where Do I Start?

Debugging Other People’s Code

Debugging PCI Option ROMs or Binary Libraries

Debugging Library Code (No Source)

Debugging Beyond Firmware

Real Mode Interrupts

System Management Mode

Industry Specifications

Pitfalls

Summary

Chapter 7: Shells and Native Applications

Pre-OS Shells

UEFI Shell Application

EFI/UEFI Script File

Different Features between Script and App

Customizing the UEFI Shell

Where to Get Shells

GUIs and the UEFI Shell

Remote Control of the UEFI Shell

Debugging Drivers and Applications in the EFI and UEFI Shells

The End for the Shell

Summary

Chapter 8: Loading an Operating System

The Boot Path

The Bus

The Device

The Partition Table

The File System

Booting via the Legacy OS Interface

Master Boot Record

Loading the Legacy OS Loader

Legacy BIOS to OS Handoff Requirements

Booting via the EFI Interface

Default EFI Boot Behavior

Direct Execution of a Linux Kernel

UEFI Runtime Services

Neither Option

Summary

Chapter 9: The Intel ® Architecture Boot Flow

Hardware Power Sequences (The Pre-Pre-Boot)

Nonhost-Based Subsystem Startup

Starting at the Host Reset Vector

Mode Selection

Early Initialization

Single-Threaded Operation

Simple Device Initialization

Memory Configuration
Post-Memory

Shadowing

Exit from No-Eviction Mode and Transfer to DRAM

Transfer to DRAM

Memory Transaction Redirection

Application Processor (AP) Initialization

Advanced Initialization

General Purpose I/O (GPIO) Configuration

Interrupt Controllers

Interrupt Vector Table (IVT)

Interrupt Descriptor Table (IDT)

Timers

Memory Caching Control

Serial Ports

Clock and Overclock Programming

PCI Device Enumeration

Graphics Initialization
Input Devices

USB Initialization

SATA Initialization

SATA Controller Initialization

Memory Map

Region Types

Region Locations

Loading the OS

Summary

Chapter 10: Bootstrapping Embedded

Optimization Using BIOS and Bootloaders

Platform Policy (What Is It and Why Is It Here?)

Case Study Summaries

Example 1

Example 2

Example 1 Details

What Are the Design Goals?

What Are the Supported Target Operating Systems?

Do We Have to Support Legacy Operating Systems?

Do We Have to Support Legacy Option ROMs?

Are We Required to Display an OEM Splash Screen?

What Type of Boot Media Is Supported?

What Is the BIOS Recovery/Update Strategy?

When Processing Things Early

Is There a Need for Pre-OS User Interaction?

A Note of Caution

Additional Details

Example 2 Details

Turn Off Debugging

Decrease Flash Size

Caching of PEI Phase

Intel SpeedStep® Technology Enabled Early

BDS Phase Optimization

Platform Memory Speed

Remove PS/2 Keyboard/Mouse

Remove BIOS Setup

Remove Video Option ROM

Remove BIOS USB Support

Divide Long Lead Pieces into Functional Blocks and Distribute Across
the Boot Flow

Summary

Chapter 11: Intel’s Fast Boot Technology

The Human Factor

Responsiveness

The (Green) Machine Factor

Boot Time Analysis

First Boot versus Next Boot Concept

Boot Mode UEFI Configuration Setting

Fallback Mechanisms

Baseline Assumptions for Enabling Intel Fast Boot

Intel Fast Boot Timing Results

Summary
Chapter 12: Collaborative Roles in Quick Boot

Power Hardware Role

Power Sequencing

Power Supply Specification

Flash Subsystem

High Speed SPI Bus for Flash

Flash Component Accesses

SPI Prefetch and Buffer

SPI Flash Reads and Writes

Slow Interface and Device Access

DMI Optimizations

Processor Optimizations

CPU Turbo Enabling

Streamline CPU Reset and Initial CPU Microcode Update

Efficient APs Initialization

Caching Code and Data

Main Memory Subsystem

Memory Configuration Complexity

Fast and Safe Memory Initialization

Hardware-Based Memory Clearing

Efficient Memory Operations Instruction Usage

SMBus Optimizations (Which Applies to Memory Init)

Minimize BIOS Shadowing Size, Dual DXE Paths for Fast Path versus
Full Boot

PCIe Port Disable Algorithm

Manageability Engine

Eliminating MEBx

Reducing Manageability Engine and BIOS Interactions

Graphics Subsystem

Graphics Device Selection

Graphics Output Protocol (GOP) Support for CSM-Free Operating

Systems

Panel Specification

Start Panel Power Early

Storage Subsystems
Spinning Media

Utilizing Nonblocking Storage I/O

Early SATA COMRESETs: Drive Spin-Up

CSM-Free Intel® Raid Storage Technology (Intel RST) UEFI Driver

Minimizing USB Latency

Power Management

Minimizing Active State Power Management Impact

Security

Intel® Trusted Execution Technology (Intel TXT)

TPM Present Detect and Early Start

Operating System Interactions

Compatibility Segment Module and Legacy Option ROMs

OS Loader

Legacy OS Interface

Reducing Replication of Enumeration Between Firmware and OS

Other Factors Affecting Boot Speed

No Duplication in Hardware Enumeration within UEFI

Minimize Occurrences of Hardware Resets

Intel Architecture Coding Efficiency

Network Boot Feature

Value-Add, But Complex Features

Tools and the User Effect

Human Developer’s Resistance to Change

Summary

Chapter 13: Legal Decisions

Proprietary License

Berkeley Software Distribution (BSD) License

Key Four Clauses to the Original License

Three-Clause BSD

General Public License (GPL)

Lesser GPL (LGPL)

Separating and Segregating Code

Conclusion

Appendix A: Generating Serial Presence Detection Data for Down

Memory Configurations
Analyzing the Design’s Memory Architecture

Calculating DIMM Equivalents

ECC Calculation

SDRAM Width Determination

SDRAM Chip Datasheet

SDRAM Architecture Analysis Example

Calculating Specific SPD Data Based on SDRAM Datasheet

SPD Field 0x00: Number of Bytes

SPD Field 0×01: SPD Revision

Byte 1: SPD Revision

SPD Field 0×02: Device Type

SPD Field 0×03: Module Type

SPD Field 0×04: SDRAM Density and Banks

SPD Field 0×05: SDRAM Rows and Columns

SPD Field 0×06: Nominal Voltage, VDD

SPD Field 0×07: Ranks & Device DQ Count

SPD Field 0×08: Module Bus Width

SPD Field 0×09: Fine Timebase Dividend/Divisor

SPD Field 0×0A and 0×0B: Medium Timebase Dividend/Divisor

SPD Field 0x0C: Cycle Time (tCKmin)

SPD Field 0×0E and 0×0F: CAS Latencies Supported

SPD Field 0×10: CAS Latency Time (tAAmin or tCL)

SPD Field 0×11: Write Recovery Time (twrmin)

SPD Field 0×12 RAS# to CAS# Delay (tRCDmin)

SPD Field 0x13: Min. Row Active to Row Active Delay (tRRDmin)

SPD Field 0×14: Min. Row Precharge Delay (tRPmin)

SPD Field 0×15: Upper Nibble of tRAS & tRC

SPD Field 0×16: Min. Active to Precharge Delay (tRASmin) LSB

SPD Field 0×17: Min. Active to Active Refresh Delay (tRCmin) LSB

SPD Field 0×18 and 0×19: Min. Refresh Recovery Delay (tRFCmin)

SPD Field 0×1A: Min. Write to Read Command Delay (tWTRmin)

SPD Field 0×1B: Min. Read to Precharge Command Delay (tRTPmin)

SPD Field 0×1C: tFAW Upper Nibble

SPD Field 0×1D: Min. Four Activate Window Delay (tFAWmin) LSB
SPD Field 0x1E: SDRAM Optional Features

SPD Field 0×1F: SDRAM Thermal and Refresh Options

SPD Field 0×20: Module Thermal Sensor

SPD Field 0x21: SDRAM Device Type

SPD Field 0×22–0×3B: Reserved

Module-Specific Section: Bytes 60–116

SPD Field 0×3C: (Unbuffered): Module Nominal Height

SPD Field 0×3D: (Unbuffered): Module Max. Thickness

SPD Field 0x3E: (Unbuffered): Reference Raw Card Used

SPD Field 0×3F: Unbuff Addr. Mapping from Edge Connector to

DRAM

SPD Field 0×40-0×74: Reserved

SPD Field 0×75 and 0×76: Module Manufacturer ID Code, LSB

SPD Field 0×77: Module Manufacturer Location

SPD Field 0×78 and 0×79: Module Manufacturing Date

SPD Field 0x7A–0x7D: Module Serial Number

SPD Field 0×7E and 0×7F: CRC Bytes

Bytes 126–127: SPD Cyclical Redundancy Code (CRC)

 SPD Field 0×80–0×91

SPD Field 0×92 and 0×93: Module Revision Code

SPD Field 0×94 and 0×95: DRAM Manufacturer ID Code

SPD Field 0×96–0×AF: Manufacturer’s Specific Data

SPD Field 0×B0–0×FF: Open for Customer Use

References for Appendix A

Index

Foreword from the First Edition

How do you explain what BIOS is? I generally explain it as the code that runs
when you first turn on the computer. It creates a level playing field so that the
operating system has a known state to start from. If the other person has some
programming knowledge, he or she generally says something like, “Oh.
You’re one of those guys!” Let’s face it. BIOS isn’t sexy. The hardware
engineers will always blame the BIOS engineers if the system fails to POST.
It’s generally up to BIOS engineers to prove it isn’t their code that is the
problem.
When I first started as a lowly BIOS Engineer II, the BIOS codebase
was pure x86 assembly code—thousands of files across almost as many
directories with lots of cryptic comments like, “I don’t know why this is here,
but it breaks if I remove or modify it! Beware!” It took 45 minutes to do a
clean compile. Comments would commonly refer to specifications that no
longer existed. To say a BIOS is filled with some secret, arcane algorithms is
like saying driving a Formula 1 car is just like driving on the freeway, only
faster! There are no college courses that teach BIOS programming. There are
no trade schools to go to. A few software and electronic engineers will be
able to make it as BIOS engineers because it takes a bit of both to be
successful.

This book is the first one I’m aware of that attempts to shine light onto
the esoteric field of BIOS engineering. A field that makes everything
from the big-iron servers to the lowly smartphone turn on. This book has
combined two fundamental concepts. What you need to know to make a
BIOS that works and what you need to know to make a BIOS that works
fast! It wasn’t that long ago that a POST in under ten seconds was
considered pretty fast. Today’s standard is now under two seconds.
There are topics outlined in this book that will help get you to that sub-
2-second goal. I am currently working on a quasi-embedded system that
is in the sub-1-second range with full measured boot using these
concepts!

This book has something for the recent college graduate as well as
the seasoned BIOS engineer. There are nuggets of tribal knowledge
scattered throughout. Help yourself become better acquainted with the
BIOS industry and read it.

–Kelly Steele,
Former BIOS Architect, Insyde Software, Inc.,
Now at Intel Corporation
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