VLSI Question bank for Semester EXAM

Define Moore's Law in the context of the development of VLSI technology.

What is the basic structure of a MOS capacitor? CO1

What is the basic difference between a CMOS and a CMOS transmission gate?

Plot the graph showing the different regions of operation of a CMOS.

What is the difference between a latch and a flip-flop?

Explain the various stages involved in the VLSI design flow. Discuss each stage briefly.

Explain the structural hierarchy of a 4-bit adder. Discuss how the individual 1-bit full adders are
combined to form the 4-bit adder.

Explain each step of fabrication for n-MOSFET

Explain different region of MOS Capacitor with energy band diagram.

Consider a MOS structure consisting of a silicon substrate with a Fermi potential above the valence
band, a silicon dioxide layer, and a metal gate. The equilibrium Fermi potential of the doped silicon
substrate is q∅_F=0.2eV. The electron affinities of silicon and the metal are 4.15 eV and 4.1 eV,
respectively. Calculate the built-in potential difference across the MOS system. Also, draw the
energy band diagrams of the components that make up the MOS system.

Draw the stick diagram of Y=((A+B)+C) ̅

Design the circuit the combinational Y=(A+B+C) ̅ using CMOS technology

Write the code of JK FF using Verilog code

Explain working principle of CMOS transmission gate and find effective resistance of three different
region

Derive V_IL and V_OH of the CMOS inverter.

Consider a resistive load n-MOS inverter circuit with VDD = 5 V, K’n=20 µA/V2, threshold voltage VT0
= 0.7 V, RL = 200 kΩ, & W/L = 1. Calculate the critical voltage (VOL, VOH, VIL, VIH) and the noise
margin of the circuit.

Find the Elmore delay at node 7 and node 5

Draw the CMOS SR-Latch circuit based on NOR gate and explain its function

and write the corresponding truth table

Find an equivalent (W/L)P and (W/L)n of CMOS inverter circuit for simultaneous switching of all
inputs, assuming that (W/L)p = 15 for all pMOS transistors and (W/L) = 10 for all nMOS transistors.

Why is the voltage bootstrapping method required? Explain with a circuit diagram and determine
the Cboot/Cs ratio.

Derive the average power of switching power dissipation of CMOS inverter .

Define accumulation and inversion region in MOS capacitor?

What is the basic difference between a static CMOS and a dynamic CMOS

What is the significance of CMOS technology in digital VLSI design?

Define the noise margin and write the expression noise margin high.

Explain the various VLSI design methodologies. Compare and contrast the Full-Custom, Semi-
Custom, and Programmable Logic design approaches in terms of design time, flexibility,
performance, and cost.

Explain different scaling models used in MOS circuits. Derive the scaling factors for key device
parameters such as channel length, gate area, and capacitance.

Discuss the key differences between dynamic logic and static CMOS logic. How do issues like charge
sharing, leakage, and cascading affect dynamic gate design in ultra-deep submicron technologies?

Draw the CMOS SR-Latch circuit based on NOR gate and explain its function and write the
corresponding truth table.

Explain the structural decomposition of a 4-bit adder. Illustrate the different levels of hierarchy
involved in combining individual 1-bit full adders to form the 4-bit adder.

Describe the fabrication process flow for manufacturing a VLSI (Very-Large-Scale Integration) chip.
Discuss the various steps involved, from wafer preparation to packaging.

Explain the behavior of a MOS (Metal-Oxide-Semiconductor) system under external bias. Derive the
expressions for the threshold voltage and discuss the effects of various external biases (gate, drain,
and source) on the operation of the MOS transistor.

Consider a MOS structure comprising a n-type doped silicon substrate, a silicon dioxide layer, and a
metal gate. The equilibrium Fermi potential of the doped silicon substrate is q∅_Fn = 0.2 eV.
Electron affinity of silicon and the metal are 4.15 and 4.1eV respectively. Calculate the built-in
potential difference across the MOS system. Draw the Energy band diagrams of the components that
make up the MOS system.

Draw the stick diagram of Y=((A+B)+C) ̅

Design the combinational logic circuit Y=(A.B.C) ̅ using CMOS technology

Write the code of SR FF using Verilog code

Explain working principle of CMOS transmission gate and find effective resistance of three different
region

Consider a CMOS inverter circuit with the following parameters: VDD =3.3 V V_(T,n)=0.6V,V_(T,p)=-
0.7 V k_n = 200 µA/V2 k_p= 80 µA/V2 (5.83) (5.84) Calculate the noise margins of the circuit..

Draw the CMOS SR-Latch circuit based on NAND gate and explain its function

and write the corresponding truth table

Find an equivalent (W/L)P and (W/L)n of CMOS inverter circuit for simultaneous switching of all
inputs, assuming that (W/L)p = 5 for all pMOS transistors and (W/L) = 6 for all nMOS transistors.
Explain the voltage bootstrapping method and discuss the need for bootstrapping, illustrate the
working with a suitable circuit diagram, and derive the expression for the capacitor ratio .C_boot/C_

Observe the given circuit and find the voltage V1, V2, V3, V4, and V5. Consider the threshold voltage
for nMOS transistor M1, M2, M3, M4, and M5 as VTH1, VTH2, VTH3, VTH4, and VTH5 respectively.

Explain the fabrication steps for fabricating n-type metal oxide semiconductor field effect transistor.

Explain the CMOS fabrication process in detail. How does it differ from nMOS and pMOS fabrication
techniques?

Explain the working principle of n-MOSFET for different gate bias condition. Draw its cross-sectional
view to explain its region of operation.

Why CMOS has become the dominant technology in VLSI design. Discuss the limitations and
advantages of other similar technology.

Explain and compare various semi-custom design methodologies used in VLSI design.

Differentiate between Logical Design and Physical Design phases in VLSI design flow. Explain how
design constraints are handled in each phase.

Draw the circuit of CMOS inverter. Explain its corresponding transfer characteristics curve and draw
its stick diagram.

Explain the basic operation of a dynamic CMOS logic gate. With the help of a diagram, describe the
precharge and evaluation phases.

Differentiate between a latch and a register. Explain the operation of a master-slave D flip-flop using
a block diagram.

Differentiate static and dynamic logic. What are the advantages and challenges in using dynamic
logic?

Describe the concept of pipelining in CMOS design. How does a clocked CMOS register help in
pipeline implementation?

Explain n-well and p-well techniques in IC fabrication. Explain the fabrication steps for nMOS.

Explain VLSI Design flow with neat sketch.

Compare the different layout styles used in VLSI design. Explain their advantages, limitations and
typical applications.

Explain the purpose of stick diagrams in VLSI design. Describe the different layers used and draw
stick diagrams for a basic CMOS inverter.

What are layout design rules in VLSI? Discuss the importance of these rules and illustrate how they
are applied in the layout of MOS circuits with suitable diagrams.

Explain the sheet resistance and how it is applied to MOS transistors and inverters. How does it
affect the performance of VLSI circuits?
Discuss the role of area and wiring capacitance in determining the propagation delay of CMOS
circuits. Explain the concept of the standard unit of capacitance and how it is used in delay
estimation.

What are propagation delays in VLSI circuits? Explain how inverter delays are affected when driving
large capacitive loads, and discuss the methods to minimize such delays.

Explain bottom up approach in VLSI design.

Draw the symbol of enhancement and depletion type of n-MOSFET.

What is parasitic capacitance in CMOS circuit?

What is interconnect delay in VLSI circuit?

Draw the nMOS pass transistor, and explain its working