Introduuction to HDL

• We are familiar with the design of a digital system. The basic steps involved in
this process are,

a. Specify the desired behaviour of the circuit.

b. Synthesize the circuit.

c. Implement the circuit.

d. Test the circuit to check whether the desired specifications meet.

• But as the size and complexity of digital systems increase, they can not be
designed manually; their design becomes highly complex. At their most detailed
level, they may consists of millions of elements, i.e. transistors or logic gates.
So Computer Aided Design (CAD) tools are used in the design of such systems.
One such a tool is a Hardware Description Language (HDL).

HDL describes the hardware of digital systems. This description is in textual

form. The Boolean expressions, logic diagrams and digital circuits (simple and
complex) can be represented using HDL. The features of HDL are :

■ The HDL provides the digital designer with a means of describing a digital
system at a wide range of levels of abstraction and at the same time, provides
access to computer-aided design tools to aid in the design process at these
levels.

■ The HDL, represents digital systems in the form of documentation which can
be understood by human as well as computers.

■ It allows hardware designers to express their design with behavioral

constructs. An abstract representation helps the designer explore architectural
alternatives through simulations and to detect design bottlenecks before detailed
design begins.

■ The HDL makes it easy to exchange the ideas between the designers.

■ It resembles a programming language, but the orientation of the HDL is

specifically towards describing hardware structures and behavior. The storage,
retrieval and processing of programs written using HDL can be performed
easily and efficiently.
■ HDLs are used to describe hardware for the purpose of simulation, modeling,
testing, design and documentation.

■ The most prominent modem HDLs in industry are Verilog and VHDL.
Verilog is one of the two major Hardware Description Languages (HDLs) used
by hardware designers in industry and academia. Of course, VHDL is the other
one.

■ Verilog is very C-like and liked by electrical and computer engineers as most
learn the C language in college. VHDL is very Ada-like and most engineers
have no experience with Ada.

Structure of VHDL Module

• The main components of a VHDL description consists of following kinds of
declarations :

■ Package (optional)

■ Entity

■ Architecture

■ Configuration (optional)

• The Fig. 10.2.1 shows the relationship of these basic blocks of VHDL
program. A design may include any number of package, entity, architecture and
configuration declarations. It is important to note that the entity and architecture
blocks are compulsorily required; however, the package and configuration
blocks are optional.
1. Entity Declaration
• It gives the specification of input/output signals to external circuitry. An entity
is modeled using an entity declaration and at least one architecture body. An
entity X, when used in another entity Y, becomes a component for the entity Y.
Entity gives interfacing between device and the other peripherals. An entity
usually has one or more ports, which are analogous to the pins on a schematic
symbol. All information must flow into and out of the entity through the ports.
Each port must contain name, data flow direction and type.

• The syntax of a VHDL entity declaration is as shown below.

entity entity_name is

port ( signal_names : mode signal_type;

signalnames : mode signal_type;

signal_names : mode signal_type);

end entity_name ;

The following section describes the different elements of entity declaration.

entity_name : It is an identifier selected by the user to name the entity.

signal_names : It is a list of user selected identifiers to name external interface

signals.

mode : The ports can be declared in four types which specify the signal
direction.

in : This mode is used for a signal that is an input to an entity (value is read not
written).

out : It is used for a signal that is an output from an entity. The value of such a
signal can not be read inside the entity's architecture. But it can be read by other
entities those use it.

inout : It is used for a signal that is both, an input to an entity and an output
from the entity.

buffer : The signal is an output from the entity and its value can also be read
inside the entity's architecture.

signal_type : It is a built-in or user defined signal type.

For example, there is a system having its inputs and outputs like rd, wr, ADD, x,
y, z, ad, al. The entity for this can be written as shown below.

entity gate_logic is port (

wr : in std_logic;

rd : in std_logic;

ad : inout std_logic_vector (7 downto 0) ;

ADD : in std_logic_vector (0 to 3) ;

x,y,z : out std_logic;

al : buffer std_logic_vector (7 downto 0)

);

end gate_logic ;

Here rd, wr are inputs to the system so they are input ports. The ad is also input
signal but it is 8 bit so it is defined as vector (7 downto 0). It means 7 is
assigned to MSB of your signal and 0 is assigned to LSB of your signal.
Similarly x, y, z are output signals so they are defined as output ports. The al is
coming out and is defined as buffer signal, so that you can also read this signal.

2. Architecture
• Architecture specifies behavior, functionality, interconnections or relationship
between inputs and outputs. It is the actual description of the design. An
architecture consists of two portions : architecture declaration and architecture
body. An architecture body specifies the internal details of an entity.

■ As a set of concurrent assignment statements (to represent dataflow)

■ As a set of interconnected components (to represent structure)

■ As a set of sequential assignment statement (to represent behavior)

■ As any combination of above three.

• The syntax for architecture is given below

architecture architecture_name of entity_name is Declarations

begin

concurrent statements;

sequential statements;

end architecture_name;

• To design any system, first we have to write the entity. In the architecture, we
write architecture_name for that entity. In declaration part, types, signals,
constants, function definitions, procedure definitions, component definitions
etc. can be declared. The variables can also be declared here. VHDL variables
are similar to signals, except that they usually do not have physical significance
in a circuit. A variable declaration is similar to a signal declaration, except that
the 'variable' keyword is used as shown below.

variable variable_names : variables_type;

Example :

3. Configuration Declaration
• Configuration declarations may be used to associate particular design entities
to component instances (unique references to lower-level components) in a
hierarchical design, or to associate a particular architecture to an entity. As their
name implies, configuration declarations are used to provide configuration
management and project organization for a large design.

• Example of configuration declaration :

library CMOS_LIB, MY_LIB

Configuration HA_BINDING of HALF_ADDER is

For HA_STRUCTURE

For XI : XOR2

Use entity CMOS_LIB.XOR_GATE (DATAFLOW);

end for;

For A1 : AND2

Use configuration MY_LIB.AND_CONFIG;

end for;

end for;

end HA_BINDING;

The library statement makes library names CMOS_LIB and MY_LIB visible
within the configuration declaration.

HA_BINDING is name of the configuration and it specifies a configuration for

the HALF_ADDER entity.

The statement for HA_STRUCTURE specifies that the architecture body

HA_STRUCTURE is selected for this configuration.

• As shown by the shaded portions there are two component bindings. The
component instantiation XI is bound to an entity represented by XOR-GATE
entity declaration and the DATAFLOW architecture body, which resides in the
CMOS_LIB design library. Similarly, component instantiation A1 is bound to a
configuration of an entity defined by the configuration declaration, with name
AND_CONFIG, residing in the MYJLIB design library.

4. Package Declaration
• There are some declarations which are common across many design units. A
package is a convenient mechanism to store and share such declarations. It is an
optional design unit. A set of declarations contained in a package declaration
may be shared by many design units. It defines items that can be made visible to
other design units. A package is represented by :

■ Package declaration

■ Package body (optional)

Package declaration

• It defines the interface to the package. The syntax of a package declaration is

given below.

PACKAGE package_name IS

type declarations

subtype declarations

constant declarations

signal declarations

variable declarations

subprogram declarations

file declarations

alise declarations

component declarations

attribute declarations

attribute specifications

disconnection specifications

use clauses

END package_name;

• The items declared in a package declaration can be accessed by other design

units by using the 'library' and 'use' clauses. This is explained in the further
section. The example of package declaration is given below.

package MUX 4-to-l_package is

component MUX 4-to-l

port (MO, Ml, M2, M3 : IN STD_LOGIC;

s : IN STD_LOGIC_VECTOR

(1 downto 0)

f : OUT STD_LOGIC ;

end component;

end MUX 4-to-l_package;

5. Package Body
• It contains the details of a package, that is the behavior of the subprograms and
the values of the deferred constants which are declared in a package declaration.
The package body may contain other declarations.

• The syntax of it is as given below.

package body package_name is

subprogram bodies

complete constant declarations

subprogram declarations

type and subtype declarations

file and alias declarations

use clauses

end package_name;

• The name of the package must be same as the name of its corresponding
package declaration. If the package declaration does not have any subprogram
or deferred constant declarations, a package body is not necessary.
Styles of Modeling
AU : Dec.-14, 15, 16, 17, May-15

• In a VHDL or Verilog program, architecture body (VHDL) or the module

(Verilog) contains a series of concurrent statements. All concurrent statements
execute simultaneously. HDL has several different concurrent statements. Also,
it has a mechanism which bundles a set of sequential statements which operate
as a single concurrent statement. The way in which these statements are used is
called the modeling style or types of descriptions. Thus these statements give
rise to six different modeling styles or types of descriptions as,

* Behavioral

* Data flow

* Structural

* Switch-level

* Mixed-Type

* Mixed-Language

• Let us see the VHDL description of full adder shown in the Fig. 10.3.1 in
various modeling styles.
1. Behavioral Description
• It is sometimes possible to directly describe the behavior or the functionality
of a circuit. Such a modeling style is called behavioral modeling which is very
similar in syntax and semantics to that of a high-level programming language
(For example : C, Pascal). A behavioral description models the system as to
how the outputs behave with the inputs.

• In VHDL, the behavior of the entity is expressed using sequentially executed,

procedural code. The key mechanism used to model the behavior of the entity
is, a process statement.

Listing 10.3.1 : Example of VHDL behavioral

description

entity full_add is

port (A, B, Cin : in bit;

Sum, Cout : out bit);

end full_add;

architecture adder of full_add is

begin

process (A, B, Cin)

begin

Sum < = A xor B xor Cin;

Cout < = (A and B) or (Cin and A) or (Cin and B);

end process;

end adder;

In Verilog, the key mechanism used to model the behavior is predefined words
always or initial.
Listing 10.3.2 : Example of Verilog behavioral

description

module full_add (A, B, Cin, Cout, Sum);

input A, B, Cin;

output Sum, Cout;

reg Sum, Cout;

always @(A, B, Cin)

begin

Sum = (A Λ B) Λ Cin;

Cout = (A & B) | (Cin & A) | (Cin & B);

end

endmodule

2. Dataflow Description
• Data flow describes how the circuit signals flow from the inputs to the outputs.
There are some concurrent statements which allow to describe the circuit in
terms of operations on signals and flow of signals in the circuit. When such
concurrent statements are used in a program, the style is called a 'dataflow
design'. Concurrent signal assignment statements are used in this type of
modeling style.

Listing 10.3.3 : Example of VHDL data-flow

description

entity full_add is

port (A, B, Cin : in bit;

Sum, Cout : out bit); end full_add;

architecture adder of full add is

begin

Sum < = A xor B xor Cin;

Cout < = (A and B) or (Cin and A) or (Cin and B);

end adder;

In Verilog, predefined word assign is used to assign a value to the left-hand side
of a signal-assignment statement.

Listing 10.3.4 : Example of Verilog data-flow

description

module full_add (A, B, Cin, Cout, Sum);

input A, B, Cin;

output Sum, Cout;

assign Sum = (A Λ B) Λ Cin;

assign Cout = (A & B) | (Cin & A) | (Cin & B);

endmodule

• The built in operators of VHDL (for example : AND, OR, NOT) and verilog
(for example & I A) are used in the expression.

• Here, the data flow model for the full_add is described using a two concurrent
signal assignment. In a signal assignment statement, the symbol <= implies an
assignment of a value to a signal in VHDL. The value of the expression on the
right-hand-side of the statement is computed and is assigned to the signal on the
left-hand-side, called a target signal. In Verilog, predefined word assign is used
to assign a value to a signal. A concurrent signal assignment is executed only
when any signal in the expression on the right-hand-side has an event on it, that
is, the value of the signal changes.
3. Structural Description
• In structural design, a VHDL and verilog uses components or gates to model
the system. The important features of VHDL structural type of architecture
body are :

■ Design hierarchy

■ Components are used

■ Each component is simulated separately

• In the structural modeling, an entity is described as a set of components

connected by signals, that is, as a netlist. The components used in an
architecture may be from a library or may be ones that were previously defined
as part of a design.

entity full_add is

port (A, B, Cin : in bit;

Sum, Cout : out bit);

end full_add;

architecture adder of full_add is

component xor3

port ( II, I2,I3 : in bit;

O1 : out bit);

end component;

component and2

port ( I1, I2 : in bit;

O1 : out bit);

end component;

component or3
port ( I1, I2,I3 : in bit;

O1 : out bit);

end component;

signal S1, S2, S3 : bit;

begin

Y1 : xor3 port map (A, B, Cin, Sum);

XI : and2 port map (A, B, SI);

X2 : and2 port map (A, Cin, S2);

X3 : and2 port map (B, Cin, S3);

Y2 : or3 port map (SI, S2, S3, Cout);

end adder;

• The name of the architecture body is adder. The entity declaration for full_add
specifies the interface ports for this architecture body. The architecture body is
composed of two parts : the declarative part (before the keyword begin) and the
statement parts (after the keyword begin). The components may either be
predefined components in a library or they may later be bound to other
components in a library. The declared components are instantiated in the
statement part of the architecture body using component instantiation statement.
Yl, XI, X2, X3, Y2 are component labels for this component instantiations. Il is
connected to signal A, 12 is connected to signal B, 13 is connected to signal
Cin, and O1 is connected to Sum in portmap xor3 gate. Similarly, port maps for
and 2 and or 3 are defined. Note that in this case, the signals in the port map of a
component instantiation and the port signals in the component declaration are
associated by position. A component instantiation statement is a concurrent
statement.
VHDL Identifiers and Types
There are two types of identifiers in VHDL :

• Basic identifiers

• Extended identifiers

Basic identifier : The base identifier in VHDL is composed of a sequence of

one or more characters. Legal characters are ;

• Lower case letter (a ... z)

• Upper case letter (A ... Z)

• Digit (0 ... 9)

• Underscore (_)

Note 1. The first character in a basic identifier must be a letter, and the last
character may not be an underscore.

2. The characters are not case sensitive. Therefore, as an example, NUM, num
and Num are considered to be same identifier.

Examples : Signal l, H Adder

Extended identifier : The extended identifier in VHDL is a sequence of

characters written between two backslashes. Here, any allowable characters can
be used including characters like . , !, @, ', and $. Examples : /COUNT/ , /- 125/
, /TTL/ /Process/

Note 1. Extended identifiers are case sensitive. Thus Num and NUM are distinct
identifiers.

2. Even though two blackslashes includes keyword it is a valid identifier. For

example, /process/ is distinct from keyword process.

Other important points while representing any module in VHDL

1. Each statement in VHDL is terminated with a semicolon (;).

2. The name of the ports must be followed by a colon (:).

3. The architecture body starts with the predefined word begin, followed by
statements that detail the relationship between the outputs and inputs.

4. The comment should begin with two hyphens (“)•

5. Leaving the blank spaces between two words or at the beginning of the line
are allowed.

6. Leaving the blank line(s) is allowed in the module.

VHDL Data Objects

• A data object holds a value or a range of values of a specified type. It is
created by means of an object declaration. In VHDL, there are four classes of
data objects, signals, variables, constants and file.

1. Signal
• A signal is data object which holds a list of values. These values include the
current value of the signal and also a set of possible future values that are to
appear on the signal. The signal represents a wire/logic signal in a circuit. In
VHDL, the signal can be placed in any of the following three places,

a) An entity declaration,

b) The declaration section of an architecture,

c) The declarative section of a package.

• The syntax for declaring signal is as follows :

SIGNAL signal_name : typename;

In this, the type_name indicates the legal value of the signal. The different
signal types are : BIT, BIT.VECTOR, BOOLEAN,
INTEGER,ENUMERATION, SIGNED, UNSIGNED, STD_LOGIC,
STD_LOGIC_VECTOR, STD_ULOGIC etc.

The examples are given below.

SIGNAL X : BIT;

• This signal declares the signal object X which is of type BIT. The initial value
of this signal is 'O' as 'O' is the leftmost value of type BIT.

2. Variable
• A variable is used to hold a signal value of a given type. Unlike a signal, a
variable does not necessarily represent a wire in a circuit. Variables can be
assigned a single value of a specific type. The different values can be assigned
to the variable at different times. For this a variable assignment statement is
used. The variable declaration has the following form :

VARIABLE variablename : variabletype : = initial value; For example,

VARIABLE index : INTEGER RANGE 0 TO 20 : = 0;

• Here, the variable 'index' is an integer having values between 0 and 20 and is
initialized to the value 0.

• The variables are used for computations within procedures, functions and
processes. The variables are sometimes used for the index variables in loops.

They are also sometimes used to hold the results of computations.

3. Constant
• The syntax for declaring a constant in a VHDL is given below.

CONSTANT constant_name : type_name : = value;

For example,

CONSTANT BUS_SIZE : INTEGER := 32; - width of component

• It is to be noted that the value of a constant can be a simple expression.

4. File
• This is a special class of data objects. It serves as the interface between VHDL
programs and the host environment. There are some special operations that can
be performed only on files. These are reading and writing files. The basic
operations that we need for reading and writing files are as given below.

• Declaration of a file type

■ Declaration of a file

■ Opening and closing a file of a specified type

■ Reading from a file and writing to a file

• Now we will discuss each operation with example.

1. File type declarations

• While declaring a file, we should ensure that the host environment correctly
interprets the format of the data which is stored in the file. So before declaration
of the file, it is necessary to declare its type. For example, text file. This file
consists of text strings of variable length. The syntax of a file type declaration is
as given below,

TYPE file_type_name IS FILE OF type_name;

The type_name is the type of values contained in the file. For example,

TYPE TEXT IS FILE OF string;

This defines a file of type TEXT that has a sequence of strings as values in it.

2. File declarations

• After declaring a particular type of a file, we can declare a file object. The
syntax of a file declaration is as given below,

FILE file_names : file_type_name [open mode] IS string_expression;

• The file can be used as a read-only, write-only or in the append mode. The
mode in the syntax specifies any of these utilization. The host-environment
interprets the string expression as the physical name of a file. For example,
FILE Input_File : TEXT OPEN READ-MODE IS

"/user/home/add.txt";

• Here, a file Input_File is declared to be of file type TEXT. That is, it has a
sequence of strings. The READ_MODE specifies that the file will be opened in
read-only mode. The string expression given after the keyword 'IS' specifies the
path name to a physical file in the host environment.

3. Opening and closing files

• After declaring file of a specific type, it is necessary to open the file before
using it and to close it before terminating the program. There are procedures and
functions to open and close a file. These are given below :

PROCEDURE FILE_OPEN (FILE FI: file_type_name;

file_name : IN STRING;

OPENKIND : IN FILEOPENKIND : =

READMODE);

- - Opens the file FI that points to the physical file specified in the string
file_name - - with the specified mode. Type FILE_OPEN_KIND has value
READ_MODE.

A file can be opened in three modes, READ_MODE, WRITE_MODE and

APPEND_MODE. The default mode is READ_MODE.

PROCEDURE FILE_OPEN (file_status : OUT

FILE_OPEN_STATUS;

file FI : file_type_name;

file_name : IN STRING

OPEN KIND : IN FILE OPEN KIND : = READ MODE);

- - This procedure returns the file open status, (other things are -similar to the
first procedure).

The FILE_OPEN_STATUS has a value returned by the procedure.

• This parameter may have one of the following four values.

1. OPEN_OK : File open operation was successful.

2. STATUS_ERROR : Attempted to open an already open file.

3. NAME_ERROR : File not found or not accessible.

4. MODE_ERROR : File cannot be opened in this mode.

• The value of FILE_OPEN_STATUS can be checked to ensure that the

FILE_OPEN call was successful.

PROCEDURE FILE_CLOSE (File F : file_type_name);

• The FILE_CLOSE procedure closes the file. There exists an implicit call to
FILE_CLOSE procedure which is called when execution terminates.

VHDL Data Types and Operators

AU : Dec.-11, 12, 15, 16, May-16

• VHDL supports a variety of data types. The type of a variable, signal, or

constant determines the operators that are predefined for that object as well as
the range of values that it can take on. The VHDL data types can be broadly
classified into following five data types :

1. Scalar types : The scalar types include numeric data types and enumerated
data types. The numeric types consist of integer, floating point (real) and
physical types. Bit, Boolean and character are all enumerated types.

2. Composite types : Array and record types are composite data types. The
values of these types are collection of their elements.

3. Access types : They are pointers; they provide access to objects of a given
data type.

4. File type : They provide access to object that contain a sequence of values of
a given type.

5. Other types : They include the data types provided by the several external
libraries.
1. Scalar Types
• We have seen that, the scalar types consist of enumeration types, integer types,
physical types, and floating point types. Enumeration, data types and integer
types are called discrete types. On the other hand, integer types, floating point
types and physical types are called numeric types.

Integer type

• As the name indicates, it covers all integer values, the values can be positive
or negative. The default range of Integer is -2147483647 to +2147483647.
However, user can specify a shorter range by using the predefined word range.
The shorter range may require less bits to represent the number when binary
encoded. We can define the subtype of base type whose range must be wholly
contained within the bounds of the range of base type.

Examples :

type num is integer;

type long is range -32768 to 32768; -- 16-bit binary encoding.

type short is range 0 to 255; -- 8-bit binary encoding.

subtype shorter is short range 0 to 31; -- 5-bit binary encoding.

subtype shortest is short range 0 to 15; -- 4-bit binary encoding.

Note : The encoding of integers in a binary format means that all ranges are
rounded up to the nearest power of two. This means that if shorter had been
declared as :

subtype shorter is short range 0 to 15;

• Then the object is synthesized into 4 wires. Objects declared type of type
integer without a range constraint will be synthesized into 32 wires.

Real (floating point) type

Example of integer object declaration :

Port (Il : in integer ;

O1 : out integer);

• Floating point type definition defines both a type and subtype of that types.
The default range of floating point is -1E38 to + IE38. Like integer type, here
also we can specify the shorter range by using the predefined word range.

Examples :

type Real_data is real;

type Voltage is range to -12.0 to +12.0;

subtype min voltage is range -5.0 to +5.0;

Example of real object declaration :

Port (Il : in real ;

O1 : out real);

Enumerated types

Bit, Boolean, Character and severity_level are the enumerated types. These are
defined in a library such as std or ieee.

Bit data type allows only two values 0 or 1. It is used to describe a signal that
takes only l(High) or 0(Low). The type Boolean has two values, True(l) or
False(0). Both True and False are predefined words.

The type character constitutes the 128 characters of the ASCII character set.
These character values are called character literals and are always written
between two single quotes (' ')• F°r example, 'A', ‘_’ ' 3 ' and so on.

An object with type severity can take one of four values ; note, warning, error or
failure. This type is typically used in assertion statements.

Examples :

type Bit is (’0’, 1’);

type Switch_level is (’0’, ‘1’, ‘x’);

Examples of enumerated type object declaration :

Port (Il : in bit;

O1 : out Boolean);

Physical type

• Values of a physical type represent measurements of some quantity. Any value

of a physical type is an integral multiple of the base unit of measurement for
that type. For example, time (e.g. second, millisecond, microsecond, etc.) and
voltage (e.g., volt, millivolt, microvolt, etc.)

• A physical type definition defines both a type and a subtype of that type. Each
unit declaration (either the base unit declaration or a secondary unit declaration)
defines a unit name. Unit name declared in secondary unit declaration must be
directly or indirectly defined in terms of integral multiples of the base unit of
the type declaration in which they appear.

Examples :

type time is range -1E18 to 1E18

units

fs; - femtosecond

ps = 1000 fs; - picosecond

ns = 1000 ps; - nanosecond

us = 1000 ns; - microsecond

ms = 1000 us; - millisecond

sec = 1000 ms; - second

min = 60 sec; - minute

end units;

type distance is range 0 to IE 16

units
- base unit:

A; - angstrom

- metric lengths;

nm = 10 A; - nanometer

um = 1000 nm; - micrometer (or micron)

mm = 1000 um; - millimeter

cm = 10 mm; - centimeter

m = 1000 mm; - meter

km = 1000 m; - kilometer

- - English lengths :

mil = 254000 A; - mil

inch = 1000 mil; - inch

ft = 12 inch; - foot

yd = 3 ft; - yard

fm = 6 ft; - fathom

mi = 5280 ft;- mile

lg = 3 mi; - league

end units;

x : distance; y : time; z : integer;

x := 5A + 13 ft - 27 inch; - arithmetic operations

y : = 3ns + 5 min; - on physical data type

z : = ns/ps;

x : = z mi;
y : = y/10;

• The arithmetic operations are predefined for all physical types. It is an error if
the execution of such an operation cannot deliver the correct result (that is, if
the value corresponding to the mathematical result is not a value of the physical
type).

User-defined types

The user can define a type by using the predefined word type.

Example :

type Multi_level_logic is (low, high, rising, falling);

type arith_op is (add, sub, mul, div);

Here, multi_level_logic and arith_op are the user defined types. The variables
declared using such data types can take values mentioned in the data type
definition. For example,

Variable operation : arithop := sub;

Variable level : Multi_level_logic := high;

2. Composite Types
• Composite types are used to define collection of values. These include both
arrays of values (collection of values of a single type) and records of values
(collection of values of the same or different types).

• An object of a composite type represents a collection of objects, one for each

element of the composite object. A composite type may only contain elements
that are of scalar, composite, or access types; elements of file types are not
allowed in a composite type. Thus, an object of a composite type ultimately
represents a collection of objects of scalar or access types, one for each non-
composite subelement of the composite object.

Array types
• An array object is a composite object consisting of elements that have the
same subtype. The name for an element of an array uses one or more index
values belonging to specified discrete types. The value of an array object is a
composite value consisting of the values of its elements.

• An array object is characterized by the number of indices (the dimensionality

of the array), the type, position and range of each index and the type and
possible constraints of the elements. The order of the indices is significant.

• A one-dimensional array has a distinct element for each possible index value.
A multidimensional array has a distinct element for each possible sequence of
index values that can be formed by selecting one value for each index (in the
given order). The possible values for a given index are all the values that belong
to the corresponding range; this range of values is called the index range.

Example :

type num is integer ;

type numarr is array (7 downto 0) of num;

-- numarr is an array of 8 integer numbers

type my_word is array (0 to 31) of BIT;

-- a memory word type with an ascending

range

type datain is array (7 downto 0) of five_level_logic;

-- an input port type with a descending

range

-- Example of unconstrained array

declarations

type memory is array (integer range o) of myword;

-- a memory array type

- Examples of array object declarations

signal dataline : datain ;

-- defines a data input line

variable mymemory : memory (0 to 2**n-1);

-- defines a memory of 2n 32-bit words

string and bit_vector are the predefined array types, which are defined in
package std.

The values of the predefined type string are one-dimensional arrays of the
predefined type character, indexed by values of the predefined subtype positive;

subtype positive is integer range 1 to integerhigh;

type string is array (positive range o) of character;

The values of the predefined type bit_vector are one-dimensional arrays of the
predefined type BIT, indexed by values of the predefined subtype natural :

subtype natural is integer range 0 to integerhigh;

type bit_vector is array (natural range <>) of bit;

- Examples of string and bit-vector object declaration

variable message : string (1 to 17) := "This is a message";

signal low_bite : bitvector (0 to 7);

Record type

• A record type is a composite type, objects of which consist of named elements.

The value of a record object is a composite value consisting of the values of its
elements. The record type is analogous to the record datatype in pascal and the
struct declaration in C.

• A record type definition creates a record types; it consists of the element

declarations, in the order in which they appear in the type definition.

Example :

type DATE is
record

DAY : INTEGER range 1 to 31 ;

MONTH : MONTH_NAME;

YEAR : INTEGER range 0 to 4000;

end record;

3. Access Types
• Values belonging to an access type are pointers to a dynamically allocated
object of some other type. These are similar to pointers in pascal or C
languages.

Example :

type ptr is access date;

- ptr is an access type whose values are

- addresses that point to object of type date.

4. File Type
• File types are used to define objects representing files in the host system
environment. The value of a file object is the sequence of values contained in
the host system file.

type_file_type_name is file of type_name;

• The type mark in a file type definition defines the subtype of the values
contained in the file. The type mark may denote either a constrained or an
unconstrained subtype. The base type of this subtype must not be a file type or
an access type. If the base type is a composite type, it must not contain a
subelement of an access type. If the base type is an array type, it must be a one-
dimensional array type.
Examples :

file of string - Defines a file type that can contain

- an indefinite number of strings

file of natural - Defines a file type that can contain

- only non-negative integer values

• Three operations are provided for objects of a file type. Given the following
file type declaration :

type FT is file of TM :

• Where type mark TM denotes a scalar type, a record type, or a constrained

array subtype, the following operations are implicitly declared immediately
following the file type declaration :

procedure read (F : in FT; value : out TM);

procedure write (F : out FT; value: in TM);

function endfile (F: in FT) return boolean;

• Procedure read retrieves the next value from a file. Procedure write appends a
value to a file. Function endfile returns False if a subsequent read operation on
an input file can retrieve another value from the file; otherwise it returns true.
Function endfile always returns true for an output file.

5. Other Types
• There are several other types provided by external library, IEEE. This library
contains a std_logic_1164 package which supports more types. Let us discuss
them.

Std_logic type

• std_logic is a data type defined by IEEE standard 1164, and defined in the file
ieee.vhd.std_logic is an enumerated type. This logic has nine values as listed in
Table. 10.6.1.
• The std_logic data type is very important for both simulation and synthesis.
Std_logic includes values that allow us to accurately simulate such circuit
conditions as unknowns and high-impedance stages. For synthesis purposes, the
high-impedance and don't care values provide a convenient and easily
recognizable way to represent three-state enables and don't care logic. For
synthesis, only the values 0, 1, z and have meaning and are supported.

std_logic_vector type

The type stdjogic_vector represents an array of bits whose type is stdjogic.

Example :

Port (I : in stdjogic_vector (7 downto 0);

O : out bit);

In the above example, port I is declared as type std_logic_vector which has 8-

bits.

Signed
The type signed is a numeric type. It is declared in the external package
numeric_std and represents signed integer data in the form of an array. The left
most bit of objects of signed type represents sign and such objects are
represented in 2's complement form, let us see the object definition.

variable difference : signed (4 downto 0) := 10011;

In the above definition, the variable difference is declared as signed type and
has 5-bits with initial value 10011, or - 13.

Unsigned

The type unsigned represents integer data in the form of an array of stdjogic and
it is declared in the external package numeric_std. Let us see the object
definition variable num: unsigned (4 downto 0) := 10011; In the above
definition, the variable num is declared as unsigned type and has 5-bits with
initial value 10011, or 19.

6. Operation in VHDL
VHDL includes the following kinds of operators :

• Logical

• Relational

• Arithmetic

• Shift and Rotate

a. Logical Operators

Logical operators, when combined with signals and/or variables, are used to
create combinational logic. VHDL provides the logical operators as shown in
the Table 10.6.2.
• These operators are defined for the types bit, std_logic and Boolean, and for
one-dimensional arrays of these types (for example, an array of type bit_vector
or std_logic_vector).

• The effects of the logical operators are defined in the following tables. The
symbol T represents TRUE for type BOOLEAN, T for type BIT; the symbol F
represents FALSE for type BOOLEAN, 'O' for type BIT.
b. Relational Operators

• Relational operators are used to create equality or magnitude comparison

functions. VHDL provides the relational operators as shown in the Table 10.6.3.
• The following statement demonstrates the use of some of the above relational
operators :

if (A/=B) then ...

A is compared to B. If A is equal to B, then the value of the expression (A/= B)

is false (0); otherwise it is true (1).

if (A > B) then

Structure of Behavioral Description

AU : Dec.-l0, 18, May-16, 17
1. Entity Declaration
• An entity declaration describes the external interface of the entity. It specifies
the name of the entity, the names of input/output ports, and the type of ports.
The syntax for an entity declaration is as shown below.

entity entity_name is

generic (list of generics and their types);

Port (list of port names and their types

entity item declarations

begin

entity statements

end entity_name;

The port in the behavioral modeling can have one of the following modes :

in : This mode is used for a signal that is an input to an entity (value is read not
written).

out: It is used for a signal that is an output from an entity. The value of such a
signal can not be read inside the entity's architecture. But it can be read by other
entities those use it.

inout: It is used for a signal that is both, an input to an entity and an output
from the entity.

buffer : The signal is an output from the entity and its value can also be read
inside the architecture of entity. The buffer is different from inout mode in that
it cannot have more than one source.

Linkage : The value of a linkage port can be read and updated. This can be
done only by another port of mode linkage.

• The entity item declaration includes those declarations that are common to all
the design unit. The Fig. 10.7.1 shows the circuit for half-adder and its entity
declaration is
entity half_adder is

port ( A : in bit;

B : in bit;

Sum : out bit;

Cout : out bit);

end half_adder;

2. Architecture Body
• Architecture specifies behavior, functionality, interconnections or relationship
between inputs and outputs. It is the actual description of the design.

• The syntax of an architecture body is :

architecture architecture_name of entity_name is

architecture item declarations

begin

Concurrent statements ; these include ->

process statement block statement

concurrent procedure call

statement

concurrent assertion statement

concurrent signal assignment

statement

component instantiation statement generate statement

end architecture_name;

• All concurrent statements execute in parallel and therefore their sequence in

the architecture body does not matter the behavior of the circuit. The
architecture body for half_adder is :

architecture adder of half_adder is

begin

process (A, B)

begin

Sum < = A xor B ;

Cout < = A and B ;

end process;

end adder;

3. Variable Assignment Statement

• We can use variables inside the processes. This is illustrated by the following
statements :

process (X)

variable A, B : bit; - variable declaration statement

begin

st l : A : =X; - Variable assignment statement

st2 : B := not A; - Variable assignment statement

st3 : O1 < = A; - use < = assignment operator

end process ;

• Variable assignment statements, as in C language, are calculated and assigned

immediately with no delay time between calculation and assignment. The
assignment operator : = is used assigned values to the variables instead of
assignment operator <=.

• One important thing to note that we can label any statement in the VHDL such
as stl, st2 and st3 in the previous description.

4. Sequential Statements
• The various forms of sequential statements are associated with behavioral
description. These statements have to appear inside process in VHDL. These
statements execute in the order in which they appear. Let us study these
sequential statements.

a. IF Statement

• An IF statement selects a sequence of statements for execution based on the

value of a condition. The condition can be any expression that evaluates to a
Boolean value.

VHDL Syntax :

if (Boolean Expression) then

statement 1;

statement 2;

else
statement x;S

statement y;

end if;

Example :

if (EN = '1') then

Q := S1;

else

Q: = S2;

end if;

In the above examples, if EN = T' (high), then the value of SI is assigned to Q;

otherwise, the value of S2 is assigned to Q.

Ex. 10.7.1 : Execution of IF as a D latch.

if Clk = '1'

then Q:= D;

end if;

if Clk is T (high), then the value of D is assigned to output Q. If Clk is not high,
Q retains its current value, thus simulating a latch.

Ex. 10.7.2 : Execution of IF as ELSE-IF

VHDL syntax :

If (Boolean Expression 1) then

statement 1 ; statement 2; ...

elsif (Boolean Expression 2) then

statement x; statement y; ...

else

statement a; statement b; ...

end if ;

Example :

process (a, b, en)

begin

if en = '00' then

c < = a;

elsif en = '01' then

c < = b;

else

c < = '0';

end if;

end process;

Structure of Data Flow Description

• The listing 10.8.1 shows the HDL code for the circuit shown in the Fig. 10.8.1.
The circuit is an AND-OR circuit in which signals A, B, C, D and E are input
signals, signal Y is an output signal and signals II and 12 are intermediate
signals.
Listing 10.8.1 : VHDL code for AND-OR circuit

Subprograms
• A subprogram defines a sequential algorithm that performs particular task.
Two types of subprograms are used in VHDL : Procedures and functions.
Procedures and functions in VHDL, are directly analogous to functions and
procedures in a high-level programming language such as C or Pascal.

• They provide the ability to execute common routines from several different
places in a description. They also provide a means of breaking up large
programs into smaller ones to make it easier to read and debug the source
descriptions.

• Function : Function performs sequential computations and return a value as a

the value of the function.

1. Must have at least one input argument.

2. Computes and returns a single value.

3. Executes in zero simulation time.

4. Always terminated by return statement.

5. Can be called only from within process.

• Procedure : Procedure performs sequential computations and return values in

global objects or by storing values into formal parameters.

1. May be used to partition large behavioral descriptions.

2. May return zero or more values.

3. May or may not execute in zero simulation time, depending on whether it has
a wait statement or not.

4. Can be called only from within process.

5. Can have more than one input and output.

• Subprograms written in VHDL must have body and may have declaration. The
typical format for a subprogram body is :

subprogram-specification is subprogram-item-declarations begin

Subprogram statements

end [function / procedure] [subprogram_name[;

• Subprogram specification gives name of subprogram and it defines the formal

parameters, their class (i.e., signal, variable, file or constant), their type, and
their mode (in, out or inout).

• When parameters are of a variable or constant class, values are passed to the
subprogram by value. On the other hand, files and signals are passed by
reference.

VHDL Description of Flip-Flops

AU : Dec.-11, 15, 17, May-15

1. Behavioral Description of D Flip-Flop using IF-THEN

Statements
• Consider a positive edge-triggered D flip-flop. We know that the D flip-flop is
similar to D-latch except 'clock pulse' is used instead of enable input. So VHDL
code for D flip-flop is same as that of D-latch with two exceptions.

• i) The Clk signal is the only signal that can cause a change in the Q output. So
only Clk signal is to be given in the process sensitivity list.

• ii) Positive edge triggering is required at the Clk input.

• In VHDL, 'attribute' refers to a property of an object, such as a signal. For D
flip-flop, two conditions are required at the Clk input. First is, change in the Clk
signal and second is, Clk should be equal to one. We are using 'EVENT
attribute to indicate any change in the Clk signal and Clock = 1 condition. Thus,
positive edge triggering condition can be obtained by logically ANDing
Clock'EVENT condition with the condition, Clock = 1.

• The VHDL code for a positive-edge-triggered D flip-flop is given below.

LIBRARY IEEE;

USE IEEE. std_logic_1164.all;

ENTITY DFF IS

PORT (D, Clock : IN STD_LOGIC;

Q : OUT STD_LOGIC);

END DFF;

ARCHITECTURE Behavior OF DFF IS

BEGIN

PROCESS (Clock)

BEGIN

IF ClockEVENT AND Clock = ‘1’

Q < = D;

END IF;

END PROCESS;

END Behavior;