LMR33620

SNVSAW1E – FEBRUARY 2018 – REVISED NOVEMBER 2020

LMR33620 SIMPLE SWITCHER® 3.8-V to 36-V, 2-A

Synchronous Step-down Voltage Converter
1 Features 3 Description
• Functional Safety-Capable The LMR33620 SIMPLE SWITCHER® regulator is
– Documentation available to aid functional safety an easy-to-use, synchronous, step-down DC/DC
system design converter that delivers best-in-class efficiency for
• Configured for rugged industrial applications rugged industrial applications. The LMR33620 drives
– Input voltage range: 3.8 V to 36 V up to 2 A of load current from an input of up
– Output voltage range: 1 V to 24 V to 36 V. The LMR33620 provides high light load
– Output current: 2 A efficiency and output accuracy in a very small
– Peak-current-mode control solution size. Features such as a power-good flag
– Short minimum on-time of 68 ns and precision enable provide both flexible and easy-
– Frequency: 400 kHz, 1.4 MHz, 2.1 MHz to-use solutions for a wide range of applications.
– Junction temperature range –40°C to +125°C The LMR33620 automatically folds back frequency at
– Low EMI and low switching noise light load to improve efficiency. Integration eliminates
– Integrated compensation network most external components and provides a pinout
• Low EMI and switching noise designed for simple PCB layout. Protection features
– HotRod™ package include thermal shutdown, input undervoltage lockout,
– Parallel input current paths cycle-by-cycle current limit, and hiccup short-circuit
• High power conversion at all loads protection. The LMR33620 is available in an 8-pin
HSOIC package and in a 12-pin 3 mm × 2 mm
– Peak efficiency > 95%
next generation VQFN package with wettable flanks.
– Low operating quiescent current of 25 µA
This device is also available in an AEC-Q100-qualified
• Flexible system interface
version.
– Power-good flag and precision enable
• Use TPSM53602 module for faster time to market Device Information
• Create a custom design using the LMR33620 with PART NUMBER PACKAGE(1) BODY SIZE (NOM)
the WEBENCH® Power Designer LMR33620 HSOIC (8) 5.00 mm × 4.00 mm
LMR33620 VQFN (12) 3.00 mm × 2.00 mm
2 Applications
(1) For all available packages, see the orderable addendum at
• Motor drive systems: drones, AC inverters,
the end of the data sheet.
VF drives, servos
• Factory and building automation systems:
PLC CPU, HVAC control, elevator control
• General purpose wide VIN powers
100
BOOT
VIN VIN 95
CBOOT
90
CIN EN SW VOUT
L1 85
Efficiency (%)

COUT
PGND 80

75
8V
VCC PG 70
12V
RFBT 65
CVCC
24V
FB 60
RFBB 36V
AGND 55
0.01 0.1 1 10
Output Current (A) C024

Efficiency versus Output Current VOUT = 5 V, 400

Simplified Schematic kHz, VQFN

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.4 Device Functional Modes..........................................14
2 Applications..................................................................... 1 9 Application and Implementation.................................. 18
3 Description.......................................................................1 9.1 Application Information............................................. 18
4 Revision History.............................................................. 2 9.2 Typical Application.................................................... 18
5 Device Comparison Table...............................................3 9.3 What to Do and What Not to Do............................... 30
6 Pin Configuration and Functions...................................4 10 Layout...........................................................................32
7 Specifications.................................................................. 5 10.1 Layout Guidelines................................................... 32
7.1 Absolute Maximum Ratings........................................ 5 10.2 Layout Example...................................................... 34
7.2 ESD Ratings............................................................... 5 11 Device and Documentation Support..........................36
7.3 Recommended Operating Conditions.........................5 11.1 Device Support........................................................36
7.4 Thermal Information....................................................6 11.2 Documentation Support.......................................... 36
7.5 Electrical Characteristics.............................................6 11.3 Receiving Notification of Documentation Updates.. 36
7.6 Timing Characteristics.................................................7 11.4 Support Resources................................................. 36
7.7 System Characteristics............................................... 8 11.5 Trademarks............................................................. 37
7.8 Typical Characteristics................................................ 9 11.6 Electrostatic Discharge Caution.............................. 37
8 Detailed Description......................................................10 11.7 Glossary.................................................................. 37
8.1 Overview................................................................... 10 12 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram......................................... 10 Information.................................................................... 38
8.3 Feature Description...................................................11 12.1 Tape and Reel Information......................................38

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2020) to Revision E (November 2020) Page
• Added functional safety bullet to the Features .................................................................................................. 1
• Updated the numbering format for tables, figures and cross-references throughout the document. ................ 1
• Added VQFN package drawing........................................................................................................................ 34

Changes from Revision C (March 2019) to Revision D (May 2020) Page

• Added link to TPSM53602 product page ...........................................................................................................1
• Changed heading to device option .................................................................................................................... 3

Changes from Revision B (June 2018) to Revision C (March 2019) Page

• Changed heading to device option .................................................................................................................... 3
• Changed Minimum peak current to reflect ATE data.......................................................................................... 6
• Changed zero cross current to reflect ATE data.................................................................................................6
• Changed to new current limit equation............................................................................................................. 13
• Added new de-rate curve .................................................................................................................................23

Changes from Revision A (April 2018) to Revision B (June 2018) Page

• Changed block diagram to fix drawing error..................................................................................................... 10
• Added graphs for Typical Switching Frequency in Dropout Mode ................................................................... 16

Changes from Revision * (February 2018) to Revision A (April 2018) Page

• Added WSON information throughout data sheet ............................................................................................. 1

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5 Device Comparison Table

DEVICE OPTION PACKAGE FREQUENCY RATED CURRENT OUTPUT VOLTAGE
LMR33620ADDA 400 kHz 2A
DDA (8-pin HSOIC)
LMR33620BDDA 1400 kHz 2A Adjustable
5 × 4 mm
LMR33620CDDA 2100 kHz 2A
LMR33620ARNX 400 kHz 2A
RNX (12-pin VQFN)
LMR33620BRNX 1400 kHz 2A Adjustable
3 × 2 × 0.85 mm
LMR33620CRNX 2100 kHz 2A

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6 Pin Configuration and Functions

SW

12

PGND 1 8 SW PGND 1 11 PGND

VIN 2 7 BOOT
THERMAL PAD VIN 10 VIN
2
EN 3 6 VCC

NC 3 9 EN
PG 4 5 FB

BOOT 4 8 PG

Not to scale 5 6 7
Figure 6-1. DDA Package 8-Pin HSOIC With VCC AGND FB
PowerPAD™ Top View Figure 6-2. RNX Package 12-Pin VQFN Top View

Table 6-1. Pin Functions

PIN
TYPE DESCRIPTION
HSOIC VQFN NAME
Power ground terminal. Connect to system ground and AGND. Connect to bypass
1 1,11 PGND G
capacitor with short wide traces.
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors
2 2,10 VIN P
directly to this pin and PGND.
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN;
3 9 EN A
Do not float.
Open drain power-good flag output. Connect to suitable voltage supply through a
4 8 PG A current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN =
Low. Can be left open when not used.
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not
5 7 FB A
float. Do not ground.
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect
6 5 VCC P to external loads. Can be used as logic supply for power-good flag. Connect a high-
quality 1-µF capacitor from this pin to GND.
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF
capacitor from this pin to the SW pin. On the VQFN package connect the SW pin to
7 4 BOOT P
NC on the PCB. This simplifies the connection from the CBOOT capacitor to the SW
pin.
Regulator switch node. Connect to power inductor. On the VQFN package connect
8 12 SW P the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin.
Analog ground for regulator and system. Ground reference for internal references
and logic. All electrical parameters are measured with respect to this pin. Connect
THERMAL to system ground on PCB. For the HSOIC package, the pad on the bottom of the
6 AGND G
PAD device serves as both the AGND connection and a thermal connection to the heat
sink ground plane. This pad must be soldered to a ground plane to achieve good
electrical and thermal performance.
On the VQFN package the SW pin must be connected to NC on the PCB. This
— 3 NC — simplifies the connection from the CBOOT capacitor to the SW pin. This pin has no
internal connection to the regulator.
A = Analog, P = Power, G = Ground

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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
PARAMETER MIN MAX UNIT
VIN to PGND –0.3 38
EN to AGND(2) –0.3 VIN + 0.3
FB to AGND –0.3 5.5 V
PG to AGND(2) 0 22
Voltages AGND to PGND –0.3 0.3
SW to PGND –0.3 VIN + 0.3
SW to PGND less than 100-ns transients –3.5 38
V
BOOT to SW –0.3 5.5
VCC to AGND(4) –0.3 5.5
TJ Junction temperature(3) –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V
(3) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
(4) Under some operating conditions the VCC LDO voltage may increase beyond 5.5V.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM) (1)
±2500
V(ESD) Electrostatic discharge V
Charged-device model (CDM) (2)
±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating temperature range of –40 °C to 125 °C (unless otherwise noted) (1)
MIN MAX UNIT
VIN to PGND 3.8 36
Input voltage EN (2) 0 VIN V
PG(2) 0 18
Adjustable output voltage VOUT (3) 1 24 V
Output current IOUT 0 2 A

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Section 7.5.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
(3) The maximum output voltage can be extended to 95% of VIN; contact TI for details. Under no conditions should the output voltage be
allowed to fall below zero volts.

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7.4 Thermal Information

The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For design information see Maximum Ambient Temperature
section.
LMR336x0
THERMAL METRIC(1) (2) DDA (HSOIC) RNX (VQFN) UNIT
8 PINS 12 PINS
RθJA Junction-to-ambient thermal resistance 42.9(2) 72.5(2) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54 35.9 °C/W
RθJB Junction-to-board thermal resistance 13.6 23.3 °C/W
ψJT Junction-to-top characterization parameter 4.3 0.8 °C/W
ψJB Junction-to-board characterization parameter 13.8 23.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.3 N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes.
These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For design information see Maximum Ambient Temperature section.

7.5 Electrical Characteristics

Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
Minimum operating input
VIN 3.8 V
voltage
Non-switching input current;
IQ VFB = 1.2 V 24 34 µA
measured at VIN pin (2)
Shutdown quiescent current;
ISD EN = 0 5 10 µA
measured at VIN pin
ENABLE
EN input level required to turn
VEN-VCC-H Rising threshold 1 V
on internal LDO
EN input level required to turn
VEN-VCC-L Falling threshold 0.3 V
off internal LDO
EN input level required to start
VEN-H Rising threshold 1.2 1.231 1.26 V
switching
VEN-HYS Hysteresis below VEN-H Hysteresis below VEN-H; falling 100 mV
ILKG-EN Enable input leakage current VEN = 3.3 V 0.2 nA
INTERNAL SUPPLIES
Internal LDO output voltage
VCC 6 V ≤ VIN ≤ 36 V 4.75 5 5.25 V
appearing at the VCC pin
Bootstrap voltage
VBOOT-UVLO undervoltage lock-out 2.2 V
threshold(3)
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage; ADJ option 0.985 1 1.015 V
Current into FB pin; ADJ
IFB FB = 1 V 0.2 50 nA
option
CURRENT LIMITS(4)
ISC High-side current limit LMR33620 2.9 3.5 4 A
ILIMIT Low-side current limit LMR33620 1.95 2.45 2.9 A

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Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPEAK-MIN Minimum peak inductor current LMR33620 0.54 A
IZC Zero current detector threshold -0.106 A
SOFT START
tSS Internal soft-start time 2.9 4 6 ms
POWER GOOD (PG PIN)
Power-good upper threshold -
VPG-HIGH-UP % of FB voltage 105% 107% 110%
rising
Power-good upper threshold -
VPG-HIGH-DN % of FB voltage 103% 105% 108%
falling
Power-good lower threshold -
VPG-LOW-UP % of FB voltage 92% 94% 97%
rising
Power-good lower threshold -
VPG-LOW-DN % of FB voltage 90% 92% 95%
falling
Power-good glitch filter
tPG 60 170 µs
delay(1)
VIN = 12 V, VEN = 4 V 76 150
RPG Power-good flag RDSON Ω
VEN = 0 V 35 60
Minimum input voltage for
VIN-PG 50-µA, EN = 0 V 2 V
proper PG function
VPG PG logic low output 50-µA, EN = 0 V, VIN = 2V 0.2 V
OSCILLATOR
ƒSW Switching frequency "A" Version 340 400 460 kHz
ƒSW Switching frequency "B" Version 1.2 1.4 1.6 MHz
ƒSW Switching frequency "C" Version, DDA package 1.8 2.1 2.4 MHz
ƒSW Switching frequency "C" Version, RNX package 1.8 2.1 2.3 MHz
MOSFETS
High-side MOSFET ON-
RDS-ON-HS RNX package 75 145 mΩ
resistance
High-side MOSFET ON-
RDS-ON-HS DDA package 95 160 mΩ
resistance
Low-side MOSFET ON-
RDS-ON-LS RNX package 50 95 mΩ
resistance
Low-side MOSFET ON-
RDS-ON-LS DDA package 66 110 mΩ
resistance

(1) See Power-Good Flag Output for details.

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge CBOOT.
(4) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.

7.6 Timing Characteristics

Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
MIN NOM MAX UNIT
tON-MIN Minimum switch on-time RNX package 68 80 ns
tON-MIN Minimum switch on-time DDA package 75 108 ns
tOFF-MIN Minimum switch off-time RNX package 52 70 ns
tOFF-MIN Minimum switch off-time DDA package 50 85 ns
tON-MAX Maximum switch on-time 7 9 µs

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7.7 System Characteristics

The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to
the case of typical components over the temperature range of TJ = –40°C to 125°C. These specifications are not ensured by
production testing.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Operating input voltage range VOUT = 3.3 V, IOUT= 0 A 3.8 36 V
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to
–1.5% 2.5%
Output voltage regulation for VOUT = 5 max. load
V(1) VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to
–1.5% 1.5%
max. load
VOUT
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A
–1.5% 2.5%
Output voltage regulation for VOUT = 3.3 to max. load
V(1) VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A
–1.5% 1.5%
to max. load
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A,
ISUPPLY Input supply current when in regulation 25 µA
RFBT = 1 MΩ
VOUT = 5 V, IOUT = 1A
VDROP Dropout voltage; (VIN – VOUT) Dropout at –1% of regulation, 150 mV
ƒSW = 140 kHz
DMAX Maximum switch duty cycle(2) VIN = VOUT = 12 V, IOUT = 1 A 98%
FB pin voltage required to trip short-circuit
VHC 0.4 V
hiccup mode
tHC Time between current-limit hiccup burst 94 ms
tD Switch voltage dead time 2 ns
Shutdown temperature 165 °C
TSD Thermal shutdown temperature
Recovery temperature 148 °C

(1) Deviation is with respect to VIN =12 V, IOUT = 1 A.

(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: ƒMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).

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7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 12 V

36 12
11
34
10
Quiescent Current (µA)

Shutdown Current (µA)

32 9
8
30
7
28 6
5
26
4
24 -40C 3 -40C
25C 2 25C
22
1
125C 125C
20 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Input Voltage (V) C005 Input Voltage (V) C003

VFB = 1.2 V EN = 0 V

Figure 7-1. Non-Switching Input Supply Current Figure 7-2. Shutdown Supply Current
600 1.35
590
1.30
580
EN Threshold Voltage (V)
Output Current (mA)

570 1.25

560
1.20
550
1.15
540
530 1.10
-40C
520
25C 1.05 UP
510
125C DN
500 1.00
0 5 10 15 20 25 30 35 40 ±40 ±20 0 20 40 60 80 100 120 140
Input Voltage (V) C007 Temperature (C) C006

VOUT = 0 V ƒS = 400 kHz See Figure 9-31

Figure 7-3. Short-Circuit Output Current Figure 7-4. Precision Enable Thresholds
700

650
OUTPUT VOLTAGE (0.8V/Div)

Peak Inductor Current (mA)

600

550

500
-40C
DN UP 450 25C
125C
400
0 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (1V/Div) Input Voltage (V) C008

IOUT = 1 mA See Figure 9-31 IOUT = 0 A VOUT = 5 V See Figure 9-31

ƒSW = 400 kHz
Figure 7-5. UVLO Thresholds
Figure 7-6. IPEAK-MIN

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8 Detailed Description
8.1 Overview
The LMR33620 is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial
applications. Advanced high speed circuitry allows the device to regulate from an input voltage of 20 V, while
providing an output voltage of 3.3 V at a switching frequency of 2.1 MHz. The innovative architecture allows
the device to regulate a 3.3-V output from an input of only 3.8 V. The regulator automatically switches modes
between PFM and PWM depending on load. At heavy loads, the device operates in PWM at a constant
switching frequency. At light loads, the mode changes to PFM with diode emulation allowing DCM. This reduces
the input supply current and keeps efficiency high. The device features internal loop compensation which
reduces design time and requires fewer external components than externally compensated regulators.
The LMR33620 is available in an ultra-miniature VQFN package with wettable flanks. This package features
extremely small parasitic inductance and resistance, enabling very high efficiency while minimizing switch node
ringing and dramatically reducing EMI. The VIN/PGND pin layout is symmetrical on either side of the VQFN
package. This allows the input current magnetic fields to partially cancel, resulting in reduce EMI generation.
8.2 Functional Block Diagram
VCC VIN

INT. REG.
OSCILLATOR
BIAS BOOT
ENABLE
EN LOGIC
HS CURRENT
SENSE

1.0V
Reference
ERROR PWM
AMPLIFIER COMP.
CONTROL
+ LOGIC DRIVER SW
+
-
FB -

LS CURRENT
PG PFM MODE
CONTROL
SENSE

POWER GOOD
CONTROL

AGND PGND

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8.3 Feature Description

8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR33620 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. The timing parameters of the
glitch filter are found in Section 7.5. Output voltage excursions lasting less than tPG do not trip the power-good
flag. Power-good operation can best be understood by reference to Figure 8-1 and Figure 8-2. Note that during
initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time that
the power-good flag goes high. This delay only occurs during start-up and is not encountered during normal
operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT, through a 100-kΩ resistor, as desired. If this function
is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With
EN low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the
power-good flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the
device is enabled and about 65 mA when the device is disabled. The internal current limit protects the device
from any transient currents that can occur when discharging a filter capacitor connected to this output.
VOUT

VPG-HIGH_UP (107%)
VPG-HIGH-DN (105%)

VPG-LOW-UP (95%)

VPG-LOW-DN (93%)

PG

High = Power Good

Low = Fault

Figure 8-1. Static Power-Good Operation

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Glitches do not cause false operation nor reset timer

VOUT

VPG-LOW-UP (95%)
VPG-LOW-DN (93%)

< tPG

PG

tPG tPG tPG

Figure 8-2. Power-Good-Timing Behavior

8.3.2 Enable and Start-up

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see Section 9.2.2.10). Applying a voltage of
≥ VEN-VCC_H causes the device to enter standby mode, powering the internal VCC, but not producing an output
voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter start-up mode and
starting the soft-start period. When the EN input is brought below VEN-H by VEN-HYS, the regulator stops running
and enters standby mode. Further decrease in the EN voltage to below VEN-VCC-L completely shuts down the
device. This behavior is shown in Figure 8-3. The EN input can be connected directly to VIN if this feature is
not needed. This input must not be allowed to float. The values for the various EN thresholds can be found in
Section 7.5 .
The LMR33620 uses a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. A typical start-up waveform is shown in Figure 8-4, indicating typical
timings. The rise time of the output voltage is about 4 ms (see Section 7.5).

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EN

VEN-H
VEN-H ± VEN-HYS

VEN-VCC-H
VEN-VCC-L

VCC

5V

VOUT

VOUT

Figure 8-3. Precision Enable Behavior

EN, 4V/Div

VOUT, 2V/Div

PG, 5V/Div

Inductor Current, 2A/Div 2ms/Div

Figure 8-4. Typical Start-up Behavior VIN = 12 V, VOUT = 5 V, IOUT = 2 A

8.3.3 Current Limit and Short Circuit

The LMR33620 incorporates both peak and valley inductor current limit to provide protection to the device from
overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current
runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum
output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for
sustained short circuits. Finally, a zero current detector is used on the low-side power MOSFET to implement
DEM at light loads (see the Glossary). The typical value of this current limit is found under IZC in Section 7.5 .
When the device is overloaded, the valley of the inductor current may not reach below ILIMIT (see Section
7.5) before the next clock cycle. When this occurs, the valley current limit control skips that cycle, causing
the switching frequency to drop. Further overload causes the switching frequency to continue to drop, and the
inductor ripple current to increase. When the peak of the inductor current reaches the high-side current limit, ISC

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(see Section 7.5), the switch duty cycle is reduced and the output voltage falls out of regulation. This represents
the maximum output current from the converter and is given approximately by Equation 1.

ILIMIT ISC
IOUT max 2 (1)

If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
into hiccup mode. In this mode, the device stops switching for tHC (see Section 7.7), or about 94 ms and then
goes through a normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit
for about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in Figure 8-5 as long as the
short-circuit-condition persists. This mode of operation helps reduce the temperature rise of the device during
a hard short on the output. The output current is greatly reduced during hiccup mode. Once the output short is
removed and the hiccup delay is passed, the output voltage recovers normally as shown in Figure 8-6.

Short Applied Short Removed

VOUT, 2V/Div

Inductor Current, 1A/Div

Inductor Current,
50ms/Div 1A/Div

50ms/Div

Figure 8-5. Inductor Current Burst in Short-Circuit Figure 8-6. Short-Circuit Transient and Recovery
Mode

8.3.4 Undervoltage Lockout and Thermal Shutdown

The LMR33620 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin).
When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start up. When VCC falls
below about 3 V, the device shuts down, regardless of EN status. Because the LDO is in dropout during these
transitions, the above values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 165°C the device shuts down; re-start occurs when the temperature falls to about
148°C.
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM. The load current for which the device moves
from PFM to PWM can be found in Section 9.2.3. The output current at which the device changes modes
depends on the input voltage, inductor value, and the nominal switching frequency. For output currents above
the curve, the device is in PWM mode. For currents below the curve, the device is in PFM. The curves
apply for and the BOMs shown in Table 9-3 and Table 9-4 and a nominal switching frequency of 400 kHz.
At higher switching frequencies, the load at which the mode change occurs is greater. For applications where
the switching frequency must be known for a given condition, the transition between PFM and PWM must be
carefully tested before the design is finalized.

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In PWM mode, the regulator operates as a constant frequency converter using PWM to regulate the output
voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and
modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and
low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.
The duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The periodicity
of these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency
(see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current
required to regulate the output voltage at light loads. PFM results in very good light-load efficiency, but also
yields larger output voltage ripple and variable switching frequency. Also, a small increase in output voltage
occurs at light loads. The actual switching frequency and output voltage ripple depends on the input voltage,
output voltage, and load. Typical switching waveforms in PFM and PWM are shown in Figure 8-7 and Figure 8-8.
See Section 9.2.3 for output voltage variation with load in auto mode.

SW, SW,
5V/Div 5V/Div

VOUT,
10mV/Div
VOUT,
10mV/Div

Inductor
Inductor Current,
Current, 1A/Div
0.5A/Div

2µs/Div

50µs/Div

Figure 8-7. Typical PFM Switching Waveforms VIN = Figure 8-8. Typical PWM Switching Waveforms VIN
12 V, VOUT = 5 V, IOUT = 10 mA = 12 V, VOUT = 5 V, IOUT = 2 A, ƒS = 400 kHz

8.4.2 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor and the maximum duty cycle that the controller can achieve. As the input voltage level
approaches the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value (see
Section 7.6). Beyond this point, the switching can become erratic, and the output voltage falls out of regulation.
To avoid this problem, the LMR33620 automatically reduces the switching frequency to increase the effective
duty cycle and maintain regulation. In this data sheet, the dropout voltage is defined as the difference between
the input and output voltage when the output has dropped by 1% of its nominal value. Under this condition,
the switching frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit
detection threshold is not activated when in dropout mode. Typical dropout characteristics can be found in Figure
8-9, Figure 8-10, Figure 8-11, and Figure 8-12.

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6 0.3

5.5 0.25

Drop-out Voltage (V)

Output Voltage (V)

5 0.2

4.5 0.15

4 0.1
0A
3.5 0.05 3.3V
1A
5V
2A 0
3
0 0.5 1 1.5 2 2.5
4 4.5 5 5.5 6 6.5 7
Output Current (A) C001
Input Voltage (V) C002

Figure 8-9. Overall Dropout Characteristic VOUT = 5 Figure 8-10. Typical Dropout Voltage versus
V Output Current in Frequency Foldback ƒSW = 140
kHz
2.4 2.4
2.2 2.2
2 2
Switching Frequency (MHz)

Switching Frequency (MHz)

1.8 1.8
1.6 1.6
1.4 1.4
1.2 1.2
1 1
0.8 0.8
0.6 0.6
0.4 1A 0.4 1A
0.2 0.2
2A 2A
0 0
3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
Input Voltage (V) C029 Input Voltage (V) C028

Figure 8-11. Typical Switching Frequency in Figure 8-12. Typical Switching Frequency in
Dropout Mode VOUT = 3.3 V, fSW = 2.1 MHz Dropout Mode VOUT = 5 V, fSW = 2.1 MHz

8.4.3 Minimum Switch On-Time

Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking
times associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR33620 automatically reduces the switching frequency when the
minimum on-time limit is reached. This way the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before
frequency foldback occurs is found in Equation 2. The values of tON and fSW can be found in Section 7.5. As
the input voltage is increased, the switch on-time (duty-cycle) reduces to regulate the output voltage. When the
on-time reaches the limit, the switching frequency drops, while the on-time remains fixed. This relationship is
highlighted in Figure 8-13 for a nominal switching frequency of 2.1 MHz.

VOUT
VIN d
t ON ˜ fSW (2)

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2.6

2.4

Switching Frequency (MHz)

2.2

1.8

1.6

1.4
1A
1.2
2A
1
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
Input Voltage (V) C027

Figure 8-13. Switching Frequency versus Input Voltage VOUT = 3.3 V

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

The LMR33620 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LMR33620. Alternately, the WEBENCH Design Tool can be used to generate a complete
design. This tool utilizes an iterative design procedure and has access to a comprehensive database of
components. This allows the tool to create an optimized design and allows the user to experiment with various
options.

Note
In this data sheet, the effective value of capacitance is defined as the actual capacitance under
D.C. bias and temperature; not the rated or nameplate values. Use high-quality, low-ESR, ceramic
capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a
large voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias
the capacitance drops considerably. Large case sizes and/or higher voltage ratings are better in this
regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum
effective capacitance up to the required value. This can also ease the RMS current requirements on
a single capacitor. A careful study of bias and temperature variation of any capacitor bank should be
made in order to ensure that the minimum value of effective capacitance is provided.

9.2 Typical Application

Figure 9-1 shows a typical application circuit for the LMR33620. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick start guide, Figure 9-1 provides typical
component values for a range of the most common output voltages. The values given in the table are typical.
Other values can be used to enhance certain performance criterion as required by the application. Note that for
the VQFN package, the input capacitors are split and placed on either side of the package; see Section 9.2.2.6
for more details.

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L
VOUT
VIN VIN SW
6 V to 36 V 10 µH 5V
CIN
CHF CBOOT 2A
10 µF
220 nF BOOT COUT
EN
0.1 µF 4x 22 µF
RFBT
PG CFF
100 NŸ
PG
100 NŸ VCC FB
CVCC
1 µF PGND AGND
RFBB
24.9 NŸ

Figure 9-1. Example Application Circuit (400 kHz)

9.2.1 Design Requirements

Table 9-1 provides the parameters for our detailed design procedure example:
Table 9-1. Detailed Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage 12 V (6 V to 36 V)
Output voltage 5V
Maximum output current 0 A to 2 A
Switching frequency 400 kHz

Table 9-2. Typical External Component Values

COUT (RATED
ƒSW
VOUT (V) L (µH) CAPACITANC RFBT (Ω) RFBB (Ω) CIN + CHF CBOOT CVCC CFF
(kHz)
E)
400 3.3 10 4 × 22 µF 100 k 43.2 k 10 µF + 220 nF 100 nF 1 µF open
1400 3.3 2.2 2 × 22 µF 100 k 43.2 k 10 µF + 220 nF 100 nF 1 µF open
2100 3.3 1.2 2 × 22 µF 100 k 43.2 k 10 µF + 220 nF 100 nF 1 µF open
400 5 10 4 × 22 µF 100 k 24.9 k 10 µF + 220 nF 100 nF 1 µF open
1400 5 2.2 2 × 22 µF 100 k 24.9 k 10 µF + 220 nF 100 nF 1 µF open
2100 5 1.5 2 × 22 µF 100 k 24.9 k 10 µF + 220 nF 100 nF 1 µF open
400 12 27 4 × 22 µF 100 k 9.09 k 10 µF + 220 nF 100 nF 1 µF open
1400 12 4.7 4 × 10 µF 100 k 9.09 k 10 µF + 220 nF 100 nF 1 µF open
2100 12 3.3 4 × 10 µF 100 k 9.09 k 10 µF + 220 nF 100 nF 1 µF open

9.2.2 Detailed Design Procedure

The following design procedure applies to Figure 9-1 and Table 9-1.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR33620 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example, 400 kHz was chosen.
9.2.2.3 Setting the Output Voltage
The output voltage of the LMR33620is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in Section 7.3. The divider network is comprised of RFBT and RFBB, and
closes the loop between the output voltage and the converter. The converter regulates the output voltage by
holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the divider
is a compromise between excessive noise pick-up and excessive loading of the output. Smaller values of
resistance reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for RFBT is
100 kΩ; with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a feedforward capacitor must be
used across this resistor to provide adequate loop phase margin (see Section 9.2.2.9). Once RFBT is selected,
Equation 3 is used to select RFBB. VREF is nominally 1 V (see Section 7.5 for limits).

RFBT
RFBB
ª VOUT º
« 1»
¬ VREF ¼ (3)

For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ are chosen.
9.2.2.4 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based
on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of
the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, the maximum device current should be used. Equation 4 can
be used to determine the value of inductance. The constant K is the percentage of inductor current ripple. For
this example, K = 0.3 was chosen and an inductance was found; the next standard value of 10 µH was selected.

VIN VOUT V
L ˜ OUT
fSW ˜ K ˜ IOUT max VIN (4)

Ideally, the saturation current rating of the inductor must be at least as large as the high-side switch current
limit, ISC (see Section 7.5). This ensures that the inductor does not saturate even during a short circuit on
the output. When the inductor core material saturates, the inductance falls to a very low value, causing the
inductor current to rise very rapidly. Although the valley current limit, ILIMIT, is designed to reduce the risk of
current run-away, a saturated inductor can cause the current to rise to high values very rapidly. This can lead
to component damage; do not allow the inductor to saturate. Inductors with a ferrite core material have very
hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores
exhibit a soft saturation, allowing for some relaxation in the current rating of the inductor. However, they have

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more core losses at frequencies typically above 1 MHz. In any case, the inductor saturation current must not
be less than the device low-side current limit, ILIMIT (see Section 7.5). The maximum inductance is limited by
the minimum current ripple required for the current mode control to perform correctly. As a rule-of-thumb, the
minimum inductor ripple current must be no less than about 10% of the device maximum rated current under
nominal conditions.

VOUT
LMIN t 0.36 ˜
fSW (5)
9.2.2.5 Output Capacitor Selection
The value of the output capacitor and the ESR of the capacitor determine the output voltage ripple and load
transient performance. The output capacitor bank is usually limited by the load transient requirements, rather
than the output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance
and an upper bound on the ESR, which is required to meet a specified load transient.

'IOUT ª K2 º
COUT t ˜«1 D ˜ 1 K ˜ 2 D»
fSW ˜ 'VOUT ˜ K «¬ 12 »¼

2 K ˜ 'VOUT
ESR d
ª K2 § 1 ·º
2 ˜ 'IOUT «1 K ˜ ¨¨1 ¸»
¬« 12 © (1 D) ¸¹¼»

VOUT
D
VIN (6)

where
• ΔVOUT = output voltage transient
• ΔIOUT = output current transient
• K = ripple factor from Section 9.2.2.4
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the peak-to-peak
output voltage ripple; Vr.

1
Vr # 'IL ˜ ESR 2 2
8 ˜ fSW ˜ COUT (7)

The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example, a ΔVOUT ≤ 250 mV for an output current step of ΔIOUT = 2 A is required. Equation 6 gives a
minimum value of 45 µF and a maximum ESR of 0.11 Ω. Assuming a 20% tolerance and a 10% bias de-rating,
you arrive at a minimum capacitance of 63 µF. This can be achieved with a bank of 4 × 22-µF, 16-V ceramic
capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response.
Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic
capacitor can be placed in parallel with the ceramics to help build up the required value of capacitance. In
general, use a capacitor of at least 10 V for output voltages of 3.3 V or less and a capacitor of 16 V or more for
output voltages of 5 V and above.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic

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placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range
of 1 nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000
µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of
start-up at full load and loop stability must be performed.
9.2.2.6 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum of 10 µF of ceramic capacitance is required
on the input of the LMR33620. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and maintain the input voltage during load transients. In addition, a small case size, 220-nF
ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency
bypass for the control circuits internal to the device. For this example a 4.7-µF, 50-V, X7R (or better) ceramic
capacitor is chosen. The 220 nF must also be rated at 50 V with an X7R dielectric. The VQFN (RNX) package
provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the
input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus improving the
effectiveness of the input bypassing. In this example, a single 4.7-µF and two 100-nF ceramic capacitors at each
VIN/PGND location.
Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is
especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR
of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of
this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high
impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
worst case RMS value of this current can be calculated from Equation 8 and must be checked against the
manufacturers' maximum ratings.

IOUT
IRMS #
2 (8)
9.2.2.7 CBOOT
The LMR33620 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 10 V is required.
9.2.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, avoid
loading this output with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see Section 8.3.1). A value of 100 kΩ is a good choice in this case. The nominal output
voltage on VCC is 5 V; see Section 7.5 for limits. Do not short this output to ground or any other external voltage.
9.2.2.9 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by

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the use of a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.

VOUT ˜ COUT
CFF
VREF
120 ˜ RFBT ˜
VOUT (9)
9.2.2.10 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can
be accomplished by using the circuit shown in Figure 9-2. The input voltage at which the device turns on is
designated VON; while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100
kΩ and then Equation 10 is used to calculate RENT and VOFF.
VIN

RENT

EN

RENB

Figure 9-2. Setup for External UVLO Application

§ V ON ·
R ENT ¨¨ 1¸¸ ˜ R ENB
© VEN H ¹

§ VEN HYS ·
V OFF V ON ˜ ¨¨ 1 ¸¸
© VEN H ¹ (10)

where
• VON = VIN turnon voltage
• VOFF = VIN turnoff voltage
9.2.2.11 Maximum Ambient Temperature
As with any power conversion device, the LMR33620 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA of the device and PCB combination. The maximum internal die temperature for the LMR33620 must
be limited to 125°C. This establishes a limit on the maximum device power dissipation and therefore the
load current. Equation 11 shows the relationships between the important parameters. It is easy to see that
larger ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and
IC Package Thermal Metrics Application Report, the value of RθJA given in Section 7.4 is not valid for design
purposes and must not be used to estimate the thermal performance of the application. The values reported in
that table were measured under a specific set of conditions that are rarely obtained in an actual application.

TJ TA K 1
IOUT MAX
˜ ˜
R TJA 1 K VOUT (11)

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where
• η = efficiency
The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air
temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent
component placement; to mention just a few. The HSOIC (DDA) package utilizes a die attach paddle, or thermal
pad (PAD) to provide a place to solder down to the PCB heat-sinking copper. This provides a good heat
conduction path from the regulator junction to the heat sink and must be properly soldered to the PCB heat sink
copper. Due to the ultra-miniature size of the VQFN (RNX) package, a DAP is not available. This means that this
package exhibits a somewhat large value RθJA. Typical examples of RθJA vs copper board area can be found
in Figure 9-3 and Figure 9-4. The copper area given in the graph is for each layer; the top and bottom layers
are 2 oz. copper each, while the inner layers are 1 oz. Typical curves of maximum output current vs ambient
temperature are shown in Figure 9-5 and Figure 9-6 . This data was taken with a device/PCB combination giving
an RθJA as noted in the graph. It must be remembered that the data given in these graphs are for illustration
purposes only, and the actual performance in any given application depends on all of the previously mentioned
factors.

44 70
42
40 65
38
36 60

JA (ƒC/w)
(ƒC/W)

34
32 55
JA

30
R

28 50
26
45
24
22 RNX, 4L
DDA, 4L 40
20
0 10 20 30 40 50 60 70
0 10 20 30 40 50 60 70
Copper Area (cm2) C005
Copper Area (cm2) C003

Figure 9-3. Typical RθJA versus Copper Area for a Figure 9-4. RθJA versus Copper Board Area for the
Four-Layer Board and the HSOIC (DDA) Package VQFN (RNX) Package
3 2.5

2.5
Maximum Output Current (A)

Maximum Output Current (A)

2
1.5
1.5
1
1

0.5
0.5

0 0
20 30 40 50 60 70 80 90 100 110 120 130 140 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
Ambient Temperature (ƒC) C004 Ambient Termperature (ƒC) C007

VIN = 12 V VOUT = 5 V VIN = 12 V VOUT = 5 V

ƒSW = 400 kHz RθJA = 30°C/W ƒSW = 400 kHz RθJA = 50°C/W

Figure 9-5. Maximum Output Current versus Figure 9-6. Maximum Output Current versus
Ambient Temperature Ambient Temperature

Use the following resources as a guide to optimal thermal PCB design and estimating RθJA for a given
application environment:

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• Thermal Design by Insight not Hindsight

• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
• Semiconductor and IC Package Thermal Metrics
• Thermal Design Made Simple with LM43603 and LM43602
• PowerPAD™ Thermally Enhanced Package
• PowerPAD™ Made Easy
• Using New Thermal Metrics

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C. The circuit is shown in Figure
9-31, with the appropriate BOM from Table 9-3 or Table 9-4.

100 100
95 95
90 90
85 85
80 80
Efficiency (%)

Efficiency (%)
75 75
70 70
65 65
8V 5V
60 60
55 12V 55 12V
50 24V 50 24V
45 45
36V 36V
40 40
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) C016 Output Current (A) C017

VOUT = 5 V 400 kHz DDA Package VOUT = 3.3 V 400 kHz DDA Package

Figure 9-7. Efficiency Figure 9-8. Efficiency

100 100
95 95
90 90
85 85
80 80
Efficiency (%)

Efficiency (%)

75 75
70 70
65 65
8V 5V
60 60
55 12V 55 12V
50 24V 50 24V
45 45
36V 36V
40 40
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) C013 Output Current (A) C014

VOUT = 5 V 1.4 MHz DDA Package VOUT = 3.3 V 1.4 MHz DDA Package

Figure 9-9. Efficiency Figure 9-10. Efficiency

100 100
95 95
90 90
85 85
80 80
Efficiency (%)

Efficiency (%)

75 75
70 70
65 65
8V 5V
60 60
55 12V 55 12V
50 24V 50 24V
45 45
36V 36V
40 40
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) C009 Output Current (A) C010

VOUT = 5 V 2.1 MHz DDA Package VOUT = 3.3 V 2.1 MHz DDA Package

Figure 9-11. Efficiency Figure 9-12. Efficiency

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100 100
95 95
90 90
85 85
Efficiency (%)

Efficiency (%)
80 80
75 75
70 8V 70 5V
65 65
12V 12V
60 60
24V 24V
55 55
36V 36V
50 50
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) C018 Output Current (A) C019

VOUT = 5 V 400 kHz RNX Package VOUT = 3.3 V 400 kHz RNX Package

Figure 9-13. Efficiency Figure 9-14. Efficiency

100 100
95 95
90 90
85 85

Efficiency (%)
Efficiency (%)

80 80
75 75
70 8V 70 5V
65 65
12V 12V
60 60
24V 24V
55 55
36V 36V
50 50
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) C022 Output Current (A) C021

VOUT = 5 V 1.4 MHz RNX Package VOUT = 3.3 V 1.4 MHz RNX Package

Figure 9-15. Efficiency Figure 9-16. Efficiency

100 100
95 95
90 90
85 85
Efficiency (%)
Efficiency (%)

80 80
75 75
70 8V 70 5V
65 65
12V 12V
60 60
24V 24V
55 55
36V 36V
50 50
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) C020 Output Current (A) C023

VOUT = 5 V 2.1 MHz RNX Package VOUT = 3.3 V 2.1 MHz RNX Package

Figure 9-17. Efficiency Figure 9-18. Efficiency

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5.055 34
8V
5.05
12V 32
5.045

Input Supply Current (µA)

5.04 24V 30
Output Voltage (V)

5.035 36V
5.03 28

5.025 26
5.02
5.015 24
5.01
22
5.005
5V
5 20
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 5 10 15 20 25 30 35 40
Output Current (A) C011 Input Voltage (V) C016

VOUT = 5 V VOUT = 5 V RFBT = 1 MΩ IOUT = 0 A

Figure 9-19. Line and Load Regulation Figure 9-20. Input Supply Current
0.25 10000000

1000000

Switching Frequency (Hz)

0.2
100000
Output Current (A)

0.15 10000
X
PWM 1000
0.1 8V
PFM 100 12V
X
0.05 10 24V
36V
5V 1
0 0.00001 0.0001 0.001 0.01 0.1 1 10
0 5 10 15 20 25 30 35 40
Output Current (A) C014
Input Voltage (V) C005
VOUT = 5 V ƒSW = 400 kHz
VOUT = 5 V ƒSW = 400 kHz

Figure 9-22. Switching Frequency versus Output

Figure 9-21. Mode Change Thresholds
Current

VOUT,
300mV/Div VOUT,
300mV/Div

Output Current, Output Current,

0.5A/Div 0.5A/Div

100µs/Div 100µs/Div

VIN = 12 V VOUT = 5 V VIN = 12 V VOUT = 5 V

tf = tr = 2 µs IOUT = 0 A to 2 A tf = tr = 2 µs IOUT = 1 A to 2 A

Figure 9-23. Load Transient Figure 9-24. Load Transient

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3.345 34
5V
3.34 32
12V

Input Supply Current (µA)

3.335 24V 30
Output Voltage (V)

3.33 36V
28
3.325
26
3.32
24
3.315

3.31 22
3.3V
3.305 20
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 5 10 15 20 25 30 35 40
Output Current (A) C012 Input Voltage (V) C015

VOUT = 3.3 V VOUT = 3.3 V IOUT = 0 A RFBT = 1 MΩ

Figure 9-25. Line and Load Regulation Figure 9-26. Input Supply Current
0.35 10000000

0.30 1000000

Switching Frequency (Hz)

0.25 100000
Output Current (A)

0.20 10000

X 1000
0.15 5V
PWM
100 12V
0.10
PFMX 10 24V
0.05
36V
3.3V 1
0.00 0.00001 0.0001 0.001 0.01 0.1 1 10
0 5 10 15 20 25 30 35 40
Output Current (A) C015
Input Voltage (V) C006
VOUT = 3.3 V ƒSW = 400 kHz
VOUT = 3.3 V ƒSW = 400 kHz

Figure 9-28. Switching Frequency versus Output

Figure 9-27. Mode Change Thresholds
Current

VOUT,
300mV/Div VOUT,
300mV/Div

Output Current, Output Current,

0.5A/Div 0.5A/Div

0 100µs/Div 100µs/Div

VIN = 12 V VOUT = 3.3 V VIN = 12 V VOUT = 3.3 V IOUT = 1 A to 2 A

tf = tr = 2 µs IOUT = 0 A to 2 A tf = tr = 2 µs

Figure 9-29. Load Transient Figure 9-30. Load Transient

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L
VOUT
VIN VIN SW
U1
CIN CBOOT
CHF BOOT COUT
EN
0.1 µF
RFBT
PG 100 NŸ

PG
100 NŸ VCC FB
CVCC
1 µF PGND AGND
RFBB

Figure 9-31. Circuit for Application Curves

Table 9-3. BOM for Typical Application Curves DDA Package

VOUT (1) FREQUENCY RFBB COUT CIN + CHF L U1
3.3 V 400 kHz 43.3 kΩ 4 × 22 µF 1 × 10 µF + 1 × 220 nF 6.8 µH, 14 mΩ LMR33620ADDA
3.3 V 1400 KHz 43.3 kΩ 4 × 22 µF 1 × 10 µF + 1 × 220 nF 2.2 µH, 11.4 mΩ LMR33620BDDA
3.3 V 2100 kHz 43.3 kΩ 4 × 22 µF 1 × 10 µF + 1 × 220 nF 1.2 µH, 16 mΩ LMR33620CDDA
5V 400 kHz 24.9 kΩ 4 × 22 µF 1 × 10 µF + 1 × 220 nF 8.2 µH, 14 mΩ LMR33620ADDA
5V 1400 KHz 24.9 kΩ 4 × 22 µF 1 × 10 µF + 1 × 220 nF 2.2 µH, 11.4 mΩ LMR33620BDDA
5V 2100 kHz 24.9 kΩ 4 × 22 µF 1 × 10 µF + 1 × 220 nF 1.5 µH, 8.2 mΩ LMR33620CDDA

(1) The values in this table were selected to enhance certain performance criteria and may not represent typical values.

Table 9-4. BOM for Typical Application Curves RNX Package

VOUT (1) FREQUENCY RFBB COUT CIN + CHF L U1
3.3 V 400 kHz 43.3 kΩ 4 × 22 µF 2 × 4.7 µF + 2 × 100 nF 4.7 µH, 28 mΩ LMR33620ARNX
3.3 V 1400 KHz 43.3 kΩ 4 × 22 µF 2 × 4.7 µF + 2 × 100 nF 2.2 µH, 11.4 mΩ LMR33620BRNX
3.3 V 2100 kHz 43.3 kΩ 4 × 22 µF 2 × 4.7 µF + 2 × 100 nF 2.2 µH, 11.4 mΩ LMR33620CRNX
5V 400 kHz 24.9 kΩ 4 × 22 µF 2 × 4.7 µF + 2 × 100 nF 6.8 µH, 14 mΩ LMR33620ARNX
5V 1400 KHz 24.9 kΩ 4 × 22 µF 2 × 4.7 µF + 2 × 100 nF 2.2 µH, 11.4 mΩ LMR33620BRNX
5V 2100 kHz 24.9 kΩ 4 × 22 µF 2 × 4.7 µF + 2 × 100 nF 2.2 µH, 11.4 mΩ LMR33620CRNX

(1) The values in this table were selected to enhance certain performance criteria and may not represent typical values.

9.3 What to Do and What Not to Do

• Don't: Exceed the Absolute Maximum Ratings.
• Don't: Exceed the ESD Ratings.
• Don't: Exceed the Recommended Operating Conditions.
• Don't: Allow the EN input to float.
• Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
• Don't: Use the value of RθJA given in the Section 7.4 table to design your application. Use the information in
Section 9.2.2.11.
• Do: Follow all the guidelines and suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see Support Resources).

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Power Supply Recommendations

The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and
Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable
of delivering the required input current to the loaded regulator. The average input current can be estimated with
Equation 12, where η is the efficiency.

VOUT ˜ IOUT
IIN
VIN ˜ K (12)

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to
the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient
is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause
the regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and/or use an aluminum or tantalum input capacitor in parallel
with the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and
reduce any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and
help to hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The user guide
AN-2162 Simple Success With Conducted EMI From DCDC Converters provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this
device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than
the output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharges through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then a Schottky diode between the input supply and the output should be used.

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10 Layout
10.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter,
the most critical PCB feature is the loop formed by the input capacitor or input capacitors, and power ground,
as shown in Figure 10-1. This loop carries large transient currents that can cause large transient voltages when
reacting with the trace inductance. These unwanted transient voltages will disrupt the proper operation of the
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. Figure 10-2 and Figure 10-3 show recommended layouts for the critical
components of the LMR33620.
1. Place the input capacitor or capacitors as close as possible to the VIN and GND terminals. VIN and
GND pins are adjacent, simplifying the input capacitor placement. With the VQFN package there are two
VIN/PGND pairs on either side of the package. This provides for a symmetrical layout and helps minimize
switching noise and EMI generation. A wide VIN plane must be used on a lower layer to connect both of the
VIN pairs together to the input supply; see Figure 10-3.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the
BOOT and SW pins. For the VQFN package, it is important to route the SW connection under the device to
the NC pin, and use this path to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF,
if used, physically close to the device. The connections to FB and GND must be short and close to those
pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act
as a heat dissipation path.
6. Connect the thermal pad to the ground plane. The SOIC package has a thermal pad (PAD) connection
that must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an
electrical ground connection for the regulator. The integrity of this solder connection has a direct bearing on
the total effective RθJA of the application.
7. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
8. Provide enough PCB area for proper heat sinking. As stated in Section 9.2.2.11, enough copper
area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient
temperature. Make the top and bottom PCB layers with two-ounce copper; and no less than one ounce. With
the SOIC package, use an array of heat-sinking vias to connect the thermal pad (PAD) to the ground plane
on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended), thermal vias can
also be connected to the inner layer heat-spreading ground planes.
9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node should be minimized to help reduce radiated EMI.

See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies
• Simple Switcher PCB Layout Guidelines
• Construction Your Power Supply- Layout Considerations
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x

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VIN

KEEP
CIN CURRENT SW
LOOP
SMALL

GND

Figure 10-1. Current Loops with Fast Edges

10.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
TI recommends providing adequate device heat sinking by utilizing the thermal pad (PAD) of the device as the
primary thermal path. Use a minimum 4 × 3 array of 10-mil thermal vias to connect the PAD to the system
ground plane heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible,
for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with
the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with
enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and
lower thermal resistance.

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10.2 Layout Example

GND
HEATSINK INDUCTOR

VOUT

COUT COUT COUT

CBOOT
GND CHF

CIN
EN CVCC

VIN PGOOD

RFBB RFBT

GND

GND
HEATSINK

VIA VIA
Top Trace Bottom Trace
Ground Plane Bottom

Figure 10-2. Example Layout for HSOIC (DDA) Package

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VOUT VOUT
INDUCTOR

COUT COUT COUT COUT

GND GND

CIN CIN
CHF CHF
1 12 11

2 10

VIN 3 9
EN VIN
CBOOT

4 8 PGOOD
5 6 7

RFBT
CVCC RFBB

GND
GND
HEATSINK
HEATSINK

INNER GND PLANE

Top Trace/Plane

Inner GND Plane

VIN Strap on Inner Layer

Top

VIA to Signal Layer Inner GND Plane

VIN Strap and

VIA to GND Planes GND Plane

Signal traces
VIA to VIN Strap and GND Plane

Trace on Signal Layer

Figure 10-3. Example Layout for VQFN Package

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11 Device and Documentation Support

11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM33620 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Thermal Design by Insight not Hindsight
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
• Semiconductor and IC Package Thermal Metrics
• Thermal Design Made Simple with LM43603 and LM43602
• PowerPADTM Thermally Enhanced Package
• PowerPADTM Made Easy
• Using New Thermal Metrics
• Layout Guidelines for Switching Power Supplies
• Simple Switcher PCB Layout Guidelines
• Construction Your Power Supply- Layout Considerations
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

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11.5 Trademarks
HotRod™, TI E2E™ are trademarks of Texas Instruments.
PowerPAD™ is a trademark of TI.
WEBENCH® is a registered trademark of Texas Instruments.
SIMPLE SWITCHER® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Tape and Reel Information
REEL DIMENSIONS TAPE DIMENSIONS
K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants
Reel Reel
Package Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter Width W1
Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) (mm)
SO
LMR33620ADDAR DDA 8 2500 330 12.4 6.4 5.2 2.1 8 12 Q1
PowerPAD
SO
LMR33620BDDAR DDA 8 2500 330 12.4 6.4 5.2 2.1 8 12 Q1
PowerPAD
SO
LMR33620CDDAR DDA 8 2500 330 12.4 6.4 5.2 2.1 8 12 Q1
PowerPAD

38 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: LMR33620

 LMR33620
www.ti.com SNVSAW1E – FEBRUARY 2018 – REVISED NOVEMBER 2020

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

L
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR33620ADDA SO PowerPAD DDA 8 75 521 194 37
LMR33620ADDAR SO PowerPAD DDA 8 2500 353 353 36
LMR33620BDDA SO PowerPAD DDA 8 75 521 194 37
LMR33620BDDAR SO PowerPAD DDA 8 2500 353 353 36
LMR33620CDDA SO PowerPAD DDA 8 75 521 194 37
LMR33620CDDAR SO PowerPAD DDA 8 2500 353 353 36

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39

Product Folder Links: LMR33620
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Jun-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LMR33620ADDA Active Production SO PowerPAD 75 | TUBE Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 33620A
(DDA) | 8
LMR33620ADDA.A Active Production SO PowerPAD 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620A
(DDA) | 8
LMR33620ADDAR Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 33620A
(DDA) | 8
LMR33620ADDAR.A Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620A
(DDA) | 8
LMR33620ADDARG4 Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620A
(DDA) | 8
LMR33620ADDARG4.A Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620A
(DDA) | 8
LMR33620ARNXR Active Production VQFN-HR (RNX) | 12 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 33620A
LMR33620ARNXR.A Active Production VQFN-HR (RNX) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620A
LMR33620ARNXT Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 33620A
LMR33620ARNXT.A Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620A
LMR33620BDDA Active Production SO PowerPAD 75 | TUBE Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 33620B
(DDA) | 8
LMR33620BDDA.A Active Production SO PowerPAD 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620B
(DDA) | 8
LMR33620BDDAR Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 33620B
(DDA) | 8
LMR33620BDDAR.A Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620B
(DDA) | 8
LMR33620BRNXR Active Production VQFN-HR (RNX) | 12 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 33620B
LMR33620BRNXR.A Active Production VQFN-HR (RNX) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620B
LMR33620BRNXT Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 33620B
LMR33620BRNXT.A Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620B
LMR33620CDDA Active Production SO PowerPAD 75 | TUBE Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 33620C
(DDA) | 8
LMR33620CDDA.A Active Production SO PowerPAD 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620C
(DDA) | 8

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Jun-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LMR33620CDDAR Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 33620C
(DDA) | 8
LMR33620CDDAR.A Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620C
(DDA) | 8
LMR33620CRNXR Active Production VQFN-HR (RNX) | 12 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 33620C
LMR33620CRNXR.A Active Production VQFN-HR (RNX) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620C
LMR33620CRNXT Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 33620C
LMR33620CRNXT.A Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620C
LMR33620CRNXTG4 Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620C
LMR33620CRNXTG4.A Active Production VQFN-HR (RNX) | 12 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 33620C

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Jun-2025

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMR33620 :

• Automotive : LMR33620-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jun-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR33620ARNXR VQFN- RNX 12 3000 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
HR
LMR33620ARNXT VQFN- RNX 12 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
HR
LMR33620BRNXR VQFN- RNX 12 3000 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
HR
LMR33620BRNXT VQFN- RNX 12 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
HR
LMR33620CRNXR VQFN- RNX 12 3000 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
HR
LMR33620CRNXT VQFN- RNX 12 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
HR
LMR33620CRNXTG4 VQFN- RNX 12 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
HR

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jun-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR33620ARNXR VQFN-HR RNX 12 3000 210.0 185.0 35.0
LMR33620ARNXT VQFN-HR RNX 12 250 210.0 185.0 35.0
LMR33620BRNXR VQFN-HR RNX 12 3000 210.0 185.0 35.0
LMR33620BRNXT VQFN-HR RNX 12 250 210.0 185.0 35.0
LMR33620CRNXR VQFN-HR RNX 12 3000 210.0 185.0 35.0
LMR33620CRNXT VQFN-HR RNX 12 250 210.0 185.0 35.0
LMR33620CRNXTG4 VQFN-HR RNX 12 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jun-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LMR33620ADDA DDA HSOIC 8 75 517 7.87 635 4.25
LMR33620ADDA DDA HSOIC 8 75 507.79 8 630 4.32
LMR33620ADDA.A DDA HSOIC 8 75 507.79 8 630 4.32
LMR33620ADDA.A DDA HSOIC 8 75 517 7.87 635 4.25
LMR33620BDDA DDA HSOIC 8 75 517 7.87 635 4.25
LMR33620BDDA DDA HSOIC 8 75 507.79 8 630 4.32
LMR33620BDDA.A DDA HSOIC 8 75 507.79 8 630 4.32
LMR33620BDDA.A DDA HSOIC 8 75 517 7.87 635 4.25
LMR33620CDDA DDA HSOIC 8 75 517 7.87 635 4.25
LMR33620CDDA DDA HSOIC 8 75 507.79 8 630 4.32
LMR33620CDDA.A DDA HSOIC 8 75 517 7.87 635 4.25
LMR33620CDDA.A DDA HSOIC 8 75 507.79 8 630 4.32

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
RNX 12 VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
2 x 3 mm, 0.5 mm pitch

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224286/A
 PACKAGE OUTLINE
RNX0012B SCALE 4.500
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2.1
B A
1.9

PIN 1 INDEX AREA

3.1
2.9 0.1 MIN

(0.05)

SECTION A-A
A-A 40.000

TYPICAL

0.9
C
0.8

SEATING PLANE
0.05
0.00 0.08 C
1

SYMM
(0.2) TYP
5 7

4X 0.5
4 8

2X
0.675
PKG

2X
2X 1.725
1.125 1.525
0.65
A 11
A
1

12
PIN 1 ID 0.3
0.3 11X
0.2
0.2
0.1 C B A
0.5
11X 0.05 C
0.3

4223969/C 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RNX0012B VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.25)
12

11X (0.6)
1 2X (0.65)
11

11X
(0.25) (1.825)
2X
(1.125)
(0.788)

PKG

2X
(0.675) 4X (0.5)

8 (1.4)
4

(R0.05) TYP

5 7
SYMM

(1.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:25X

0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
SOLDER MASK
METAL EDGE OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL METAL
OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) PADS 1, 2, 10-12

SOLDER MASK DETAILS

4223969/C 10/2018
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
RNX0012B VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (0.25)
2X (0.812) 12
11X (0.6)
11X (0.25)
1
11

2X
EXPOSED METAL (0.65) (1.294)
2X
(1.125)

PKG

(0.282)
2X (0.675)
4X (0.5)

8 (1.4)
4

(R0.05) TYP

5 7
SYMM

(1.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PAD 12
87.7% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4223969/C 10/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
RNX0012C VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

2.1 A
B 1.9

PIN 1 INDEX AREA 3.1

2.9

0.1 MIN

(0.13)

SECTION A-A
TYPICAL

1.0
0.8 C

SEATING PLANE
0.05 0.08 C
0.00 1
PKG
(0.2) TYP
5 7

(0.16)
4X 0.5
4 8

2X
PKG 0.675

2X
1.125 1.725
2X 1.525
0.65 A A
11
1

12
PIN 1 ID 0.3 11X 0.3
0.2
0.2
11X 0.5
0.3
0.1 C A B
0.05 C
4225021/C 05/2022
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RNX0012C VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

(0.25)
11X (0.6) 12

11X (0.25) 2X (0.65)

1
11

(1.825)
2X
(1.125)
(0.7875)
PKG

2X
(0.675) 4X (0.5)
8 (1.4)
4

5 7
(R0.05) TYP PKG

(1.8)

LAND PATTERN EXAMPLE

SCALE: 20X

0.075 MAX 0.075 MIN

ALL AROUND SOLDER MASK
ALL AROUND OPENING
METAL
EXPOSED METAL

EXPOSED METAL SOLDER MASK

OPENING METAL

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225021/C 05/2022

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
RNX0012C VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

2X (0.25)

11X (0.6) 2X (0.812)

12

11X (0.25) 2X (0.65)

1
11

2X EXPOSED (1.294)
(1.125) METAL

PKG (0.281)

2X
(0.675) 4X (0.5)
8 (1.4)
4

5 7
(R0.05) TYP PKG

(1.8)

SOLDER PASTE EXAMPLE

BASED ON 0.100 mm THICK STENCIL

FOR PAD 12
87.7% PRINTED COVERAGE BY AREA
SCALE: 20X

4225021/C 05/2022

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.1 0.25
2.5 GAGE PLANE

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0

4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9

6X (1.27)

5
4

( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK

(1.3) TYP

(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221637/B 03/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8

8X (0.6)

(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED SEE TABLE FOR

SYMM DIFFERENT OPENINGS
BY SOLDER MASK
FOR OTHER STENCIL
THICKNESSES
(5.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.91 X 3.47
0.125 2.6 X 3.1 (SHOWN)
0.150 2.37 X 2.83
0.175 2.20 X 2.62

4221637/B 03/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

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