Digital Signal Processing: Laboratory Experiments Using C and the TMS320C31 DSK

Rulph Chassaing
Copyright © 1999 John Wiley & Sons, Inc.
Print ISBN 0-471-29362-8 Electronic ISBN 0-471-20065-4

C
External and Flash Memory

This appendix describes a homemade daughter board with 32K words (32-bit
wide) of external memory and 128K bytes of flash memory. This board con-
nects directly to (fits underneath) the DSK through the four 32-pin connectors
JP2-3 and JP5-6 along the edge of the DSK board. All the appropriate signals
used on the TMS320C31, such as address, data, V+, GND, R/W, INT0-3, and
STRB are available through these four connectors. Figure C.1 shows a photo of
the DSK with the daughter board. A specific application program can run from
flash without any connection through the PC, as illustrated later. Programming
examples test the external memory board with the supporting files on the ac-
companying disk. Figure C.2 shows a diagram of the daughter board with the
external SRAM and flash memory.

CONSTRUCTION OF THE EXTERNAL/FLASH MEMORY BOARD

The external memory board was constructed using a 4⬙ x 5⬙ Vector board with
copper on one side, with the following parts purchased for approximately $107:

Quantity Parts description Price

1 Vector 4⬙ x 5⬙ 169P44C1 copper circuit board $ 16.00
16 3M P/N 3397-1240 wire connection strips 15.00
4 32-pin DIL plug—AMP P/N 1-534206-6 11.00
4 32-pin DIL header—0.1 inch spacing 15.00
1 12-pin DIL header—0.1 inch spacing 2.00
4 28-pin IC socket—0.3 wide 7.00
1 32-pin IC socket—0.5 wide 1.00
2 14-pin IC socket—0.3 wide 1.50
1 2.5mm power connector 3.50
4 14 ns 32K x 8 SRAM 16.00
1 AM29F010-70PC flash memory 11.00

283
284 External and Flash Memory

FIGURE C.1 Photo of DSK and daughter board with external and flash memory.

Quantity Parts description Price

1 74AS27 3-input NOR gate 1.00
1 74S00 2-input NAND gate 1.00
7 0.1␮F ceramic decoupling capacitors 1.00
1 47␮F/25V tantalum capacitor 1.00
1 10␮F/10V tantalum capacitor 1.00
1 LM340T5 voltage regulator 2.00
6 (3) 10K and (3) 470 ¼ watt resistors 1.00
————
Total $ 107.00

The four 32-pin DIL plugs are to be carefully soldered into the DSK board. The
corresponding holes in the vector board are marked for the mating 32-pin head-
er connectors. A pad cutter is used for all signal pins of the four 32-pin header
connectors, except the ground pins. Provide a low-impedance power trace to the
SRAM’s and supporting IC’s, with a power strip between two adjacent perforat-
ed holes to create an isolated trace (0.2 inch wide) and route power to all the
power pins. After the IC sockets are soldered to the vector board, the wire con-
nection strips can then be soldered to the pins on the IC sockets.
A 5-volt regulator supplies power to the external board, since the current
285
FIGURE C.2 Diagram of external and flash memory.
286 External and Flash Memory

drawn is too high to use the 5-volt supply on the DSK. Connect the power to the
V+ pins 23 and 24 from connector JP6 to allow both the DSK and the external
board to be powered from one external power supply.

C.1 EXTERNAL MEMORY

The address lines are decoded to provide the following memory decode ranges:

Memory range (Hex) A22 A23

0–3FFFFF Low Low
400000–7FFFFF High Low
800000–BFFFFF Low High
C00000–FFFFFF High High

Since the DSK does not decode any address below 800000h, the first decode
range of 0–3FFFFFh is chosen for the external SRAM. The external SRAM can
be accessed through any 32K boundary within this range, such as 8000h,
200000h, 300000h, or any valid 8000h boundary within the decoded ad-
dress range 0–3FFFFF. Since the addresses 0–FFFh are reserved for the boot
loader operations on the TMS320C31, as shown in Figure 2.2, the starting ad-
dress of 100000h is chosen for the external SRAM.
The STRB output is used to qualify for a valid external memory address on
the external bus. For example, the STRB line would not be asserted in the mem-
ory range reserved for the boot loader operations or associated with any
TMS320C31 reserved-memory locations listed in the memory map.
For zero wait state operations, an access time of 15 ns or less for the SRAM
chips should be used. A 32K x 8 bit SRAM with these specifications can be
purchased, such as the L7C199PC15 from Logical Devices, the MCM6206-15P
from Motorola, or the UM61256FK-15. The propagation delay of the logic
gates must have a combined delay of less than 6 ns to decode the two MSBs of
the TMS320C31 address bus that are used for chip selects of the SRAMs and
flash devices.

Testing the External Memory

The program TESTMEM.CPP (on the accompanying disk) is used to test the ex-
ternal memory SRAM. It is to be compiled using Borland’s C/C++ compiler.
Different data is written to the memory locations 100000h–107FFFh (32K x
32) on the SRAM and the same data is read back. If any memory error is en-
countered, the program will halt and display the memory location with the error.
Execute this program. For example, option 1 writes the value 0xAAAAAAAA to
memory, and then reads it back from memory locations 0x100000 to
0x107FFF (32k words).
 C.2 Flash Memory 287

Example C.1 Multirate Filter With 10 Bands Using

External Memory and TMS320C3x Code
The 10-band multirate filter is described in Chapter 8, where a 7-band version
was implemented. The 10-band multirate filter requires over 3K words of pro-
gram and data memory spaces and cannot be implemented on the DSK without
additional memory. The program MR10SRAM.ASM (on the accompanying disk)
implements the 10-band multirate filter using the daughter board with 32K
words of additional memory. Text or code starts at the address 0x100000,
which is the starting address of SRAM. The sampling frequency is set at ap-
proximately 16 kHz, and band 8 is turned on. Download the executable DSK
file as done throughout the manual. Verify a bandpass filter centered at 1 kHz.
With band 10 on, the center frequency is at 4 kHz.

C.2 FLASH MEMORY

The daughter board includes the 1 Megabit or 128K x 8 bit 29F010 flash mem-
ory chip, available from Advanced Micro Devices [1–4]. The flash memory ad-
dress is chosen to start at 400000h to correspond to the second boot region in
the TMS320C31 memory map. By configuring INT0, INT2, INT3 High and
INT1 Low, the TMS320C31 starts boot loading from address 400000h. Four
jumpers, used to obtain these conditions when running from flash, must be re-
moved when downloading a program through external memory to flash.
The flash memory is divided into 8 sectors of 16K Bytes and can be repro-
grammed in standard EPROM programmers, requiring a single 5-V power sup-
ply operation for both read and write functions. It can store TMS320C3x code
and allows the DSK to boot up out of flash memory when the external board is
powered. To program the flash, the host PC program downloads a bootable hex
file into the external SRAM and the flash memory is then written 8 bits at a
time from the external SRAM until the entire hex file is programmed into the
flash.

Example C.2 Sine Generation With Four Points From Flash

Memory, Using C Code
This example illustrates a sine generation with four points with the program
SINEHEX.C shown in Figure C.3, run from flash. All appropriate support files
are on the accompanying disk. A version of this sine generation program was
tested with the DSK in Experiment 3. The DB25 cable is not connected to the
PC, and the program runs when power is applied to the daughter board only.
This program runs with zero wait states. By setting the primary bus control reg-
ister with 0x1018 (see Appendix A), bits 5–7, which designate WTCNT =
(000)b = 0, specify zero wait states [5].
288 External and Flash Memory

/*SINEHEX.C - SINE GENERATION PROGRAM TO RUN FROM FLASH */

#include “aiccomc.c” /*AIC comm routines */
int AICSEC[4] = {0x162C,0x1,0x4892,0x67}; /*AIC data */
int data_out, loop = 0; /*declare global variables */
int sin_table[4]={0,4096,0,-4096}; /*values for 4-point sinewave */

void c_int05() /*TINT0 interrupt routine */

{
PBASE[0x48]=sin_table[loop] << 2; /*output value from sine table*/
if (loop < 3) ++loop; /*increment loop counter < 3 */
else loop = 0; /*reset loop counter */
}

main()
{
unsigned int *pAddr;
pAddr = (unsigned int *)0x808064; /*primary bus control register*/
*pAddr = 0x1018; /*set WTCNT for 0 wait states */
pAddr = (unsigned int *)0x808038;
*pAddr = 0x00100000; /*set timer 1 period */
pAddr = (unsigned int *)0x808030;
*pAddr = 0x000003C1; /*set timer1 control register */
AICSET_I(); /*function to configure AIC */
for (;;); /*wait for interrupt */
}

FIGURE C.3 Program to generate sine using flash memory (SINEHEX.C).

1. Compile the program SINEHEX.C with the TMS320 tools.

2. Link with the linker command file SINEHEX.CMD, which creates the ex-
ecutable COFF file SINEHEX.OUT and a map file SINEHEX.MAP
(both on disk).
3. Locate from the map file the entry address of “_c_int00” as
0x10008C.
4. Edit the file SINHEX30.CMD (on disk) to specify the entry address of
0x10008C.
5. Create the hex file SINEHEX.A0 (on disk) with the command Hex30
SINHEX30.CMD.
 References 289

6. Download this hex file through the external memory to the flash with the
command C31DLHEX SINEHEX.A0.

The file C31DLHEX.CPP is to be compiled using Borland’s C/C++ compiler.

The file HEX30.EXE is provided with the TMS320 floating-points tools de-
scribed in Chapter 1. The sine generator program is executed once power is ap-
plied to the daughter board, producing a 2-kHz tone. The LED on the DSK
board should flash rapidly.

Example C.3 FIR Bandpass Filter From Flash Memory

Using C Code
The FIR bandpass filter program FIRC.C was implemented in Chapter 4. It is
modified to yield BP45HEX.C (on disk) to run from flash. Repeat the proce-
dure in the previous example to create and download the hex file
BP45HEX.A0 (on disk) to run from flash. On power to the external board, a
bandpass FIR filter with a center frequency at Fs/10 or 800 Hz is implemented
from flash. Verify these results.

REFERENCES

1. AM29F010 Data Sheet, Publication #16736, Advanced Micro Devices, Sunnyvale, CA,
October 1996, at www.amd.com.
2. AM29F010 1 Megabit CMOS 5.0 Volt-only, Sector Erase Flash Memory, Publication
#16736, Advanced Micro Devices, Sunnyvale, CA, November 1995.
3. K. Prabhat, Design-in with AMD’s AM29F010–Application Note, Publication #17097,
Advanced Micro Devices, Sunnyvale, CA, November 1995.
4. K. Prabhat, Reprogrammable Flash BIOS Design Using AMD’s AM29F010–Application
Note, Publication #17078, Advanced Micro Devices, Sunnyvale, CA, March 1994.
5. TMS320C3x User’s Guide, Texas Instruments Inc., Dallas, TX, 1997.