DIGITAL ELECTRONICS AND COMPUTER

ORGANIZATION
(CSE207)

Practical File

AMITY SCHOOL OF ENGINEERING AND

TECHNOLOGY
AMITY UNIVERSITY, UTTAR PRADESH

Submitted By: Yash Jindal

A2305220130
3CSE2-Y

Yash Jindal A2305220130

 Index

S.No Aim of the Experiment Date

.
1 Verification and interpretation of truth table for AND, OR, 12/08/2021
NOT, NAND, NOR, Ex-OR, Ex-NOR gates.
2 To verify and study half adder 19/08/2021

3 To verify and study full adder 19/08/2021

4 To verify and study half subtractor 26/08/2021
5 To verify and study full subtractor 26/08/2021
6 Implementation of 4x1 and 8x1 multiplexer 02/09/2021
7 To design a 1x4 and 1x8 De-multiplexer using NAND gates. 09/09/2021
8 Implementation and verification of decoder 16/09/2021
9 To design a 4-bit combinational shifter using logic gates. 23/09/2021
10 To design an ALU 30/09/2021
11 To design a 4-Bit BCD adder 14/10/2021
12 To design a 4-bit adder subtractor 28/10/2021

Yash Jindal A2305220130

Experiment 1

Aim - Verification and interpretation of truth table for AND, OR, NOT, NAND, NOR,
Ex-OR, Ex-NOR gates.

Tools Used – Circuitverse, IITR Vlab

Theory –
Logic gates are the basic building blocks of any digital system. Logic gates are
electronic circuits having one or more than one input and only one output. The
relationship between the input and the output is based on a certain logic. Based on
this, logic gates are named as:-
1. AND gate
2. OR gate
3. NOT gate
4. NAND gate
5. NOR gate
6. Ex-OR gate
7. Ex-NOR gate

1) AND gate
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs
are high. A dot (.) is used to show the AND operation i.e. A.B or can be written as AB
Y= A.B

Figure-1:Logic Symbol of AND Gate

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Figure-2:Truth Table of AND Gate

2) OR gate
The OR gate is an electronic circuit that gives a high output (1) if one or more of its
inputs are high. A plus (+) is used to show the OR operation.

Y= A+B

Figure-4:Logic Symbol of OR Gate

Figure-5:Truth Table of OR Gate

3) NOT gate
The NOT gate is an electronic circuit that produces an inverted version of the input at

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its output. It is also known as an inverter. If the input variable is A, the inverted output
is known as NOT A. This is also shown as A' or A with a bar over the top, as shown
at the outputs.

Y= A'

Figure-7:Logic Symbol of NOT Gate

Figure-8:Truth Table of NOT Gate

4) NAND gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an
AND gate with a small circle on the output. The small circle represents inversion.

Y= AB

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Figure-10:Logic Symbol of NAND Gate

Figure-11:Truth Table of NAND Gate

5) NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR
gate with a small circle on the output. The small circle represents inversion.

Y= A+B

Figure-13:Logic Symbol of NOR gate

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Figure-14:Truth Table of NOR gate

6) Ex-OR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both
of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR
operation.

Y= A⊕B

Figure-16:Logic Symbol of Ex-OR gate

Figure-17:Truth Table of Ex-OR gate

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7) Ex-NOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a
low output if either, but not both of its two inputs are high. The symbol is an EX-OR
gate with a small circle on the output. The small circle represents inversion.

Y= A⊕B

Figure-19:Logic Symbol of Ex-NOR gate

Figure-20:Truth Table of Ex-NOR gate

Observations –

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Yash Jindal A2305220130
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Result – Logic Gates are successfully verified

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Experiment 2

Aim - To verify the truth table of half adder by using XOR and NAND gates and
analyse the working of half adder circuit with the help of LEDs in simulator 1 and
verify the truth table only of half adder

Tools Used – Circuitverse, IITR Vlab

Theory –
Adders are digital circuits that carry out addition of numbers. Adders are a key
component of arithmetic logic unit. Adders can be constructed for most of the
numerical representations like Binary Coded Decimal (BCD), Excess – 3, Gray code,
Binary etc. out of these, binary addition is the most frequently performed task by
most common adders. Apart from addition, adders are also used in certain digital
applications like table index calculation, address decoding etc.

Binary addition is similar to that of decimal addition. Some basic binary additions are
shown below.

Figure 1. Schematic representation of half adder

1)Half Adder
Half adder is a combinational circuit that performs simple addition of two binary
numbers. If we assume A and B as the two bits whose addition is to be
performed,the block diagram and a truth table for half adder with A, B as inputs and
Sum, Carry as outputs can be tabulated as follows.

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Figure 2. Block diagram and truth table of half adder

The sum output of the binary addition carried out above is similar to that of an Ex-OR
operation while the carry output is similar to that of an AND operation. The same can
be verified with help of Karnaugh Map.
The truth table and K Map simplification and logic diagram for sum output is shown

below.

Figure 3. Truth table, K Map simplification and Logic diagram for sum output
of half adder

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Observations –

Construction

Result – Full and half adder are successfully constructed and verified

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Experiment 3

Aim - To verify the truth table of full adder by using XOR and NAND gates and
analyse the working of full adder circuit with the help of LEDs in simulator 1 and
verify the truth table of full adder in simulator 2.

Tools Used – Circuitverse, IITR Vlab

Theory –
Adders are digital circuits that carry out addition of numbers. Adders are a key
component of arithmetic logic unit. Adders can be constructed for most of the
numerical representations like Binary Coded Decimal (BCD), Excess – 3, Gray code,
Binary etc. out of these, binary addition is the most frequently performed task by
most common adders. Apart from addition, adders are also used in certain digital
applications like table index calculation, address decoding etc.

Binary addition is similar to that of decimal addition. Some basic binary additions are
shown below.

1)Full Adder

Full adder is a digital circuit used to calculate the sum of three binary bits. Full
adders are complex and difficult to implement when compared to half adders. Two of
the three bits are same as before which are A, the augend bit and B, the addend bit.
The additional third bit is carry bit from the previous stage and is called 'Carry' – in
generally represented by CIN. It calculates the sum of three bits along with the carry.
The output carry is called Carry – out and is represented by Carry OUT.
The block diagram of a full adder with A, B and CIN as inputs and S, Carry OUT as
outputs is shown below.

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Figure 8. Full Adder Block Diagram and Truth Table

Figure 9. Full Adder Logic Diagram

Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT)
can be derived using K – Map.

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Figure 10. The K-Map simplified equation for sum is S = A'B'Cin + A'BCin' +
ABCin

Figure 11. The K-Map simplified equation for COUT is COUT = AB + ACIN +
BCIN

In order to implement a combinational circuit for full adder, it is clear from the
equations derived above, that we need four 3-input AND gates and one 4-input OR
gates for Sum and three 2-input AND gates and one 3-input OR gate for Carry – out.

Observations –

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Full Adder

Result – Full and half adder are successfully constructed and verified

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Experiment 4

Aim - To verify the truth table of half subtractor by using the ICs of XOR, NOT and
AND gates

Tools Used – Circuitverse, IITR Vlab

Theory –
Subtractor circuits take two binary numbers as input and subtract one binary number
input from the other binary number input. Similar to adders, it gives out two outputs,
difference and borrow (carry-in the case of Adder). There are two types of
subtractors.

1. Half Subtractor
2. Full Subtractor

1) Half Subtractor
The half-subtractor is a combinational circuit which is used to perform subtraction of
two bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs
Difference and Borrow. The logic symbol and truth table are shown below.

Figure-1:Logic Symbol of Half subtractor

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 Figure-2:Truth Table of Half subtractor

Figure-3:Circuit Diagram of Half subtractor

From the above truth table we can find the boolean expression.

Difference = A ⊕ B
Borrow = A' B
From the equation we can draw the half-subtractor circuit as shown in the figure 3.

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Observations:

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Result – Half Subtractor is successfully constructor and its truth table is
verified

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Experiment 5

Aim - To verify the truth table of full subtractor by using the ICs of XOR, NOT and
AND gates

Tools Used – Circuitverse, IITR Vlab

Theory –
Subtractor circuits take two binary numbers as input and subtract one binary number
input from the other binary number input. Similar to adders, it gives out two outputs,
difference and borrow (carry-in the case of Adder). There are two types of
subtractors.

1. Half Subtractor
2. Full Subtractor
2) Full Subtractor

A full subtractor is a combinational circuit that performs subtraction involving three

bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three
inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two
outputs: D (difference) and Bout (borrow out). The logic symbol and truth table are
shown below.

Figure-4:Logic Symbol of Full subtractor

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 Figure-5:Truth Table of Full subtractor

From the above truth table we can find the boolean expression.

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin
From the equation we can draw the Full-subtractor circuit as shown in the figure 6.

Figure-6:Circuit Diagram of Full subtractor

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Observations:

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Result – Full Subtractor is successfully constructor and its truth table is
verified

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Experiment 6

Aim - To analyse the truth table and working of 1x4 and 1x8 Multiplexer

Tools Used – Circuitverse, IITR Vlab

Theory –
The function of a multiplexer is to select the input of any ‘n’ input lines and feed that
to one output line. The function of a de-multiplexer is to inverse the function of the
multiplexer and the shortcut forms of the multiplexer. The de-multiplexers are mux
and demux. Some multiplexers perform both multiplexing and de-multiplexing
operations.

Figure-1:Block diagram of Multiplexer and De-multiplexer

1) Multiplexer Multiplexer is a device that has multiple inputs and a single line output.
The select lines determine which input is connected to the output, and also to
increase the amount of data that can be sent over a network within certain time. It is
also called a data selector.

Multiplexers are classified into four types:

a) 2-1 multiplexer (1 select line)
b) 4-1 multiplexer (2 select lines)
c) 8-1 multiplexer(3 select lines)
d) 16-1 multiplexer (4 select lines)

b)4x1 Multiplexer

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4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1
and one output Y. The block diagram of 4x1 Multiplexer is shown in the following
figure.One of these 4 inputs will be connected to the output based on the
combination of inputs present at these two selection lines. Truth table of 4x1
Multiplexer is shown below.

Figure-2:Block diagram of 4x1 Multiplexer

Figure-3:Truth table of 4x1 Multiplexer

c)8x1 Multiplexer
A Boolean equation for 8×1 Multiplexer is
Z = A’.B’.C’ + A’.B’.C + A’.B.C’ + A’.B.C + A.B’.C’ + A.B’.C + A.B.C’ + A.B.C

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Observations –

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Result - 4x1 and 8x1 multiplexers are implemented successfully

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Experiment 7

Aim - To design a 1x4 and 1x8 De-multiplexer using NAND gates

Tools Used – Circuitverse, IITR Vlab

Theory –
The function of a multiplexer is to select the input of any ‘n’ input lines and feed that
to one output line. The function of a de-multiplexer is to inverse the function of the
multiplexer and the shortcut forms of the multiplexer. The de-multiplexers are mux
and demux. Some multiplexers perform both multiplexing and de-multiplexing
operations.

Figure-1:Block diagram of Multiplexer and De-multiplexer

De-multiplexers are classified into four types:
a) 1-2 demultiplexer (1 select line)
b) 1-4 demultiplexer (2 select lines)
c) 1-8 demultiplexer(3 select lines)
d) 1-16 demultiplexer (4 select lines)
1. 1x4 De-multiplexer
1x4 De-Multiplexer has one input Data(D), two selection lines, S0 & S1 and four
outputs Y0, Y1, Y2 & Y3. The block diagram of 1x4 De-Multiplexer is shown in the
following figure.

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Figure 7.2:Block diagram of 1x4 De-multiplexer

Table 7.1:Truth table of 1x4 De-multiplexer

From the above truth table, we can derive the Boolean Expressions for the outputs
as follows:
Y0 = S 1 S 0 D
Y1 = S 1 S0 D
Y2 = S1 S 0 D
Y3 = S1 S0 D
Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.
2. 1x8 De-multiplexer
The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of
single input D, three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
It is also called as 3-to-8 demultiplexer due to its three select input lines and 8 output
lines. It distributes one input line to one of 8 output lines depending on the
combination of select inputs.

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Figure 7.3 :Block diagram of 1x8 De-multiplexer

Table 7.2:Truth table of 1x8 demultiplexer

From the above truth table, we can derive the Boolean Expressions for the outputs
as follows:
Y0 = S 2 S 1 S 0 D
Y1 = S 2 S 1 S0 D
Y2 = S 2 S1 S 0 D
Y3 = S 2 S1 S0 D
Y4 = S2 S 1 S 0 D
Y5 = S2 S 1 S0 D
Y6 = S2 S1 S 0 D
Y7 = S2 S1 S0 D

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Observations –

Result - 1x4 and 1x8 demux has been designed successfully.

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Experiment 8

Aim - Implementation and verification of decoder

Tools Used – Circuitverse, IITR Vlab

Theory –
Introduction
Binary code of N digits can be used to store 2N distinct elements of coded
information. This is what encoders and decoders are used for. Encoders convert
2N lines of input into a code of N bits and Decoders decode the N bits into 2N lines.

1) 2x4 Decoder / De-multiplexer

The name “Decoder” means to translate or decode coded information from one
format into another, so a digital decoder transforms a set of digital input signals into
an equivalent decimal code at its output
A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of m=2^n unique output lines.

Figure 1. Logic Diagram of Decoder

1.1) 2-to-4 Binary Decoder

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Figure 2. Circuit Diagram of 2-to-4 Decoder

The 2-to-4 line binary decoder depicted above consists of an array of four AND
gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs, hence
the description of 2-to-4 binary decoder. Each output represents one of the minterms

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of the 2 input variables, (each output = a minterm).

Figure 3. Logic Diagram and Truth table of 2-to-4 Decoder

The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at
logic level “1” while the remaining outputs are held “LOW” at logic “0” so only one
output can be active (HIGH) at any one time.

Therefore, whichever output line is “HIGH” identifies the binary code present at the
input, in other words it “decodes” the binary input.Some binary decoders have an
additional input pin labelled “Enable” that controls the outputs from the device.

This extra input allows the decoders outputs to be turned “ON” or “OFF” as required.
Output is only generated when the Enable input has value 1; otherwise, all outputs
are 0. Only a small change in the implementation is required: the Enable input is fed
into the AND gates which produce the outputs.
If Enable is 0, all AND gates are supplied with one of the inputs as 0 and hence no
output is produced. When Enable is 1, the AND gates get one of the inputs as 1, and
now the output depends upon the remaining inputs. Hence the output of the decoder
is dependent on whether the Enable is high or low.

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Observations–

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Result – 2x4 and 3x8 demux are implemented successfully

Experiment 9

Aim - To design a 4-bit combinational shifter using logic gates.

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Tools Used – Circuitverse, IITR Vlab

Theory –
 Shift micro-operations are used for serial transfer of data.
 Information transferred through the serial input determines the type of shift.
 There are three types of shift.
 Logical shift
 Circular shift
 Arithmetic shift
4-bit combinational circuit shifter

Figure 9.1:Block diagram of 4-bit combinational shifter

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Table 9.2: Function Table of 4-bit combinational shifter
When the selection inputS = 0, the input data are shifted right (down in the diagram).
When S = 1, the input data are shifted left (up in the diagram).

Observations–

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Result – 4-bit combinational shifter using logic gates has been designed
successfully.

Experiment 10

Aim – To design an ALU

Tools Used – Circuitverse, IITR Vlab

Theory –
In computing, an arithmetic logic unit (ALU) is a digital circuit that performs
arithmetic and logical operations. The ALU is a fundamental building block of the
central processing unit (CPU) of a computer, and even the simplest microprocessors
contain one for purposes such as maintaining timers. The processors found inside
modern CPUs and graphics processing units (GPUs) accommodate very powerful
and very complex ALUs; a single component may contain several ALUs.
Mathematician John von Neumann proposed the ALU concept in 1945.
Below is a block diagram for an ALU:

Observations–

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Result – ALU is designed

Experiment 11

Aim - To design a 4-bit BCD adder

Tools Used – Circuitverse, IITR Vlab

Theory –
 BCD stand for binary coded decimal.
 Suppose we have two 4-bit numbers A and B
 The value of A and B can vary from 0(0000 in binary) to 9 (1001 in binary)
 The output will vary from 0 to 18, the carry from the previous sum is not considered.
 But if the carry is considered, then the maximum value of output will be 19
 When A and B are added, then the binary sum is obtained. Here, to get the output in
BCD form, BCD Adder is used.

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 Truth Table

Observations–

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Result – 4-bit bcd adder is designed

Experiment 12

Aim - To design a 4-bit adder subtractor

Tools Used – Circuitverse, IITR Vlab

Theory –
It is a combinational circuit which can act as both a binary adder and a binary
subtractor. It is constructed using 4 full adders. Block diagram of the circuit is shown
below:
In this case if sub is 0, then the circuit acts as an adder, else subtractor. Subtraction
is done by adding two’s compliment of B to A, which effectively results in A - B.

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Observations–

Result – 4-bit subtractor is designed.

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Yash Jindal A2305220130