Timing Closure

Lecture 3
Jignesh Shah
UCSC Extension, Silicon Valley
Spring 2024
Agenda
• Announcement / Logistics
• Quick review of lecture 2
• Device Manufacturing Variation in STA
• Lab #3 –
Logistics
• Use discussion forum to get help in debugging or to share knowledge
or to ask questions
• Question on Lab1 or Lab 2 or on CCS vs NLDM
Review of lecture 2
• Dynamic simulation versus STA
• STA is exhaustive and fast
• Objective of the timing analysis or closure
• Meet setup and hold time at input port, output ports and at the Data & Reset
inputs of sequential elements such as flip flops, latches, memory, ….
• Introduction to STA
• Ran a basic STA flow on a simple design
• Looked at Library model, design constraint and setup/hold violations
STA Tools
• Primetime from Synopsys, an EDA company
• Tempus from Cadence, an EDA company
• Software from FPGA Vendor like AMD (i.e. Xilinx), Intel (i.e. Altera), Lattice
• openSTA from the Open Road project
• few others..

• For the lab we will use Primetime & openSTA.

Timing arcs in Liberty model of SRAM (Read)

Example of Timing check of SRAM pins for READ operation

Timing arcs in Liberty model of SRAM (Write)

Example of Timing check of SRAM pins for WRITE operation

Delay under variation
• What cause variation?
• Process (i.e. Manufacturing )
• Voltage
• Temperature

• In today’s lecture will focus on Process variation modeling in STA.

Process Variation category
Process variation sources
• Systematic Variation
• Spatial position based variations
• Lithography induced variations
• Etch induced variations
• CMP induced variations
• Layout context dependent variations
• Etc…
Fig 1 Device Variation
• Random Variation
• Random dopant fluctuations
• Interconnect variations
• Oxide thickness variation
• Line Edge Roughness
• Etc…
Fig 2 Interconnect Variation
 Delay under Variation
Distribution for • Variations which cause similar impact
Global variation to all same transistors of a die
categorized as global variation.

• Variations which cause distinct impact

to all same transistors of a die,
categorized as Local variation.

• In STA , global variation is accounted

Distribution for
through Process Corners.
Local variation
• In STA ,local variation is accounted
through margin methods.

SS TT FF
(Mean + 3 or higher sigma) ( Mean ) (Mean - 3 or higher sigma)

* Delay distribution on silicon is not Gaussian. It is long tail or skewed on one side.
 Device variation for STA
• Global Variation
• Die to Die, Wafer to Wafer, Lot to Lot variation

• Foundry provides spice model of extreme corners for variation of transistor parameters

• Delay of Standard cell or IP are modeled at extreme corners through spice simulation.

• STA flow use abstract models of extreme corners for timing analysis to account global variation.

Process Nmos Pmos Cell Delay

Corner Parameter Parameter

SS Slow Slow Nominal + 3 or

higher sigma
TT Typical Typical Nominal

FF Fast Fast Nominal - 3 or

higher sigma

Fig1: Process Corners Fig2: Gaussian Distribution Fig3: Delay with global Variation
 Device variation for STA (contd)
• Local Variation
• Within Die Variation

• Delay of same cells can be different

• STA flow apply worst delay variation for Launch & Capture side of a timing path.

• Margin methods to bound local variations

-> Fixed absolute margin

-> Fixed percentage for launch and capture side. (aka OCV)

-> Variable percentage based on number of logic gate and spatial distance. (aka AOCV, SBOCV)

-> A statistical based on number of logic gate & spatial distance (aka POCV, SOCV)

-> A industry standard format to characterize variation model , Liberty Variation Format (LVF)
Fixed absolute Margin for Local variation
• Frequency margin for setup check
• Over fix for hold check
• Example
• Silicon needs 1GHz operational freq – design to 1.2GHz (close timing to
1.2GHz)
• 20% design margin
• Fix all hold up to +100ps
• Pros – simple and easy approach
• Cons – design (area/power) becomes bigger than necessary
• Tends to over design
• Cuts into profit ($$)
On Chip Variation (i.e. OCV) through derate
• Monte Carlo simulations to determine the % of delay variations for
selected combinational & Sequential cells
• Apply +% delay variation to all cells of Late side of paths. (aka late derate)
• Apply –% delay variation to all cells of Early side of Paths (aka early derate)
• Take variation delay credit for common cell between Launch & Capture
• Improvement over fixed margin methodology
• Less over design leading to smaller area and less power

Cell Delay of each arc is 0.9 ns

• Late derate is +11% (0.9 * 1.11 = 1 ns)
• Early derate is -12% (0.9 *0.88 = 0.8 ns)
• Variation credit for common path
= 1 + 1 – 0.8 –0.8 = 0.4ns

Fig 1 Setup timing path

AOCV, SBOCV
• Paths with less gates have larger variations compared to paths with more gates
• Random variations tends to average out
• Paths with less gates have larger variations compared to paths with more gates
• Some systematic variations increases as physical distance among cells increases
• Applying same fix margin/OCV % to all paths results in over fixing “deep” paths
and/or under fixing “shallow” paths
• Deep and shallow are relative terms used to describe number of gates in logic paths
• A path with three gates (shallow) will have a larger variation then a path with 20 gates (deep)
• This issue addressed by applying different % derate to different levels of logic
• Effectively each gate in a path is a level of logic
• Monte Carlo sims are ran for timing paths to generate derate lookup table for each arc.
POCV, SOCV
• One drawback of the AOCV/SBOCV approach is that not all cells are
characterized
• Even though paths may have the same level of logic but the gates in the path may be
different
• Smaller gates and gates with fewer transistors have high variation
• An inverter with Wn = 1um and Wp = 1um
• If process has DW = 0.1um, variation results in Wn = (0.9, 1.1)um and Wp = (0.9, 1.1)um or
about 10%
• The same inverter with Wn = 10um and Wp = 10um results in a variation that is 1% (9.9, 10.1)
• Complex gates with many more transistors also has less variation as a result
• Simulating all path types and all gate types is not realistic
• With POCV, SOCV method each cell is characterized for variation sensitivity.
• The variation margin then becomes cell specific for a chosen Path sigma.
• Least pessimistic compared to other method.
• It requires more up front work in terms of cell characterization
 Liberty Variation Format (aka LVF)
• POCV characterized rise & fall delay and rise & fall slew components
but it uses the worst % as the single % for the cell
• However, due to P/N differences, rise/fall may have different variation %
• Thus, one single % may lead to over design
• LVF – an extension of the POCV methodology
• Instead of a single % for each cell, the variation % specific to rise delay, fall
delay, rise slew and fall slew will be integrated into the cell’s liberty (.lib) file
• Additional variation tables are added to the .lib file (for each cell)
• Variation for sequential arc (i.e. setup, hold, recovery, removal, etc) is also
characterized.
• This is an accuracy improvement over POCV
• This requires library development support
Variation characterization with LVF
 Interconnect variation for STA
• Resistance & Capacitance of Metal & VIA can be different on silicon than the extracted value due to
• Variation in Metal Height

• Variation Metal Width

• Variation in spacing between wire.

• Variation in dielectric thickness

• Foundry provide extreme interconnect corners to extract R&C of interconnect.

• STA flow uses parasitic netlist (i.e. SPEF) of each corner for timing analysis.

T3
M3 Extraction Corner ΔWidth ΔThickness ΔHeight
H2
Inter-layer dielectric Typical typical typical Typical
T2 M2 C-best min min max
S2 W2
C-worst max max min
H1
RC-best max max max
T1
M1 RC-worst min min min
Inter-metal dielectric
Fig2: Interconnect Corners
Fig1: Drawn Metal layers
Lab #3 –

• Copy all files from /home/jdshah/fall_2024_tc_labs/lab3/*

Thank You
Backup Slide
 Random Dopant Fluctuations (RDF)

Arising from the small number of discrete dopants and their random position in the
channel depletion regions

Realistic discrete dopant distribution in an n-channel

MOSFET with an effective channel length Leff = 30 um and
Weffeffective channel width = 50 nm

⚫ Effect becomes smaller for FinFETs

⚫
Affecting Vth
Source: A Brown et al., IEEE Trans. Nanotechnology .p. 195, 2002 17
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Line Edge Roughness (LER)

Consequence of Lithography Fin LWR affects device performance by

processing changing the average Fin width in the
channel region. Gate LWR induces the
FG and BG mismatch and offset.
fin-width LER
fi
sourc
n Gate ℎ𝑓𝑖𝑛
e
𝐿𝑏𝑔
3 4
substrat
drai
n S Fin D 3 𝑡 4
𝑓𝑖𝑛
e
1 2 2
1 𝐿
𝑓𝑔

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Lithography Induced Variations

Diffusion Flaring

Line edge

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Etch Induced Variations

Contacts

a nm
resisto
r
0.04 a nm
roughness resisto
r

Final size Drown

size

17
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CMP Induced Variations

T var
METAL

Field Oxide
Loss
Dishing Erosion

Oxide

Fine Line Large Line Fine Line Large Line

Fine Space Large Space Large Space Fine Space

17
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Random Dopant Fluctuations

17
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Interconnects Variations

OCV

Interconnec
t

ILD Thickness (𝑚)

Global Local

Metal thickness
Metal width and
spacing
Metal resistivity
Dielectric thickness
Dielectric constant

18
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Metal
Mismatch

Fail
Slow
Q D Q D

CLK
Fast

18
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