III Sem EC Components for Electronic Circuit Design Paper Solution

PRIYADARSHINI BHAGWATI COLLEGE OF ENGINEERING

Department of Electronics & Communication Engineering
CAT-2 Examination (2023-24)
Question Paper Solution
III Semester
Components for Electronic Circuit Design
Subject Code : BEEC302T

Que. 1 (A)
(i) How many junctions are there in BJT?
(a) One (b) Two (c) Three (iv) Four
(ii) Which of the following configuration of BJT has high current and volt-
age gain?
(a) CB Configuration (ii) CE Configuration
(iii) CC Configuration (d) Both CC and CB configuration

Solution :
(i) Option (b) - Two
(ii) Option (b) - CE Configuration

Que. 1 (B)
What is Base Width Modulation? Explain

Solution :

Figure 1: Base width

• As shown in figure 1, the width of the base region occupied by charge par-
ticles is known as electrical witdth or physical width of the base region.
• Since doping in the base is ordinarily substantially smaller than that of the
collector, the penetration of the transition region into the base is much larger
than into the collector. Hence the base depletion region is large.

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Paper Solution Components for Electronic Circuit Design III Sem EC

• Here, when reverse bias voltage VCB increases, the width of the depletion
region in base region also increases, which reduces the electrical base width
(WB′ ).
• Due to reduction of electrical base width, now there are more charge parti-
cles per unit area. In other words, due to reduction of electrical base width,
concentration of the charge gradient increases in the base region. This in-
crease in concentration of charge carriers causes more diffusion of electrons
from n-type emitter to p-type base increasing emitter current slightly.

Figure 2: Change in base and depletion region width with change in reverse bi-
ased voltage

• The increase in reverse bias voltage VCB , the width of depletion region in-
creases, which reduces the electrical base width. This effect is called as
’Early Effect’ or Base width modulation’. This effect can be explained with
the help of equation -
e · NA · W2
V=
2ϵ
where, V = Reverse bias voltage and W = Width of the space charge re-
gion/depletion region.
• As we know, the depletion width is more on the lightly doped region, i.e.
base region, this effect is more in the base region reducing the effective (elec-
trical) base width.
• This decrease in base width has two consequences :

1. There is less chance for recombination within the base region. Hence
the transport factor β and also α, increase with an increase in the mag-
nitude of the collector junction voltage.
2. The charge gradient is increased within the base and consequently, the
current of minority carriers injected across the junction increases.

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III Sem EC Components for Electronic Circuit Design Paper Solution

Que. 2 (A)
(i) Which of the following is the function of transistor?
(a) Rectifier (b) Amplifier
(c) Voltage Regulator (d) Clamper
(ii) BJT is ............device
(a) Voltage controlled device (b) Current controlled device
(c) Very high input impedance device (d) None of above

Solution :
(i) Option (b) - Amplifier
(ii) Option (b) - Current controlled device

Que. 2 (B)
What is biasing of transistor? Explain any one biasing technique in detail.

Solution : In order to operate transistor properly as an amplifier, it is necessary

to correctly bias the two P-N junctions with external voltages. Depending upon
external bias voltage polarities used, the transistor works in one of the three re-
gions, viz

1. Active Region
2. Cut-off Region
3. Saturation Region

Region Emitter-Base Junction Collector-Base Junction

Active Forward Biased Reverse Biased
Cut-off Reversed Biased Reverse Biased
Saturation Forward Biased Forward Biased
To bias the transistor in its active region, the emitter base junction is forward
biased while the collector-base junction is reverse biased as shown in fig 3

Figure 3: NPN and PNP transistor in Active region

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Paper Solution Components for Electronic Circuit Design III Sem EC

The externally applied bias voltages are VEE and VCC , as shown in fig 3 which
bias the transistor in its active region. The operation of the PNP transistor is the
same as for the NPN except that the roles of the electrons and holes, the bias
voltage polarities and the current directions are reversed. Note that in both cases
the base-emitter (JE ) junction is forward biased and the collector-base junction
(JC ) is reversed biased.
To operate transistor in a particular region of operation, we need to apply the d.c.
voltage across the two junctions of a transistor , which is called as biasing.
The different types of biasing circuits that are used for transistors are :

1. Fixed Bias Circuit

2. Collector to Base Bias Circuit
3. Voltage Divider Bias Circuit

Fixed Bias Circuit

Figure 4 shows the fixed bias circuit. Applying Kirchoff’s voltage law to the base
circuit, we get,

VCC – IB RB – VBE = 0 (1)

∴ IB RB = VCC – VBE (2)
V – VBE
∴ IB = CC (3)
R

As VBE ≪ VCC , we get,

VCC
IB ≈ (4)
RB

Figure 4: Fixed Bias Circuit

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III Sem EC Components for Electronic Circuit Design Paper Solution

The supply voltage VCC is of fixed value. Once the resistance RB is selected, IB is
also fixed. Hence this circuit is called fixed bias circuit.
Applying Kirchoff’s voltage law to the collector circuit, we get,

VCC – IC RC – VCE = 0 (5)

∴ VCE = VCC – IC RC (6)

The collector current in CE configuration is given as ,

IC = βIB + ICEO ≈ βIB (7)

Since βIB ≫ ICEO

∴ VCC = IC RC + VCE (8)

V – VCE
∴ IC = CC (9)
RC

i.e. supply voltage provides the voltage across RC and the collector to emitter
voltage. Therefore voltage drop across RC can never be more than VCC .

∴ IC RC < VCC (10)

V
∴ IC < CC (11)
RC

If IC becomes greater than the value limited by above expression, the operating
point will lie in the saturation region of the characteristics.

Que. 3 (A)
(i) The current in n-channel JFET flows due to ..........
(a) Electrons (b) Holes (c) Electrons and Holes both
(ii) The gate voltage in JFET at which the drain current becomes zero is
called.......
(a) Saturation voltage (b) Pinch-off Voltage
(c) Active voltage (d) Cut-off Voltage

Solution :
(i) Option (a) - Electrons
(ii) Option (d) - Cut-off Voltage

Que. 3 (B)
List the difference between BJT and JFET.

Solution :

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Paper Solution Components for Electronic Circuit Design III Sem EC

Comparison of BJT and FET

S.N. Parameter BJT FET

1 Control Ele- Current Controlled device. Voltage controlled device.
ment Input current IB controls out- Input voltage VGS controls
put current IC drain current ID .
2 Device Type Current flows due to both, Current flows only due to
majority and minority carri- majority carriers and hence
ers and hence bipolar device. unipolar device.
3 Types NPN and PNP type N-channel and P-channel
4 Configurations CB, CE and CC CS,CG and CD
5 Input resistance Less as compared to JFET High as compared to BJT
6 Size Bigger than JFET Smaller in construction than
BJT thus making them useful
in integrated circuits (ICs)
7 Sensitivity Higher sensitivity to changes Less sensitivity to changes in
in the applied signals the applied voltage.
8 Thermal Stabil- Less More
ity
9 Thermal Run- Exist in BJT, because of cumu- Does not exists in JFET,
away lative effect of increase in IC because drain resistance rd
with temperture resulting in increases with temperature
increase in temperature of de- which reduces ID , reduc-
vice. ing the ID and hence the
temperture of the device.
10 Relationship Linear Non-linear
between input
and output
11 Thermal Noise More in BJT as more charge Much lower in JFET as very
carriers cross junctions few charge carriers cross the
junction.
12 Gain Band- High Low
width Product

Que. 3 (C)
Draw and explain the Drain & Transfer characteristics of JFET.

Solution : To understand electrical behavior of a JFET, it is necessary to study the

interrelation of the current and voltage in JFET. These relationships can be plotted
graphically which are commonly known as the characteristics of JFET.
The important characteristics of JFET are drain characteristics and transfer char-
acteristics.

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III Sem EC Components for Electronic Circuit Design Paper Solution

Drain characteristics of N-channel JFET

Figure 5: Drain V-I characteristics of n-channel JFET

Figure 6: Experimental Setup to plot JFET characteristics

• Figure 5 shows the drain characteristics of a n-channel JFET. The curves rep-
resent relationship between the drain current ID and drain to source voltage
VDS for different values of VGS . Figure 6 shows the experimental setup re-
qudired to plot this characteristics.
• VGS and VDS both = 0 : when VGS = 0 the channel is entirely open. But
VDS = 0, so there is no attractive force for the majority carriers (electrons in
n-channel JFET) and hence drain current does not flow.
• Self pinch-off at no bias (VGS = 0) : As VGS = 0, in response to a small
applied voltage VDS , the n-type bar acts as a simple semiconductor resis-
tor, and the current ID increasaes linearly with VDS . As VDS increases, the
voltage drop along the channel also increases. This increase in voltage drop
increases the reverse bias on gate-source junction and causes the depletion
region to penetrate into the channel, reducing channel width. The effect of
reduction in channel width provides more opposition to increase in drain
current ID . Thus rate of increase in ID with respect to VDS is now reduced.
this is shown by the curved shape in the characteristics.
• At som value of VDS , drain current ID cannot be increased further, due to
reduction in channel width. Any further increase in VDS does not increase

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Paper Solution Components for Electronic Circuit Design III Sem EC

the drain current ID . ID approaches the constant saturation value. The volt-
age VDS at which the current ID reaches to its constant saturation level is
called ’Pinch-off Voltage’ Vp .
• VGS with negative bias : When an external bias of say -1 V, is applied be-
tween the gate and the source, the gate channel junctions are further re-
versed biased, reducing the effective width of the channel available for the
conduction. Because of this, drain current will reduce and pinch off voltage
is reached at a lower drain current than when VGS = 0 as shown in figure 5.
• By applying several values of negative external bias voltage VGS , a family
of curves are obtained as shown in figure 5. From figure it can be observed
that for more negative values of VGS , the pinch-off voltage is reached at
lesser values of ID .
• Breakdown region : WE can observe from the figure 5 that if we increase
value of VDS beyond pinch off voltage Vp , the drain current ID remains
constant, upto certain value of VDS . IF we further exceed VDS , the voltage
will be reached at which the gate-channel junction breaks down, due to
avalanche effect. At this point the drain current increases rapidly, and the
device may be destroyed.
• It can be observed that the values of VDS for breakdown are reduced as the
negative gate bias is increased. this is because the total reverse breakdown
voltage is the addition of the reverse voltage due to self pinch-off and the
externally applied voltage VGS .
• Ohmic and saturation regions : It is seen that the drain characteristics of
JFET is divided into two regions :ohm,ic region and saturation region. In
the ohmic region, the drain current ID varies with VDS and the JFET is said
to behave as voltage variable resistance. In the saturation region, the drain
current ID remains fairly constant and does not vary with VDS .
• Cut-off : As we know, for an n-channel JFET, the more negative VGS causes
drain current to reduce and pinch-off voltage to reach at a lower drain cur-
rent. When VGS is made sufficiently negative, ID is reduced to 0. as shown
in figure 5. This is caused by the widening of the depletion region to a point
where it completely closes the channel. The value of VGS at the cut-off point
is designated as VGS(off) .

Transfer characteristics of n-channel JFET

• The relationship between the drain current ID and gate to source voltage
VGS is non-linear as shown in the figure 7. This relationship is defined by
Schockley’s equation.
VGS 2
 
ID = IDSS 1 –
VP

• The squared term of the equation will result in a non-linear relationship

between ID and VGS , producing a cure that grows exponentially with de-

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III Sem EC Components for Electronic Circuit Design Paper Solution

creasing magnitudes of VGS . From equation we can also write,

s !
ID
VGS = VP 1 –
IDSS

• In the equation values of IDSS and VP are constants, value of VGS controls
ID .

• A point A at the bottom end of the curve on the VGS axis represents VGS(off)
and point B at the top end of the curve on the ID axis represents IDSS .

Figure 7: Transfer characteristics of n-channel JFET

Que. 4 (A)
(i) JFET is an ........... device.
(a) Tripolar (b) Antipolar (c) Unipolar (d) Bipolar
(ii) Which type of device is JFET?
(a) Voltage controlled (b) Current Ccontrolled
(c) Resistance controlled (d) Conductance controlled

Solution :
(i) Option (c) - Unipolar
(ii) Option (a) -Voltage controlled

Que. 4 (B)
Explain the working of n-channel JFET with neat diagram.

Solution :

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Paper Solution Components for Electronic Circuit Design III Sem EC

0.1 Working of n-channel JFET

In the absence of any applied voltage, JFET has gate channel junction under no
bias conditions. The result is a depletion region at each junction as shown in fig-
ure 8. This represents same depletion region of a diode under no bias conditions.
The depletion region does not enable to support conduction through the region.

Figure 8: n-channel JFET structure

In JFET, the p-n junction between gate and source is always kept in reverse biased
conditions. Since the current in a reversed biased p-n junction is extremely small,
practically zero; the gate current in JFET is often neglected and assumed to be
zero.

Figure 9: Effect of gate voltage on channel width

Let us consider the circuit shown in figure 9. Voltage VDD is applied between
drain and source. Gate terminal is kept open. The bar is of n-type material. Due
to the polarities of applied voltage as shown in figure 9, the majority carriers i.e.
electrons start flowing from the source to the drain. This flow of electrons make
the drain current ID .
The majority carriers (Electrons in n-channel JFET and holes in p-channel JFET)
move from source to drain through the space between the gate regions. This space
is commonly known as channel. The width of this channel can be controlled by

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III Sem EC Components for Electronic Circuit Design Paper Solution

varying the gate voltage. The effect of gate voltage on channel width and on drain
current ID is shown in figure 10 .

Figure 10: Effect of different gate voltages on depletion region width

Figure 10(a) shows that an n-channel JFET with the gate directly connected to the
source terminal. When drain voltage VDS is applied, a drain current ID flows in
the direction shown. Since the n-material is resistive, the drain current causes a
voltage drop along the channel. This voltage drop reverse biases the p-n junctions
and causes the depletion regions to penetrate into the channel. Since the gate is
heavily doped and the channel is lightly doped, the width of the depletion region
will mainly be spread in the channel shown in figure 10(a). This penetration de-
pends on the reverse bias voltage. From figure 10(b), we observe that depletion
region width is more at the drain side as compared to source side near the junc-
tion, voltage at the drain side is more than the voltage at the source side. This
shows that reverse bias is not uniform near the junction; it gradually increases
from source side to drain side.
The depletion region does not contain charge carriers, the space between two
depletion regions is available for the conducting portion of the channel. If we
externally apply reverse bais voltge to teh gate, the reverse bias will further in-
creases and hence increase the penetration of the depletion region, which reduces
the width of the conducting portion of the channel. As width of the conducting
portion of the channel reduces, the number of electrons flowing from source to
drain reduces and hence the current flowing from drain to source reduces. If
we go on increasing the reverse bias voltage to the gate as shown in figure 10(b)
and (c), depletion region will increase more and more, and stage will come when
the width of the depletion region will be equal to the original width of the chan-
nel, leaving zero width for conducting portion of the channel, as shown in figure
10(c). This will prevent any current flow from drain to source and this will cut-off
the drain current. The gate to source voltage that produces cut-off is known as
cut-off voltage and it is denoted by VGS(off) .
When the gate is shorted to source, there is minimum reverse bias between gate
and source p-n junction, making depletion width minimum and conducting chan-
nel width maximum. In this case maximum drain current flows which is desig-
nated by IDSS and this is the maximum possible drain current in JFET. It is clear

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Paper Solution Components for Electronic Circuit Design III Sem EC

that the gate to source voltage controls the current flowing through channel and
hence FETs is also called voltage controlled current source.

Que. 4 (C)
For JFET, prove that the transconductance gm is given by -
 
VGS
gm = gmo 1 –
VP

–2IDSS
where, gmo = .
VP

Solution : The transconductance, gm is the change in the drain current for given
change in gate to source voltage with the drain to source voltage constant.

△ ID
i.e. gm = at VDS constant (12)
△VGS
The transconductance gm is also called mutual conductance. The unit for gm is
mS (milli-siemens) or mA/V.
The gm can be calculated at any point on the transfer characteristics curve using
the following equations :
" #
VGS
gm = gmo 1 – (13)
VGS(off)

where, gmo is the value of gm for VGS = 0 and is given by -

–2IDSS
gmo = (14)
Vp

This can be proved as below.

We know that,
VGS 2
 
ID = IDSS 1 – (15)
Vp
Differentiating this equation with respect to VGS we get,

△ ID
 
–2IDSS VGS
gm = = 1– (16)
△VGS Vp Vp
 
V
∴ gm = gmo 1 – GS (17)
Vp

Where, gmo = –2IVDSS

p

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III Sem EC Components for Electronic Circuit Design Paper Solution

Que. 5 (A)
(i) Which insulating layer used in Fabrication of MOSFET?
(a) Aluminium oxide (b) Silicon Nitride
(c) Silicon dioxide (d ) Germanium oxide
(ii) Which component can not be fabricated on an IC ?
(a) Resistor (b) Capacitor (c) Inductor (d) Diode

Solution :
(i) Option (c) - Silicon dioxide
(ii) Option (c) - Inductor

Que. 5 (B)
Explain the process of Fabrication of IC in detail.

Solution : The fabrication of a monolithic transistor includes the following steps:

1. Epitaxial growth
2. Oxidation
3. Photolithography
4. Diffusion
(a) i. Isolation diffusion
(b) Base diffusion
(c) Emitter diffusion
5. Ion implantation
6. Isolation Technique
7. Contact mask
8. Aluminium metallization
9. Passivation

Note : The letters P and N in the figures refer to type of doping, and a minus (-)
or plus (+) with P and N indicates lighter or heavier doping respectively

Epitaxial Growth
1. Epitaxy means growing a single crystal silicon structure upon an original
silicon substrate, so that the resulting layer is an extension of the substrate
crystal structure.
2. The basic chemical reaction in the epitaxial growth process of pure silicon
is the hydrogen reduction of silicon tetrachloride.

SiCl4 + 2H2 ¸ßSi + 4HCl

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Paper Solution Components for Electronic Circuit Design III Sem EC

Figure 11:

3. The first step in transistor fabrication is creation of the collector region.

4. It normally requires a low resistivity path for the collector current.
5. This is due to the fact that, the collector contact is normally taken at the top,
thus increasing the collector series resistance and the VCE(Sat) of the device.
6. Thehigher collector resistance is reduced by a process called buried layer as
shown in figure 11
7. In this arrangement, a heavily doped N region is sandwiched between the
N-type epitaxial layer and P– type substrate.
8. This buried N+ layer provides a low resistance path in the active collector
region to the collector contact C.
9. In effect, the buried layer provides a low resistance shunt path for the flow
of current.
10. For fabricating an NPN transistor, we begin with a P-type silicon substrate
having a resistivity of typically 1 Ω – cm, corresponding to an acceptor ion
concentration of 1.4 × 1015 atoms/cm3 .
11. An oxide mask with the necessary pattern for buried layer diffusion is pre-
pared.
12. This is followed by masking and etching the oxide in the buried layer mask.
13. The N-type buried layer is now diffused into the substrate.
14. A slow-diffusing material such as arsenic or antimony is used, so that the
buried layer will stay-put during subsequent diffusions.
15. The junction depth is typically a few microns, with sheet resistivity of around
20 Ω per square.
16. Then, an epitaxial layer of lightly doped N-silicon is grown on the P-type
substrate by placing the wafer in the furnace at 1200o C and introducing a
gas containing phosphorus (donor impurity).
17. The subsequent diffusions are done in this epitaxial layer.
18. All active and passive components are formed on the thin N-layer epitaxial
layer grown over the P-type substrate.

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III Sem EC Components for Electronic Circuit Design Paper Solution

2. Oxidation
1. The process of oxidation consists of growing a thin film of silicon dioxide
on the surface of the silicon wafer at 1000o C.

Si + 2HO → SiO2 + 2H2

2. Silicon dioxide plays an important role in shielding of the surface so that

dopant atoms, by diffusion or ion implantation, may be driven into other
selected regions.
3. SiO2 is an extremely hard protective coating & is unaffected by almost all
reagents except by hydrochloric acid. Thus it stands against any contami-
nation.

Figure 12:

3. Photolithography
1. The prime use of photolithography in IC manufacturing is to selectively
etch or remove the SiO2 layer.
2. As shown in figure, the surface of the oxide is first covered with a thin uni-
form layer of photosensitive emulsion (Photo resist).
3. The mask, a black and white negative of the required pattern, is placed over
the structure.
4. When exposed to ultraviolet light, the photo resist under the transparent
region of the mask becomes polymerized.
5. The mask is then removed and the wafer is treated chemically that removes
the unexposed portions of the photo resist film.
6. The polymerized region is cured so that it becomes resistant to corrosion.
7. Then the chip is dipped in an etching solution of hydrofluoric acid which
removes the oxide layer not protected by the polymerized photoresist.
8. This creates openings in the SiO2 layer through which P-type or N-type
impurities can be diffused using the isolation diffusion process as shown in
figure.

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Paper Solution Components for Electronic Circuit Design III Sem EC

Figure 13:

9. After diffusion of impurities, the polymerized photoresist is removed with

sulphuric acid and by a mechanical abrasion process.

4. Diffusion

Isolation Diffusion
1. The integrated circuit contains many devices.
2. Since a number of devices are to be fabricated on the same IC chip, it be-
comes necessary to provide good isolation between various components
and their interconnections.
3. The most important techniques for isolation are:
(a) PN junction Isolation
(b) Dielectric Isolation
4. In PN junction isolation technique, the P+ type impurities are selectively
diffused into the N-type epitaxial layer so that it touches the P-type sub-
strate at the bottom.
5. This method generated N-type isolation regions surrounded by P type moats.
6. If the P-substrate is held at the most negative potential, the diodes will be-
come reverse-biased, thus providing isolation between these islands.
7. The individual components are fabricated inside these islands.
8. This method is very economical, and is the most commonly used isolation
method for general purpose integrated circuits.
9. In dielectric isolation method, a layer of solid dielectric such as silicon diox-
ide or ruby surrounds each component and this dielectric provides isola-
tion.
10. The isolation is both physical and electrical.
11. This method is very expensive due to additional processing steps needed
and this is mostly used for fabricating IC‘s required for special application

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III Sem EC Components for Electronic Circuit Design Paper Solution

in military and aerospace.

12. The PNjunction isolation diffusion method is shown in figure. The process
takes place in a furnace using boron source.
13. The diffusion depth must be at least equal to the epitaxial thickness in order
to obtain complete isolation.
14. Poor isolation results in device failures as all transistors might get shorted
together.
15. The N-type island shown in figure forms the collector region of the NPN
transistor.
16. The heavily doped P-type regions marked P+ are the isolation regions for
the active and passive components that will be formed in the various N-
type islands of the epitaxial layer.

Base Diffusion

1. Formation of the base is a critical step in the construction of a bipolar tran-

sistor.
2. The base must be aligned, so that, during diffusion, it does not come into
contact with either the isolation region or the buried layer.
3. Frequently, the base diffusion step is also used in parallel to fabricate dif-
fused resistors for the circuit.
4. The value of these resistors depends on the diffusion conditions and the
width of the opening made during etching.
5. The base width influences the transistor parameters very strongly. There-
fore, the base junction depth and resistivity must be tightly controlled.
6. The base sheet resistivity should be fairly high (200- 500 Ω per square) so
that the base does not inject carriers into the emitter.
7. For NPN transistor, the base is diffused in a furnace using a boron source.
8. The diffusion process is done in two steps, pre-deposition of dopants at
900o C and driving them in at about 1200o C.
9. The drive-in is done in an oxidizing ambience, so that oxide is grown over
the base region for subsequent fabrication steps.
10. Figure shows that P-type base region of the transistor diffused in the N-type
island (collector region) using photolithography and isolation diffusion pro-
cesses.

Emitter Diffusion

1. Emitter Diffusion is the final step in the fabrication of the transistor.

2. The emitter opening must lie wholly within the base.
3. Emitter masking not only opens windows for the emitter, but also for the
contact point, which provides a low resistivity ohmic contact path for the
emitter terminal.
4. The emitter diffusion is normally a heavy N-type diffusion, producing low-
resistivity layer that can inject charge easily into the base.

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Paper Solution Components for Electronic Circuit Design III Sem EC

5. A Phosphorus source is commonly used so that the diffusion time id short-

ened and the previous layers do not diffuse further.
6. The emitter is diffused into the base, so that the emitter junction depth very
closely approaches the base junction depth.
7. The active base is then a P-region between these two junctions which can be
made very narrow by adjusting the emitter diffusion time.
8. Various diffusion and drive in cycles can be used to fabricate the emitter.
The Resistivity of the emitter is usually not too critical.
9. The N-type emitter region of the transistor diffused into the P-type base
region is shown below.
10. However, this is not needed to fabricate a resistor where the resistivity of
the P-type base region itself will serve the purpose.
11. In this way, an NPN transistor and a resistor are fabricated simultaneously.

5. Ion Implantation

Figure 14: Ion Implantation

1. It is another technique to introduce impurities into a silicon wafer.

2. In this process silicon wafer are placed in a vacuum chamber, and are scanned
by a beam of high energy ions. (boron for p- type, phosphorus for n- type)
3. These ions are accelerated by energies between 20 kV to 259 kV.
4. These ions strike the silicon wafers, they penetrate some distance into wafer.
5. The depth of any penetration of any particular type of ion increasing accel-
erating voltage.
6. It is performed at low temperature. Therefore, previously diffused regions
have a lesser tendency for lateral spreading.
7. In diffusion process, temperature has to be controlled over a large area in-
side the oven, where as in ion implantation process, accelerating potential
& beam content are dielectrically controlled from outside.

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III Sem EC Components for Electronic Circuit Design Paper Solution

Advantages of Ion Implantation

• Doping levels can be precisely controlled since the incident ion beam can be
accurately measured as an electric current.
• The depth of the dopant can be easily regulated by control of the incident
ion velocity. It is capable of very shallow penetrations.
• Extreme purity of the dopant is guaranteed.
• The doping uniformity across the surface can be accurately controlled.
• Because the ions enter the solid as a directed beam, there is very little spread
of the beam, thus the doping area can be clearly defined.
• Since this is a low-temperature process, the movement of impurities is min-
imized.

6. Isolation Techniques

P-N Junction Isolation

1. Consider a p-substrate with n-type epitaxial layer grown over it.
2. To provide isolation, a p-type impurity with high concentration is diffused
selectively into an epitaxial layer such that it reaches to the p-substrate as
shown below.

Figure 15:

3. From the fig. it is clear that n-epitaxial region forms a region which is sur-
rounded by p-type regions. This region is called island.
4. Two regions are connected back-to-back and these two back-to back diodes
serve as isolation regions if both are reverse biased.
5. The main advantage of p-n junction isolation is that different components
can be fabricated within the isolation islands.
6. But the disadvantage is the presence of undesirable and unavoidable para-
sitic capacitances at the islands.

Dielectric Isolation
1. In dielectric isolation, a layer of solid dielectric such as SiO2 or ruby com-
pletely surrounds each components thereby producing isolation, both elec-

L: Dr. P.R. Bokde 19 PBCOE, Nagpur

Paper Solution Components for Electronic Circuit Design III Sem EC

trical & physical.

2. This isolating dielectric layer is thick enough so that its associated capaci-
tance is negligible.
3. Also, it is possible to fabricate both pnp & npn transistors within the same
silicon substrate which is the main advantage of this technique.
4. But the disadvantage is the increase in cost. As the technique requires ad-
ditional steps in fabrication to deposit a dielectric layer, this technique is
expensive.

7. Contact Mask
1. After the fabrication of emitter, windows are etched into the N-type regions
where contacts are to be made for collector and emitter terminals.
2. Heavily concentrated phosphorus N+ dopant is diffused into these regions
simultaneously.
3. Thereason for the use of heavy N+diffusion is explained as follows:

(a) Aluminium, being a good conductor used for interconnection, is a P-

type of impurity when used with silicon.

(b) Therefore, it can produce an unwanted diode or rectifying contact with

the lightly doped N- material.

(c) Introducing a high concentration of N+ dopant caused the Si lattice at

the surface semi- metallic.

(d) Thus the N+ layer makes a very good ohmic contact with the Alu-
minium layer. This is done by the oxidation, photolithography and
isolation diffusion processes.

8. Metallization
1. The IC chip is now complete with the active and passive devices, and the
metal leads are to be formed for making connections with the terminals of
the devices.
2. Aluminium is deposited over the entire wafer by vacuum deposition. The
thickness for single layer metal is 1 µm.
3. Metallization is carried out by evaporating aluminium over the entire sur-
face and then selectively etching away aluminium to leave behind the de-
sired interconnection and bonding pads as shown in figure.
4. Metallization is done for making interconnection between the various com-
ponents fabricated in an IC and providing bonding pads around the cir-
cumference of the IC chip for later connection of wires.

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III Sem EC Components for Electronic Circuit Design Paper Solution

Figure 16: Metallization

9. Passivation / Assembly and Packaging

1. Metallization is followed by passivation, in which an insulating and protec-

tive layer is deposited over the whole device.
2. This protects it against mechanical and chemical damage during subse-
quent processing steps.
3. Doped or un doped silicon oxide or silicon nitride, or some combination of
them, are usually chosen for passivation of layers.
4. The layer is deposited by chemical vapour deposition (CVD) technique at a
temperature low enough not to harm the metallization.

Que. 6(A)
(i) Which of the following is most difficult to fabricate on an IC?
(a) Diode (b) Transistor (c) FET (d) Capacitor
(ii)ICs are generally made of ..........
(a) Silicon (b) Germanium (c) Copper (d) None of given

Solution :
(i) Option (d) - Capacitor
(ii) Option (a) - Silicon

Que. 6 (B)
Write a short note on ’Photolithography’ and ’Oxidation’ in relation to fab-
rication of IC.

Solution :

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Paper Solution Components for Electronic Circuit Design III Sem EC

2. Photolithography
1. The prime use of photolithography in IC manufacturing is to selectively
etch or remove the SiO2 layer.
2. As shown in figure, the surface of the oxide is first covered with a thin uni-
form layer of photosensitive emulsion (Photo resist).
3. The mask, a black and white negative of the required pattern, is placed over
the structure.
4. When exposed to ultraviolet light, the photo resist under the transparent
region of the mask becomes polymerized.
5. The mask is then removed and the wafer is treated chemically that removes
the unexposed portions of the photo resist film.
6. The polymerized region is cured so that it becomes resistant to corrosion.
7. Then the chip is dipped in an etching solution of hydrofluoric acid which
removes the oxide layer not protected by the polymerized photoresist.
8. This creates openings in the SiO2 layer through which P-type or N-type
impurities can be diffused using the isolation diffusion process as shown in
figure.
9. After diffusion of impurities, the polymerized photoresist is removed with
sulphuric acid and by a mechanical abrasion process.

Figure 17:

Oxidation
1. The process of oxidation consists of growing a thin film of silicon dioxide
on the surface of the silicon wafer at 1000o C.

Si + 2HO → SiO2 + 2H2

2. Silicon dioxide plays an important role in shielding of the surface so that

dopant atoms, by diffusion or ion implantation, may be driven into other
selected regions.

PBCOE, Nagpur 22 L: Dr. P.R. Bokde

III Sem EC Components for Electronic Circuit Design Paper Solution

3. SiO2 is an extremely hard protective coating & is unaffected by almost all

reagents except by hydrochloric acid. Thus it stands against any contami-
nation.

Figure 18:

Que. 6 (C)
Explain in detail the process of fabrication of Resistor.

Solution : The fabrication of resistors involves several stages, including wafer

preparation, oxidation, diffusion, photolithography, etching, metallization, and
possibly ion implantation, depending on the type of resistor and the desired char-
acteristics.

1. Wafer Preparation:
(a) Starting Material:
The fabrication begins with a silicon wafer, which is the foundation for
the resistor and other components.
(b) Cleaning and Polishing:
The wafer undergoes rigorous cleaning and polishing to ensure a smooth
and defect-free surface.
2. Oxidation:

Figure 19:

Here’s a more detailed breakdown of the process:

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Paper Solution Components for Electronic Circuit Design III Sem EC

(a) Creating Insulating Layers:

A thin layer of silicon dioxide (SiO2) is grown on the wafer surface
through oxidation, which serves as an insulating layer.
(b) Controlling Thickness:
The thickness of the oxide layer is precisely controlled, as it plays a
crucial role in the performance of the resistor.

3. Diffusion and Ion Implantation (for doped resistors):

(a) Introducing Impurities:
Impurities (e.g., phosphorus for n-type doping, boron for p-type dop-
ing) are introduced into the silicon wafer to create regions with specific
electrical properties.
(b) Diffusion:
Impurities can be introduced through diffusion, where atoms are al-
lowed to move into the silicon lattice at high temperatures.
(c) Ion Implantation:
Alternatively, impurities can be implanted into the silicon lattice using
high-energy ions, providing precise control over the doping profile.
4. Photolithography and Etching:
(a) Patterning:
Photolithography is used to create patterns on the wafer’s surface,
defining the areas where the resistor and other components will be
formed.
(b) Photoresist Coating:
A photosensitive material (photoresist) is applied to the wafer, and
then exposed to ultraviolet (UV) light through a mask.
(c) Etching:
The exposed areas of the photoresist are removed, and then the under-
lying material (e.g., silicon dioxide, silicon, or metal) is etched away,
creating the desired patterns.
5. Metallization:
(a) Connecting Resistors:
Metal layers are deposited on the wafer surface to create electrical con-
nections to the resistor and other components.
(b) Thin Film Deposition:
Thin films of metals (e.g., aluminum, copper) are deposited using tech-
niques like sputtering or chemical vapor deposition.
(c) Patterning and Etching (again):
Photolithography and etching are used to pattern the metal layers, cre-
ating the desired interconnects and contact pads.
6. Thin Film Resistor Fabrication:
(a) Metal Film Deposition: Thin-film resistors are fabricated by deposit-
ing a thin layer of a resistive material (e.g., tantalum nitride, titanium-
tungsten) on an insulating substrate.

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III Sem EC Components for Electronic Circuit Design Paper Solution

(b) Patterning:
The metal film is patterned using photolithography and etching to cre-
ate the desired resistor geometry.
Advantages: Thin-film resistors offer high precision, stability, and tol-
erance, making them suitable for applications requiring high accuracy.
7. Thick Film Resistor Fabrication:
• Conductive Paste: Thick-film resistors are fabricated by screen-printing
or painting a conductive paste (containing metal powders or metal ox-
ides) onto a ceramic substrate.
• Firing: The paste is then fired at high temperatures to form a conduc-
tive layer.
• Trimming: The resistance value can be adjusted by laser trimming or
other techniques.
8. Packaging:
(a) Final Assembly: The fabricated resistors, along with other compo-
nents, are packaged to form a functional circuit.
(b) Mounting: The components are mounted on a substrate or header us-
ing solder, adhesive, or chip bonding techniques.
(c) Electrical Connections: Electrical connections are made using wire
bonding or other techniques.

L: Dr. P.R. Bokde 25 PBCOE, Nagpur