Experiment 1: Introduction to the design rules and specification of layout.
Objective:
1. To be familiar with tool.
2. To learn about λ (Lambda) Rules for 90 nm Technology.
Microwind Getting Started:
The present experiment is a guide to using the « Microwind » educational software on a PC
computer.
The MICROWIND program allows the student to design and simulate an integrated circuit. The
package itself contains a library of common logic and analog ICs to view and simulate.
MICROWIND includes all the commands for a mask editor as well as new original tools never
gathered before in a single module. You can gain access to Circuit Simulation by pressing one
single key. The electric extraction of your circuit is automatically performed and the analog
simulator produces voltage and current curves immediately.
A specific command displays the characteristics of pMOS and nMOS, where the size of the device
and the process parameters can be very easily changed. Altering the MOS model parameters and,
then, seeing the effects on the Vds and Ids curves constitutes a good interactive tutorial on devices.
The Process Simulator shows the layout in a vertical perspective, as when fabrication has been
completed. This feature is a significant aid to supplement the descriptions of fabrication found in
most textbooks.
The Logic Cell Compiler is a particularly sophisticated tool enabling the automatic design of a
CMOS circuit corresponding to your logic description in VERILOG. The DSCH software, which
is a user-friendly schematic editor and a logic simulator presented in a companion manual, is used
to generate this Verilog description. The cell is created in compliance with the environment, design
rules and fabrication specifications.
A set of CMOS processes ranging from 1.2µm down to state-of-the-art 0.25µm are proposed.
To use the MICROWIND program use the following procedure:
Go to the directory in which the software has been copied
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(The default directory is MICROWIND)
Double-click on the MicroWind icon
The MICROWIND display window is shown in Figure 1. It includes four main windows: the main
menu, the layout display window, the icon menu and the layer palette. The cursor appears in the
middle of the layout window and is controlled by using the mouse.
The layout window features a grid that represents the current scale of the drawing, scaled in lambda
() units and in micron.
The lambda unit is fixed to half of the minimum available lithography of the technology. The
default technology is a 0.8 µm technology, consequently lambda is 0.4 µm.
Fig. 1. The MICROWIND window as it appears at the initialization stage..
The MOS device
The MOS symbols are reported below. The n-channel MOS is built using polysilicon as the gate
material and N+ diffusion to build the source and drain. The p-channel MOS is built using
polysilicon as the gate material and P+ diffusion to build the source and drain.
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nMOS pMOS
Manual Design
By using the following procedure, you can create a manual design of the n-channel MOS. The
default icon is the drawing icon shown above. It permits box editing. The display window is empty.
The palette is located in the lower right corner of the screen. A red color indicates the current layer.
Initially the selected layer in the palette is polysilicon. The two first steps are illustrated in Figure
2.
Fix the first corner of the box with the mouse.
While keeping the mouse button pressed, move the mouse to the
opposite corner of the box.
Release the button. This creates a box in polysilicon layer as shown in Figure 2.
The box width should not be inferior to 2 , which is the minimum width of the
polysilicon box.
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Fig. 2. Creating a polysilicon box.
Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button.
Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the
drawing as in Figure 3. N-diffusion boxes are represented in green. The intersection between
diffusion and polysilicon creates the channel of the nMOS device.
Fig. 3. Creating the N-channel MOS transistor
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Process Simulation
Click on this icon to access process simulation. The cross-section is given by a click of the mouse
at the first point and the release of the mouse at the second point. In the example below (Figure 4),
three nodes appear in the cross-section of the n-channel MOS device: the gate (red), the left
diffusion called source (green) and the right diffusion called drain (green), over a substrate (gray).
The gate is isolated by a thin oxide called the gate oxide. Various steps of oxidation have lead to
a thick oxide on the top of the gate.
Fig. 4. The cross-section of the nMOS devices.
The physical properties of the source and of the drain are exactly the same. Theoretically, the
source is the origin of channel impurities. In the case of this nMOS device, the channel impurities
are the electrons. Therefore, the source is the diffusion area with the lowest voltage.
The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the source and
the drain. The gate controls the current flow from the drain to the source, both ways. A high voltage
on the gate attracts electrons below the gate, creates an electron channel and enables current to
flow. A low voltage disables the channel.
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Mos Characteristics
Click on the MOS characteristics icon. The screen shown in Figure 5 appears. It represents the
Id/Vd simulation of the nMOS device.
Fig. 5. N-Channel MOS characteristics.
The MOS size (width and length of the channel situated at the intersection of the polysilicon gate
and the diffusion) has a strong influence on the value of the current. In Figure 5, the MOS width
is 12.8µm and the length is 1.2µm. Click on OK to return to the editor. A high gate voltage (Vg
=5.0) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. The maximum current
is obtained for Vg=5.0V, Vd=5.0V, with Vs=0.0.
The MOS parameters correspond to SPICE Level 3. You can alter the value of the parameters, or
even access to Level 1. You may also skip to PMOS. You may as well add some measurements to
fit the simulation. Finally, you can simulate devices with other sizes in the proposed list.
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Add Properties for Simulation
Properties must be added to the layout to activate the MOS device. The most convenient way to
operate the MOS is to apply a clock to the gate, another to the source and to observe the drain. The
summary of available properties is reported below.
VDD property
VSS property Node visible
Pulse property
Clock property
Apply a clock to the drain. Click on the Clock icon, click on the left diffusion. The Clock menu
appears (See below). Change the name into « drain » and click on OK. A default clock with 3 ns
period is generated. The Clock property is sent to the node and appears at the right hand side of
the desired location with the name « drain ».
Fig. 6. The clock menu.
Apply a clock to the gate. Click on the Clock icon and then, click on
the polysilicon gate. The clock menu appears again.
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Change the name into « gate» and click on OK to apply a clock with 6 ns period.
Watch the output: Click on the Visible icon and then, click on the right diffusion.
The window below appears. Click OK. The Visible property is then sent
to the node. The associated text « s1 » is in italic. The wave form of this node
will appear at the next simulation.
Fig. 7. The visible node menu.
Save before Simulation
Click on File in the main menu. Move the cursor to Save as ... and click on it. A new window
appears, into which you enter the design name. Type, for example, myMos. Use the keyboard for
this and press . Then click on OK. After a confirmation question, the design is saved under that
filename.
IMPORTANT : Always save BEFORE any simulation !
Analog Simulation
Click on Simulate on the main menu. The timing diagrams of the inverter appear, as shown in
Figure 8.
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Fig. 8. Analog simulation of the MOS device.
When the gate is at zero, no channel exists so the node s1 is disconnected from the drain. When
the gate is on, the source copies the drain. It can be observed that the nMOS device drives well at
zero but at the high voltage. The final value is 4.2V, that is VDD minus the threshold voltage.
Click on More in order to perform more simulations. Click on Stop to return to the editor.
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λ (Lambda) Rule:
Design Rules
The software can handle various technologies. The process parameters are stored in files with the
appendix '.RUL'. The default technology corresponds to the ATMEL-ES2 2-metal 0.8µm CMOS process.
The default file is ES208.RUL.
To select a foundry, click on File -> Select Foundry and choose the appropriate technology in the list.
N-Well
r101 r102
nwell nwell
p substrate
r101 Minimum well size : 12
r102 Between wells : 12
Diffusion
r201 Minimum diffusion size : 4
r202 Between two diffusions : 4
r203 Extra well after diffusion : 6
r204 Between diffusion and well : 6
r203 r202
P+ diff P+ diff
r201
nwell
r204
N+ diff
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Polysilicon
r301 Polysilicon width : 2
r302 Polysilicon gate on diff n+ : 2
r303 Polysilicon gate on diff p+ : 2
r304 Between two polysilicons : 3
r305 Poly v.s other diff diffusion : 2
r306 Diffusion after polysilicon : 4
r307 Extension of Poly after diff : 3
Contact
r401 Contact width : 2
r402 Between two contacts : 3
r403 Extra metal over contact:1
r404 Extra poly over contact: 2
r405 Extra diff over contact: 1
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r403
r402
metal
r401 contact
r405 r404
N+diff poly
Metal 1
r501 Metal width : 3
r502 Between two metals : 3
r501
metal r502 metal
Via
r601 Via width : 3
r602 Between two Via: 3
r603 Between Via and contact: 3
r604 Extra metal over via: 2
r605 Extra metal 2 over via: 2
r604
r602
vi a
metal2
r601
r603
contact
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Metal 2
r701 Metal width: 5
r702 Between two metal2 : 5
r701
metal2 r702 metal2
Via 2
r801 Via2 width : 3
r802 Between two Via2s: 4
r803 Between Via2 and via : 4
r804 Extra metal2 & metal 3 over via2: 3
Metal 3
r901 Metal3 width: 6
r902 Between two metal3s : 5
Via 3
ra01 Via3 width : 4
ra02 Between two Via3s : 6
ra03 Between Via3 and via2 : 6
ra04 Extra metal4 and metal3 over via3: 6
Metal 4
rb01 Metal4 width: 10
rb02 Between two metal4s: 22
Via 4
rc01 Via4 width : 4
rc02 Between two Via4s : 6
rc03 Between Via4 and Via3 : 6
rc04 Extra metal4 & metal 5 over via4: 6
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rc04
rc02
v ia4
rc01
metal5 & metal4
rc03
V ia3
Metal 5
rd01 Metal 5 width: 10
rd02 Between two metal5s : 4
Pads
rp01 Pad width: 100 µm (lambda conversion depending on the technology)
rp02 Between two pads 100 µm
rp03 Opening in passivation v.s via : 5µm
rp04 Opening in passivation v.s metals: 5µm
rp05 Between pad and unrelated active area : 20 µm
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