LM74502-Q1, LM74502H-Q1

SNOSDE0A – FEBRUARY 2022 – REVISED MAY 2022

LM74502-Q1, LM74502H-Q1 Automotive Low IQ Reverse Polarity Protection Controller

with Overvoltage Protection

1 Features 3 Description
• AEC-Q100 qualified with the following results The LM74502-Q1, LM74502H-Q1 is an automotive
– Device temperature grade 1: AEC-Q100 qualified controller which operates in
–40°C to +125°C ambient operating conjunction with an external back-to-back connected
temperature range N-channel MOSFETs as a low loss reverse polarity
– Device HBM ESD classification level 2 protection and load disconnect solution. The wide
– Device CDM ESD classification level C4B supply input range of 3.2 V to 65 V allows control
• 3.2-V to 65-V input range (3.9-V start-up) of many popular DC bus voltages such as 12-V,
• –65-V input reverse voltage rating 24-V and 48-V automotive battery systems. The 3.2-
• Integrated charge pump to drive V input voltage support is particularly well suited
– External back-to-back N-Channel MOSFETs for severe cold crank requirements in automotive
– External high side switch MOSFET systems. The device can withstand and protect the
– External reverse polarity protection MOSFET loads from negative supply voltages down to –65
• Gate drive variants V. The LM74502-Q1, LM74502H-Q1 does not have
– LM74502-Q1: 60-μA peak gate drive source reverse current blocking and is suitable for input
capacity reverse polarity protection of loads that can potentially
– LM74502H-Q1: 11-mA peak gate drive source deliver energy back to the input supply such as
capacity automotive body control module motor loads.
• 2-A peak gate sink capacity The LM74502-Q1 controller provides a charge pump
• 1-µA shutdown current (EN/UVLO = Low) gate drive for an external N-channel MOSFET.
• 45-µA typical operating quiescent current (EN/ The high voltage rating of LM74502-Q1 helps to
UVLO = High) simplify the system designs for automotive ISO7637
• Adjustable overvoltage and undervoltage protection. With the enable pin low, the controller is
protection off and draws approximately 1 µA of current, thus
• Meets automotive ISO7637 pulse 1 transient offering low system current when put into sleep mode.
requirements with additional TVS diode LM74502-Q1 offers programmable overvoltage and
• Available in 8-pin SOT-23 package 2.90 mm × undervoltage protection which cuts off the load from
1.60 mm the input source in case of these faults.
2 Applications Device Information(1)
• Body electronics and lighting PART NUMBER PACKAGE BODY SIZE (NOM)
• Automotive infotainment systems – digital cluster, LM74502-Q1
SOT-23 (8) 2.90 mm × 1.60 mm
head unit LM74502H-Q1
• Automotive USB hubs
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VBATT VOUT VIN Q1 VOUT

CIN CIN
COUT COUT

VS GATE SRC VS GATE SRC

CVCAP CVCAP
R1 R1

VCAP LM74502-Q1 VCAP

LM74502-Q1
OV EN / UVLO OV EN/UVLO
ON OFF ON OFF
R2
R2
GND GND

LM74502-Q1 as a Load Switch Controller with

LM74502-Q1 Typical Application Schematic Overvoltage Protection

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 10 Application and Implementation................................ 15
2 Applications..................................................................... 1 10.1 Application Information........................................... 15
3 Description.......................................................................1 10.2 Typical Application.................................................. 15
4 Revision History.............................................................. 2 10.3 Surge Stopper Using LM74502-Q1,
5 Device Comparison Table...............................................3 LM74502H-Q1.............................................................20
6 Pin Configuration and Functions...................................4 10.4 Fast Turn-On and Turn-Off High Side Switch
7 Specifications.................................................................. 5 Driver Using LM74502H-Q1........................................ 21
7.1 Absolute Maximum Ratings........................................ 5 11 Power Supply Recommendations..............................23
7.2 ESD Ratings............................................................... 5 12 Layout...........................................................................23
7.3 Recommended Operating Conditions.........................5 12.1 Layout Guidelines................................................... 23
7.4 Thermal Information....................................................6 12.2 Layout Example...................................................... 23
7.5 Electrical Characteristics.............................................6 13 Device and Documentation Support..........................24
7.6 Switching Characteristics............................................7 13.1 Receiving Notification of Documentation Updates..24
7.7 Typical Characteristics................................................ 8 13.2 Support Resources................................................. 24
8 Parameter Measurement Information.......................... 10 13.3 Trademarks............................................................. 24
9 Detailed Description...................................................... 11 13.4 Electrostatic Discharge Caution..............................24
9.1 Overview................................................................... 11 13.5 Glossary..................................................................24
9.2 Functional Block Diagram......................................... 11 14 Mechanical, Packaging, and Orderable
9.3 Feature Description...................................................12 Information.................................................................... 25
9.4 Device Functional Modes..........................................14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2022) to Revision A (May 2022) Page
• Changed status from "Advance Information" to "Production Data".....................................................................1

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5 Device Comparison Table

Parameter LM74502-Q1 LM74502H-Q1
Gate drive strength 60 μA 11 mA

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6 Pin Configuration and Functions

EN/UVLO 1 8 SRC

GND 2 7 OV
6 GATE
N.C 3

VCAP 4 5 VS

Figure 6-1. DDF Package 8-Pin SOT-23 LM74502-Q1, LM74502H-Q1 Top View

Table 6-1. LM74502-Q1, LM74502H-Q1 Pin Functions

PIN
I/O(1) DESCRIPTION
NO. NAME
EN/UVLO input. Connect to VS pin for always ON operation. Can be driven externally from
a micro controller I/O. Pulling this pin low below V(ENF) makes the device enter into low
1 EN/UVLO I
Iq shutdown mode. For UVLO, connect an external resistor ladder from input supply to EN/
UVLO to GND.
2 GND G Ground pin
3 N.C — No connection
4 VCAP O Charge pump output. Connect to external charge pump capacitor.
Input power supply pin to the controller. Connect a 100-nF capacitor across VS and GND
5 VS I
pins.
6 GATE O Gate drive output. Connect to gate of the external N-channel MOSFET.
Adjustable overvoltage threshold input. Connect a resistor ladder across input and output.
When the voltage at OV pin exceeds the overvoltage cutoff threshold, then the GATE is
7 OV I pulled low. GATE turns ON when the OV pin voltage goes below the OV protection falling
threshold.
Connect OV pin to GND if OV feature is not used.

Source pin. Connect to common source point of external back-to-back connected N-channel
8 SRC I
MOSFETs or the source pin of the high side switch MOSFET.

(1) I = Input, O = Output, G = GND

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS to GND –65 65 V
EN/UVLO, OV to GND, V(VS) > 0 V –0.3 65 V
Input Pins
EN/UVLO, OV, V(VS) ≤ 0 V V(VS) (65 + V(VS))
SRC to GND, V(VS) ≤ 0 V (V(VS) + 0.3) V
Input Pins SRC to GND, V(VS) > 0 V –(70 – V(VS)) V(VS) V
GATE to SRC 0 15 V
Output Pins
VCAP to VS –0.3 15 V
Operating junction temperature(2) –40 150 °C
Storage temperature, Tstg –40 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) ±2000
Corner pins (EN, VCAP, SRC,
V(ESD) Electrostatic discharge Charged device model (CDM), ±750 V
VS)
per AEC Q100-011
Other pins ±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VS to GND –60 60
Input Pins V
EN/UVLO, OV, SRC to GND –60 60

External VS 22 nF
capacitance VCAP to VS 0.1 µF
External
MOSFET max GATE to SRC 15 V
VGS rating
TJ Operating junction temperature range(2) –40 150 °C

(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see electrical characteristics
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

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7.4 Thermal Information

LM74502-Q1
LM74502H-Q1
THERMAL METRIC(1) UNIT
DDF (SOT)
8 PINS
RθJA Junction-to-ambient thermal resistance 133.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.6 °C/W
RθJB Junction-to-board thermal resistance 54.5 °C/W
ΨJT Junction-to-top characterization parameter 4.6 °C/W
ΨJB Junction-to-board characterization parameter 54.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

7.5 Electrical Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(VS) = 12 V, C(VCAP) = 0.1 µF, V(EN/UVLO) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VS SUPPLY VOLTAGE
V(VS) Operating input voltage 4 60 V
VS POR Rising threshold 3.9 V
V (VS_POR)
VS POR Falling threshold 2.2 2.8 3.1 V
V(VS POR(Hys)) VS POR Hysteresis 0.44 0.67 V
I(SHDN) Shutdown Supply Current V(EN/UVLO) = 0 V 0.9 1.5 µA
I(Q) Operating Quiescent Current IGND 45 65 µA
I(S) leakage current during input
I(REV) 0 V ≤ V(VS) ≤ – 65 V 100 150 µA
reverse polarity
ENABLE INPUT
V(EN_UVLOF) Enable/UVLO falling threshold 1.027 1.14 1.235
V
V(EN_UVLOR) Enable/UVLO rising threshold 1.16 1.24 1.32
Enable threshold voltage for low IQ
V(ENF) 0.32 0.64 0.94 V
shutdown
V(EN_Hys) Enable Hysteresis 38 90 132 mV
I(EN) Enable sink current V(EN/UVLO) = 12 V 3 5 µA
GATE DRIVE
I(GATE) Peak source current V(GATE) – V(SRC) = 5 V 40 60 77 µA
Peak source current V(GATE) – V(SRC) = 5 V, LM74502H-Q1 3 11 mA
I(GATE) EN/UVLO= High to Low
Peak sink current 2370 mA
V(GATE) – V(SRC) = 5 V
EN/UVLO = High to Low
RDSON discharge switch RDSON 0.4 2 Ω
V(GATE) – V(SRC) = 100 mV
CHARGE PUMP
Charge Pump source current (Charge
V(VCAP) – V(S) = 7 V 162 300 600 µA
pump on)
I(VCAP)
Charge Pump sink current (Charge
V(VCAP) – V(S) = 14 V 5 10 µA
pump off)
V(VCAP) – V(VS) Charge pump voltage at V(S) = 3.2 V I(VCAP) ≤ 30 µA 8 V
V(VCAP) – V(VS) Charge pump turn-on voltage 10.3 11.6 13 V
V(VCAP) – V(VS) Charge pump turn-off voltage 11 12.4 13.9 V
Charge Pump Enable comparator
V(VCAP) – V(VS) 0.45 0.8 1.25 V
Hysteresis

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(VS) = 12 V, C(VCAP) = 0.1 µF, V(EN/UVLO) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(VCAP) – V(VS) UV release at rising
V(VCAP UVLO) 5.7 6.5 7.5 V
edge
V(VCAP) – V(VS) UV threshold at falling
V(VCAP UVLO) 5.05 5.4 6.2 V
edge
OVERVOLTAGE PROTECTION
V(OVR) Overvoltage threshold input, rising 1.165 1.25 1.333 V
V(OVF) Overvoltage threshold input, falling 1.063 1.143 1.222 V
V(OV_Hys) OV Hysteresis 100 mV
I(OV) OV Input leakage current 0 V < V(OV) < 5 V 12 50 110 nA

7.6 Switching Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(VS) = 12 V, CIN = C(VCAP) = COUT = 0.1 µF, V(EN/UVLO) = 3.3 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(VCAP) > V(VCAP UVLOR), V(EN/UVLO) step
from (0 V to > V(EN_UVLOR) ) ,
ENTDLY EN high to Gate Turn-on delay 75 110 µs
V(GATE-SRC) > 5 V, C(GATE-SRC) = 4.7
nF, LM74502H-Q1
tEN_OFF(deg)_G V(EN/UVLO) ↓ to V(GATE-SRC) < 1 V, C(GATE-
GATE Turn-off delay during EN/UVLO 2 µs
ATE SRC) = 4.7 nF

tOVP_OFF(deg)_ V(OV) ↑ to V(GATE-SRC) < 1 V, C(GATE-SRC)

GATE Turn-off delay during OV 0.6 1 µs
GATE = 4.7 nF
V(OV) ↓ to V(GATE-SRC) > 5 V, C(GATE-SRC)
tOVP_ON(deg)_G
GATE Turn-on delay during OV = 4.7 nF 5 10 µs
ATE
LM74502H-Q1,

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7.7 Typical Characteristics

7 420
390 –40C
360 25C
5.6 85C
330 125C

Quiescent Current (A)

Shutdown Current (A)

300 150C
270
4.2 240
210
–40C
25C 180
2.8
85C 150
125C 120
150C 90
1.4
60
30
0 0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65
VS (V) VS (V)

Figure 7-1. Shutdown Supply Current vs Supply Voltage Figure 7-2. Operating Quiescent Current vs Supply Voltage
390 550
–40C
360 500 25C
330 85C
Charge Pump Current (A)

Charge Pump Current (A)

450 125C
300 150C
400
270
240 350
210 300
180 –40C
25C 250
150 85C
200
120 125C
150C 150
90
60 100
3 4 5 6 7 8 9 10 11 12 0 2 4 6 8 10 12
VS (V) VCAP (V)
Figure 7-3. Charge Pump Current vs Supply Voltage at VCAP = 6 Figure 7-4. Charge Pump V-I Characteristics at VS > = 12 V
V
240 1.35
–40C Enable/UVLO rising
220 Enable/UVLO falling
25C
200 85C 1.28
Charge Pump Current (A)

125C
EN/UVLO Threshold (V)

180 150C
160 1.21
140
120
1.14
100
80
1.07
60
40
1
20
-40 0 40 80 120 160
0 1 2 3 4 5 6 7 8 9
Free-Air Temperature (C)
VCAP (V)
Figure 7-5. Charge Pump V-I Characteristics at VS = 3.2 V Figure 7-6. EN/UVLO Rising and Falling threshold vs
Temperature

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7.7 Typical Characteristics (continued)

85 14
VCAP ON

Charge Pump ON/OFF Threshold (V)

VCAP OFF
EN to GATE Turn ON Delay (s)

80 13.4

75 12.8

70 12.2

65 11.6

11
60
-40 0 40 80 120 160
-40 0 40 80 120 160
Free-Air Temperature (C)
Free-Air Temperature (C)
Figure 7-7. Enable to Gate Delay vs Temperature Figure 7-8. Charge Pump ON and OFF Threshold vs
(LM74502H-Q1) Temperature

7.4 3.2
VCAP UVLOR VS PORR
VCAP UVLOF VS PORF
Charge Pump UVLO Threshold (V)

7
3

VS POR Threshold (V)

6.6
2.8
6.2
2.6
5.8

2.4
5.4

5 2.2
-40 0 40 80 120 160 -40 0 40 80 120 160
Free-Air Temperature (C) Free-Air Temperature (C)
Figure 7-9. Charge Pump UVLO Threshold vs Temperature Figure 7-10. VS POR Threshold vs Temperature
1.4 6
OV Rising
OV Falling
5
OV Comparator Threshold (V)

1.32
OV to GATE Delay (s)

4
1.24 GATE OFF
GATE ON
3
1.16
2
1.08
1

1
-40 0 40 80 120 160 0
Free-Air Temperature (C) -40 0 40 80 120 160
Free-Air Temperature (C)
Figure 7-11. OV Comparator Threshold vs Temperature
Figure 7-12. OV to GATE Delay vs Temperature (LM74502H-Q1)

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8 Parameter Measurement Information

3.3 V
VEN

VEN/UVLOF – 0.1 V

VENF
0V
0V

12.4 V 12.4 V
90%

VGATE – VSRC
VGATE – VSRC

1V
0V 0V
tENTDLYt ttUVLO_OFF(deg)GATEt

VOVR + 0.1 V VOVF – 0.1 V

0V 0V

12.4 V 12.4 V

VGATE – VSRC
VGATE – VSRC

5V
1V
0V 0V
ttOVP_OFF(deg)GATEt ttOVP_ON(deg)GATEt

Figure 8-1. Timing Waveforms

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9 Detailed Description
9.1 Overview
The LM74502-Q1, LM74502H-Q1 controller has all the features necessary to implement an efficient and fast
reverse polarity protection circuit with load disconnect function. This easy to use reverse polarity protection
controller is paired with an external back-to-back connected N-channel MOSFETs to replace other reverse
polarity schemes such as a P-channel MOSFETs. The wide input supply of 4 V to 65 V allows protection
and control of 12-V and 24-V automotive battery powered ECUs. The device can withstand and protect the
loads from negative supply voltages down to –65 V. An integrated charge pump drives external back-to-back
connected N-channel MOSFETs with gate drive voltage of approximately 12.4 V to realize reverse polarity
protection and load disconnect function in case of overvoltage and undervoltage event. LM74502-Q1 with it's
typical gate drive strength of 60 μA provides smooth start-up with inherent inrush current control due to its lower
gate drive strength. LM74502H-Q1 with it's 11-mA typical peak gate drive strength is suitable for applications
which need faster turn on such as load switch applications. LM74502-Q1 features an adjustable overvoltage
cutoff protection feature using a programming resistor divider to OV terminal. LM74502-Q1 features enable
control. With the enable pin low during the standby mode, both the external MOSFETs and controller is off and
draws a very low 1 μA of current.
9.2 Functional Block Diagram
VIN VOUT

VS VCAP GATE SRC

CP
CP
VS

VCAP Gate
Internal Driver
Rails

Charge Gate Drive

VS Pump Enable
Enable Logic
Logic

UVLOb EN OV
+ OV
EN 1.25 V
EN/UVLO +
1V 1.14 V

0.3 V VS

+ UVLOb
1.25 V Reverse
Protection Logic
1.14 V LM74502-Q1
LM74502H-Q1

GND

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9.3 Feature Description

9.3.1 Input Voltage (VS)
The VS pin is used to power the LM74502-Q1's internal circuitry, typically drawing 45 µA when enabled and 1
µA when disabled. If the VS pin voltage is greater than the POR Rising threshold, then LM74502-Q1 operates in
either shutdown mode or conduction mode in accordance with the EN/UVLO pin voltage. The voltage from VS to
GND is designed to vary from 65 V to –65 V, allowing the LM74502-Q1 to withstand negative voltage transients.
9.3.2 Charge Pump (VCAP)
The charge pump supplies the voltage necessary to drive the external N-channel MOSFET. An external charge
pump capacitor is placed between VCAP and VS pin to provide energy to turn on the external MOSFET. For the
charge pump to supply current to the external capacitor the EN/UVLO pin, voltage must be above the specified
input high threshold, V(EN_IH). When enabled the charge pump sources a charging current of 300-µA typically. If
EN/UVLO pins is pulled low, then the charge pump remains disabled. To ensure that the external MOSFET can
be driven above its specified threshold voltage, the VCAP to VS voltage must be above the undervoltage lockout
threshold, typically 6.5 V, before the internal gate driver is enabled. Use Equation 1 to calculate the initial gate
driver enable delay.

T(DRV_EN) = 75 µs + C(VCAP) × V(VCAP_UVLOR)

300 µA (1)

where
• C(VCAP) is the charge pump capacitance connected across VS and VCAP pins
• V(VCAP_UVLOR) = 6.5 V (typical)
To remove any chatter on the gate drive approximately 800 mV of hysteresis is added to the VCAP undervoltage
lockout. The charge pump remains enabled until the VCAP to VS voltage reaches 12.4 V, typically, at which point
the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until
the VCAP to VS voltage is below to 11.6 V typically at which point the charge pump is enabled. The voltage
between VCAP and VS continue to charge and discharge between 11.6 V and 12.4 V as shown in Figure 9-1. By
enabling and disabling the charge pump, the operating quiescent current of the LM74502-Q1 is reduced. When
the charge pump is disabled it sinks 5-µA typical.
TDRV_EN TON TOFF

VIN

VS

0V

VEN

12.4 V

11.6 V
VCAP-VS
6.5 V V(VCAP UVLOR)

GATE DRIVER
(GATE to SRC)
ENABLE

Figure 9-1. Charge Pump Operation

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9.3.3 Gate Driver (GATE an SRC)

The gate driver is used to control the external N-Channel MOSFET by setting the appropriate GATE to SRC
voltage.
Before the gate driver is enabled following three conditions must be achieved:
• The EN/UVLO pin voltage must be greater than the specified input high voltage.
• The VCAP to VS voltage must be greater than the undervoltage lockout voltage.
• The VS voltage must be greater than VS POR Rising threshold.
If the above conditions are not achieved, then the GATE pin is internally connected to the SRC pin, assuring that
the external MOSFET is disabled. After these conditions are achieved the gate driver operates in the conduction
mode enhancing the external MOSFET completely.
The controller offers two gate drive variants. LM74502-Q1 with typical peak gate drive strength of 60 μA is
suitable to achieve smooth start-up with inherent inrush current control due to its lower gate drive strength.
LM74502H-Q1 with its 11-mA typical peak gate drive strength is suitable for applications which need faster
turn-on such as load switch applications.
LM74502-Q1, LM74502H-Q1 SRC pin is capable of handling negative voltage which also makes it suitable for
load disconnect switch applications with loads which are inductive in nature.

9.3.3.1 Inrush Current Control

An external circuit as shown in Figure 9-2 can be added on the GATE pin of the LM74502-Q1 to have additional
inrush current control for the applications which have large capacitive loads.
Q1

RG
Cdvdt

GATE SRC

LM74502-Q1

Figure 9-2. Inrush Current Limiting Using LM74502-Q1

The CdVdT capacitor is required for slowing down the GATE voltage ramp during power up for inrush current
limiting. Use Equation 2 to calculate CdVdT capacitance value.
Cdvdt = IGATE × COUT
IINRUSH (2)

where IGATE is 60 μA (typical), IINRUSH is the inrush current and COUT is the output load capacitance. An extra
resistor, RG, in series with the CdVdT capacitor acts as an isolation resistor between Cdvdt and gate of the
MOSFET.
The inrush current control scheme shown in Figure 9-2 is not applicable to LM74502H-Q1 as its gate drive is
optimized for fast turn-on load switch applications.

9.3.4 Enable and Undervoltage Lockout (EN/UVLO)

The LM74502-Q1 has an enable pin, EN/UVLO. The enable pin allows for the gate driver to be either enabled
or disabled by an external signal. If the EN/UVLO pin voltage is greater than the rising threshold, the gate driver
and charge pump operates as described in Gate Driver and Charge Pump sections. If the enable pin voltage
is less than the input low threshold, the charge pump and gate driver are disabled placing the LM74502-Q1

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in shutdown mode. The EN/UVLO pin can withstand a voltage as large as 65 V and as low as –65 V. This
feature allows for the EN/UVLO pin to be connected directly to the VS pin if enable functionality is not needed. In
conditions where EN/UVLO is left floating, the internal sink current of 3 uA pulls EN/UVLO pin low and disables
the device.
An external resistor divider connected from input to EN/UVLO to ground can be used to implement the input
Undervoltage Lockout (UVLO) functionality. When EN/UVLO pin voltage is lower than UVLO comparator falling
threshold (VEN/UVLOR) but higher than enable falling threshold (VENF), the device disables gate drive voltage,
however, charge pump is kept on. This action ensures quick recovery of gate drive when UVLO condition is
removed. If UVLO functionality is not required, connect EN/UVLO pin to VS.
9.3.5 Overvoltage Protection (OV)
LM74502-Q1 provides programmable overvoltage protection feature with OV pin. A resistor divider can be
connected from input source to OV pin to ground to set overvoltage threshold. An internal comparator compares
the input voltage against fixed reference (1.25 V) and disables the gate drive as soon as OV pin voltage goes
above the OV comparator reference. When the resistor divider is referred from input supply side, the device is
configured for overvoltage cutoff functionality. When the resistor divider is referred from output side (VOUT), the
device is configured for overvoltage clamp functionality.
When OV pin voltage goes above OV comparator VOVR threshold (1.25-V typical), the device disables gate
drive, however, charge pump remains active. When OV pin voltage falls below VOVF threshold (1.14-V typical),
the gate is quickly turned on as charge pump is kept on and the device does not go through the device start-up
process. When OV pin is not used, it can be connected to ground.
9.4 Device Functional Modes
9.4.1 Shutdown Mode
The LM74502-Q1 enters shutdown mode when the EN/UVLO pin voltage is below the specified input low
threshold V(EN_IL). Both the gate driver and the charge pump are disabled in shutdown mode. During shutdown
mode the LM74502-Q1 enters low IQ operation with the VS pin only sinking 1 µA.
9.4.2 Conduction Mode
For the LM74502-Q1, LM74502H-Q1 to operate in conduction mode the gate driver must be enabled as
described in the Gate Driver (GATE an SRC) section. If these conditions are achieved the GATE pin is
• Internally driven through 60-μA current source in case of LM74502-Q1
• Internally connected to the VCAP for fast turn-on of external FET in case of LM74502H-Q1
LM74502-Q1, LM74502H-Q1 gate drive is disabled when OV pin voltage is above VOVR threshold or EN/UVLO
pin voltage is lower than VEN/UVLOF threshold.

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10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

10.1 Application Information

The LM74502-Q1 is used with N-Channel MOSFET controller in a typical reverse polarity protection application.
The schematic for the 12-V battery protection application is shown in Figure 10-1 where the LM74502-Q1 is
used to drive back-to-back connected MOSFETs Q1 and Q2 in series with a battery to realize reverse polarity
protection and load disconnect solution. The TVS is not required for the LM74502-Q1 to operate, but they are
used to clamp the positive and negative voltage surges. TI recommends the output capacitor COUT to protect the
immediate output voltage collapse as a result of line disturbance.
10.2 Typical Application
Q1 Q2
VBATT VOUT
12 V
CIN COUT
0.1 µF 220 µF
SMBJ33CA
CVCAP VS GATE SRC
220 nF
R1
100 kΩ
VCAP LM74502-Q1

OV EN / UVLO
ON OFF
R2
GND
3.5 kΩ

Figure 10-1. Typical Application Circuit

10.2.1 Design Requirements

Table 10-1 list design examples with system design parameters.
Table 10-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
12-V battery, 12-V nominal with 3.2-V cold crank and 35-V load
Input voltage range
dump
Output voltage 3.2 V during cold crank to 35-V load dump
Output current range 3-A nominal, 5-A maximum
Output capacitance 220-µF typical output capacitance
Overvoltage Protection 37-V typical
Automotive EMC compliance ISO 7637-2 and ISO 16750-2

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10.2.2 Detailed Design Procedure

10.2.2.1 Design Considerations
• Input operating voltage range, including overvoltage conditions
• Nominal load current and maximum load current
10.2.2.2 MOSFET Selection
The important MOSFET electrical parameters are the maximum continuous drain current, ID, the maximum
drain-to-source voltage, VDS(MAX), the maximum source current through body diode, and the drain-to-source On
resistance, RDSON.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The
maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage
seen in the application. This requirement includes any anticipated fault conditions. TI recommends to use
MOSFETs with voltage rating up to 60-V maximum with the LM74502-Q1 because SOURCE pin maximum
voltage rating is 65 V. The maximum VGS LM74502-Q1 can drive is 13.9 V, so a MOSFET with 15-V minimum
VGS rating must be selected. If a MOSFET with VGS rating < 15 V is selected, a Zener diode can be used to
clamp VGS to safe level.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred. Selecting a MOSFET with
RDS(ON) that gives VDS drop 20 mV to 50 mV at full load provides good trade off in terms of power dissipation
and cost.
Thermal resistance of the MOSFET must be considered against the expected maximum power dissipation in the
MOSFET to ensure that the junction temperature (TJ) is well controlled.
10.2.2.3 Overvoltage Protection
Resistors R1 and R2 connected in series is used to program the overvoltage threshold. Connecting R1 to VIN
provides overvoltage cutoff and switching the connection to VOUT provides overvoltage clamp response. The
resistor values required for setting the overvoltage threshold VOV to 37 V are calculated by solving Equation 3

VOVR = R2 × VOV
R1 + R2 (3)

For minimizing the input current drawn from the supply through resistors R1 and R2, TI recommends to use
higher value of resistance. Using high value resistors adds error in the calculations because the current through
the resistors at higher value becomes comparable to the leakage current into the OV pin. Select (R1 + R2) such
that current through resistors is around 100 times higher than the leakage through OV pin. Based on the device
electrical characteristics, VOVR is 1.25 V, select (R1) = 100 kΩ and R2 = 3.5 kΩ as a standard resistor value to
set overvoltage cutoff of 37 V.
Based on application use case, overvoltage threshold can be set at the lower voltage as it enables lower rated
downstream components, thus providing solution size and lower cost benefit.
10.2.2.4 Charge Pump VCAP, Input and Output Capacitance
Minimum required capacitance for charge pump VCAP and input and output capacitance are:
• VCAP: Minimum recommended value of VCAP (µF) ≥ 10 × CISS(MOSFET_effective) (µF),
CVCAP of 0.22 µF is selected
• CIN: Typical input capacitor of 0.1 µF
• COUT: Typical output capacitor 220 µF
10.2.3 Selection of TVS Diodes for 12-V Battery Protection Applications
TVS diodes are used in automotive systems for protection against transients. In the 12-V battery protection
application circuit shown in Figure 10-1, a bi-directional TVS diode is used to protect from positive and negative

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transient voltages that occur during normal operation of the car and these transient voltage levels and pulses are
specified in ISO 7637-2 and ISO 16750-2 standards.
The two important specifications of the TVS are breakdown voltage and clamping voltage. Breakdown voltage
is the voltage at which the TVS diode goes into avalanche similar to a Zener diode and is specified at a low
current value typical 1 mA and the breakdown voltage must be higher than worst case steady state voltages
seen in the system. The breakdown voltage of the TVS+ must be higher than 24-V jump start voltage and 35-V
suppressed load dump voltage and less than the maximum input voltage rating of LM74502-Q1 (65 V). The
breakdown voltage of TVS– must be higher than maximum reverse battery voltage –16 V, so that the TVS– is
not damaged due to long time exposure to reverse connected battery.
Clamping voltage is the voltage the TVS diode clamps in high current pulse situations and this voltage is much
higher than the breakdown voltage. TVS diodes are meant to clamp transient pulses and must not interfere
with steady state operation. In the case of an ISO 7637-2 pulse 1, the input voltage goes up to –150 V with a
generator impedance of 10 Ω. This action translates to 15 A flowing through the TVS– and the voltage across
the TVS is close to its clamping voltage.
The next criterion is that the absolute minimum rating of source voltage of the LM74502-Q1 (–65 V) and the
maximum VDS rating MOSFET are not exceeded. In the design example, 60-V rated MOSFET is chosen.
SMBJ series of TVS' are rated up to 600-W peak pulse power levels. This rating is sufficient for ISO 7637-2
pulses and suppressed load dump (ISO-16750-2 pulse B).
10.2.4 Selection of TVS Diodes and MOSFET for 24-V Battery Protection Applications
Typical 24-V battery protection application circuit shown in Figure 10-2 uses two uni-directional TVS diodes to
protect from positive and negative transient voltages.
Q1 Q2
VBATT VOUT
24 V
CIN COUT
TVS+ 0.1 µF 220 µF
SMBJ58A
CVCAP VS GATE SRC
220 nF
R1
TVS-
SMBJ26A VCAP LM74502-Q1

OV EN / UVLO
ON OFF
R2
GND

Figure 10-2. Typical 24-V Battery Protection with Two Uni-Directional TVS

The breakdown voltage of the TVS+ must be higher than 48-V jump start voltage, less than the absolute
maximum ratings of source and enable pin of LM74502-Q1 (65 V) and must withstand 65-V suppressed load
dump. The breakdown voltage of TVS– must be lower than maximum reverse battery voltage –32 V, so that the
TVS– is not damaged due to long time exposure to reverse connected battery.
During ISO 7637-2 pulse 1, the input voltage goes up to –600 V with a generator impedance of 50 Ω. Single
bi-directional TVS cannot be used for 24-V battery protection because breakdown voltage for TVS+ ≥ 48 V,
maximum negative clamping voltage is ≤ –65 V . Two uni-directional TVS connected back-to-back must be used
at the input. For positive side TVS+, TI recommends SMBJ58A with the breakdown voltage of 64.4 V (minimum),
67.8 (typical). For the negative side TVS–, TI recommends SMBJ26A with breakdown voltage close to 32 V (to
withstand maximum reverse battery voltage –32 V) and maximum clamping voltage of 42 V.
For 24-V battery protection, TI recommends a 75-V rated MOSFET to be used along with SMBJ26A and
SMBJ58A connected back-to-back at the input.

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10.2.5 Application Curves

Figure 10-3. ISO 7637-2 Pulse 1

Time (2.5 ms/DIV)

Figure 10-4. Response to ISO 7637-2 Pulse 1 (–150

V)

Time (4 ms/DIV)
Time (40 ms/DIV)
Figure 10-6. Start-up with No Load
Figure 10-5. Start-up with Input Reverse Voltage (–
12 V)

Time (4 ms/DIV) Time (20 ms/DIV)

Figure 10-7. Start-up with 5-A Load Figure 10-8. Overvoltage Cutoff Response (37 V)

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Time (20 ms/DIV)

Time (10 ms/DIV)

Figure 10-9. Overvoltage Recovery Figure 10-10. Overvoltage Clamp Response

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10.3 Surge Stopper Using LM74502-Q1, LM74502H-Q1

Many automotive applications are designed to comply with unsuppressed load dump transients specified by
ISO16750-2 Pulse 5A. LM74502, LM74502H can be configured as input surge stopper to provide overvoltage
along with input reverse supply protection and protect the downstream loads in case of unsuppressed load dump
event.
Q1 200 V Q2 60 V
24-V VBATT
VOUT
200-V Unsuppressed
Load Dump

CIN R1 COUT VOUT

0.1 µF 10 k
220 µF (OV Clamp)

R2 VIN
VS GATE SRC 100 k OV cut-off

DZ OV
CVS 60 V VCAP R3
1 µF CVCAP LM74502-Q1 3.5 k
220 nF

EN/UVLO

GND ON OFF

Figure 10-11. Typical Surge Stopper Application for 24-V Powered Systems

As shown in Figure 10-11, MOSFET Q1 is used to turn off or clamp output voltage to acceptable safe level
and protect the MOSFET Q2 and LM74502 from input transient. Note that only the VS pin is exposed to input
transient through a resistor, R1. A 60-V rated Zener diode is used to clamp and protect the VS pin within
recommended operating condition. Th rest of the circuit is not exposed to higher voltage as the MOSFET Q1 can
either be turned off completely or output voltage clamped to safe level.

10.3.1 VS Capacitance, Resistor R1 and Zener Clamp (DZ)

A minimum of 1-µF CVS capacitance is required. During input overvoltage transient, resistor R1 and Zener diode,
DZ, are used to protect VS pin from exceeding the maximum ratings by clamping VVS to 60 V. Choosing R1 = 10
kΩ, the peak power dissipated in Zener diode DZ can be calculated using Equation 4 .

PDZ = VDZ × (VIN(MAX) – VDZ)

R1 (4)

Where VDZ is the breakdown voltage of Zener diode. Select the Zener diode that can handle peak power
requirement.
Peak power dissipated in resistor R1 can be calculated using Equation 5.

PR1 = (VIN(MAX) – VDZ)2

R1 (5)

Select a resistor package which can handle peak power and maximum DC voltage.
10.3.2 Overvoltage Protection
For the overvoltage setting, refer to the resistor selection procedure described in Overvoltage Protection. Select
(R2) = 100 kΩ and R3 = 3.5 kΩ as a standard resistor value to set overvoltage cutoff of 37 V.

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10.3.3 MOSFET Selection

The VDS rating of the MOSFET Q1 must be minimum VIN(max) for designs with output overvoltage cutoff where
output can reach 0 V with higher loads. For designs with output overvoltage clamp, MOSFET VDS rating must
be (VIN(max) – VOUT_CLAMP). The VGS rating is based on GATE-SRC maximum voltage of 15 V. TI recommends a
20-V VGS rated MOSFET. Power dissipation on MOSFET Q1 on a design where output is clamped is critical and
SOA characteristics of the MOSFET must be considered with sufficient design margin for reliable operation. An
additional Zener diode from GATE to SRC can be needed to protect the external FET in case output is expected
to drop to the level where it can exceed external FET VGS(max) rating.

Figure 10-12. 200-V Surge Stopper with Overvoltage Cutoff Using LM74502-Q1

10.4 Fast Turn-On and Turn-Off High Side Switch Driver Using LM74502H-Q1
In automotive load driving applications N-Channel MOSFET based high side switch is very commonly used to
disconnect the loads from supply line in case of faults such as overvoltage event . LM74502-Q1, LM74502H-Q1
can be used to drive external MOSFET to realize simple high side switch with overvoltage protection. Figure
10-13 shows a typical application circuit where LM74502H-Q1 is used to drive external MOSFET Q1 as a main
power path connect and disconnect switch. A resistor divider from input to OV pin to ground can be used the set
the overvoltage threshold.
If VOUT node (SRC pin) of the device is expected to drop in case of events such as overcurrent or short-circuit
on load side then additional Zener diode is required across gate and source pin of external MOSFET to protect it
from exceeding its maximum VGS rating.

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Q1

VIN
VOUT High Side LOAD3
Switch
COUT
CIN
10 µF
4.7 µF

VS GATE SRC Low Side LOAD2

CVCAP Switch
VIN
470 nF
R1

OV pin used for VCAP

overvoltage R2 LM74502H-Q1 DC/DC LOAD3
protection Converter
OV EN/UVLO
ON OFF

GND
OFF
ON

OV pin used as logic input for

fast turn ON/OFF of FET Q1

Figure 10-13. Fast Turn-ON and OFF High Side Switch Using LM74502H-Q1

Many safety applications require fast switching off of the MOSFET in case of fault events such as overvoltage
or overcurrent fault. Some of the load driving path applications also require PWM operation of high side switch.
LM74502H-Q1 OV pin can be used as control input to realize fast turn-on and turn-off load switch functionality.
With OV pin pulled above VOVR threshold of (1.25-V typical), LM74502H-Q1 turns off the external MOSFET (with
Ciss = 4.7 nF) within 1 μs typically. When OV pin is pulled low, LM74502H-Q1 with its peak gate drive strength of
11 mA turns on external MOSFET with turn-on speed of 7-μs typical. Figure 10-14 shows LM74502H-Q1 GATE
to SRC response when OV pin is toggled with ON/OFF logic input.

Figure 10-14. Fast Turn-On and Turn-Off High Side Switch Driver Using LM74502H-Q1

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11 Power Supply Recommendations

The LM74502-Q1, LM74502H-Q1 reverse polarity protection controller is designed for the supply voltage range
of 3.2 V ≤ VS ≤ 65 V. If the input supply is located more than a few inches from the device, TI recommends
an input ceramic bypass capacitor higher than 0.1 μF. Based on system requirements, a higher input bypass
capacitor can be needed with LM74502H-Q1 to avoid supply glitch in case of high inrush current start-up event.
To prevent LM74502-Q1 and surrounding components from damage under the conditions of a direct output short
circuit, use a power supply having overload and short-circuit protection.
12 Layout
12.1 Layout Guidelines
• Connect GATE and SRC pin of LM74502-Q1 close to the MOSFET's gate and source pin.
• Use thick traces for source and drain of the MOSFET to minimize resistive losses because the high current
path of for this solution is through the MOSFET.
• Keep the charge pump capacitor across VCAP and VS pin away from the MOSFET to lower the thermal
effects on the capacitance value.
• Connect the GATE pin of the LM74502-Q1 to the MOSFET gate with short trace. Avoid excessively thin and
long running trace to the Gate Drive.

12.2 Layout Example

Bo
om Layer
Signal Via
G
D
D

VOUT
Q2
D

S
S
D

G S S S

COUT

LM74502-Q1
EN 1 8 SRC Q1
GND 2 7 OV
VIN
N.C 3 6 GATE
D D D D

VCAP 4 5 VS

CIN TVS
CVCAP

GND GND

Figure 12-1. Layout Example

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13 Device and Documentation Support

13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LM74502HQDDFRQ1 Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 502HQ
LM74502HQDDFRQ1.A Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 502HQ
LM74502QDDFRQ1 Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L502Q
LM74502QDDFRQ1.A Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L502Q

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM74502-Q1, LM74502H-Q1 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

• Catalog : LM74502, LM74502H

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM74502HQDDFRQ1 SOT-23- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
THIN
LM74502QDDFRQ1 SOT-23- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
THIN

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM74502HQDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
LM74502QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DDF0008A SCALE 4.000
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

C
2.95 SEATING PLANE
TYP
2.65

A PIN 1 ID 0.1 C
AREA

6X 0.65
8
1

2.95
2.85 2X
NOTE 3 1.95

4 4X 0 -15
5
0.38
8X
0.22
1.65 0.1 C A B
B 1.1
1.55
MAX

4X 4 -15

0.20
TYP
0.08

SEE DETAIL A

0.25
GAGE PLANE

0.1
0 -8 0.6 0.0
0.3
DETAIL A
TYPICAL

4222047/E 07/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

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 EXAMPLE BOARD LAYOUT
DDF0008A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05)
SYMM
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(R0.05)
TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX EXPOSED EXPOSED

METAL 0.05 MIN
ALL AROUND ALL AROUND METAL

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4222047/E 07/2024
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DDF0008A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05) SYMM
(R0.05) TYP
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4222047/E 07/2024
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

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