DIGITAL CIRCUITS DESIGN

(23A04404A)

LECTURE NOTES

B.TECH
(II YEAR – I SEM)
(2024-25)

Department of Electronics and Communication Engineering

PARVATHAREDDY BABUL REDDY

VISVODAYA INSTITUTE OF TECHNOLOGY & SCIENCE
(AUTONOMOUS)
(Affiliated to J.N.T.U.A, Approved by AICTE and Accredited by NAAC)

Kavali – 524201, S.P.S.R Nellore Dist., A.P. India. Ph: 08626-243930.

 II B.TECH – I SEM DIGITAL CIRCUITS DESIGN (R23)

Course Code DIGITAL CIRCUITS DESIGN L T P C

23A04404A ( ECE ) 3 0 0 3
Basic Electrical and Electronics
Pre-requisite Semester III
Engineering

COURSE OBJECTIVES:

 Understand the properties of Boolean algebra, logic operations, and minimization of

Boolean functions.
 Analyze combinational and analyze sequential logic circuits.
 Understand the concepts of FSM and compare various Programmable logic devices.
 Model combinational and sequential circuits using HDLs.

COURSE OUTCOMES:

After completion of the course, student will be able to

CO1: Understand the properties of Boolean algebra, logic operations and Karnaugh Maps . (K2)
CO2: Apply minimization techniques to design combinational circuits.(K3)
CO3: Design Sequential logic circuits using different types of flip flops. (K5)
CO4: Design and Model combinational and sequential circuits using HDLs. (K5)
CO5: Compare various FSMs and also Programmable logic devices. (K4)

CO-PO MAPPING:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 3 - - - - - - - - - - 2 - 3
CO2 3 2 2 2 3 - - - - - - 3 - 3
CO3 3 3 3 2 3 - - - - - - 3 - 3
CO4 3 2 3 3 3 - - - - - - 2 - 3
CO5 3 2 3 2 3 - - - - - - 3 - 3

UNIT-I (10 Hrs)

Boolean algebra, logic operations, and minimization of Boolean functions
Number Systems and Codes, Representation of unsigned and signed integers, Floating Point
representation of real numbers, Laws of Boolean Algebra, Theorems of Boolean Algebra, Realization
of functions using logic gates, Canonical forms of Boolean Functions, Minimization of Functions
using Karnaugh Maps.

Learning Outcomes: At the end of this unit, students should be able to

 Understand different number systems and their conversions (L2)
 Understand the properties of Boolean algebra, logic operations, concepts of FSM (L2)
2
 Understand the concept of Karnaugh Maps (L2)

UNIT-II (10 Hrs)

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 II B.TECH – I SEM DIGITAL CIRCUITS DESIGN (R23)

Combinational Logic Circuits

Combinational circuits, Design with basic logic gates, design procedure, adders, subtractors, 4-bit
binary adder/ subtractor circuit, BCD adder, carry look ahead adder, binary multiplier, magnitude
comparator, data selectors, priority encoders, decoders, multiplexers, demultiplexers.
Learning Outcomes: At the end of this unit, students should be able to
 Understand the design procedure of Combinational circuit. (L2)
 Apply minimization techniques to design combinational circuits (L3)

UNIT-III (9 Hrs)
Sequential Logic Circuits
Basic architectural distinction between combinational and sequential circuits, Design procedure,
latches, flip-flops, truth tables and excitation tables, timing and triggering consideration, conversion
of flip- flops, design of counters, ripple counters, synchronous counters, ring counter, Johnson
counter, registers, shift registers, universal shift register.

Learning Outcomes: At the end of this unit, students should be able to

 Understand the design procedure of Sequential circuit. (L2)
 Design Sequential logic circuits using different types of flip flops. (L5)

UNIT-IV (8Hrs)
Hardware Description Language
Introduction to Verilog - structural specification of logic circuits, behavioral specification of logic
circuits, hierarchical Verilog Code, Verilog for combinational circuits - conditional operator, if-else
statement, case statement, for loop using storage elements with CAD tools-using Verilog constructs
for storage elements, flip-flop with clear capability, using Verilog constructs for registers and
counters.
Learning Outcomes: At the end of this unit, students should be able to
 Understand the basics of Verilog language(L2)
 Apply the conditional, loop statements . (L3)
 Design and Model combinational and sequential circuits using HDLs. (L5)

UNIT-V (8 Hrs)
Finite State Machines and Programmable Logic Devices
Types of FSM, capabilities and limitations of FSM, state assignment, realization of FSM using flip-
flops, Mealy to Moore conversion and vice-versa, reduction of state tables using partition
technique, Design of sequence detector. Types of PLD’s: PROM, PAL, PLA, basic structure of CPLD
and FPGA, advantages of FPGAs, Design of sequential circuits using ROMs, PLAs, CPLDs and FPGAs.
3
Learning Outcomes: At the end of this unit, students should be able to
 Understand the various FSMs. (L2)
 Compare various Programmable logic devices. (L4)

PBR VITS, KAVALI | ECE DEPT.

 II B.TECH – I SEM DIGITAL CIRCUITS DESIGN (R23)

TEXTBOOKS:

1. M. Morris Mano, “Digital Design”, 3rd Edition, PHI. (Unit I to IV)

2. Stephen Brown and ZvonkoVranesic, “Fundamentals of Digital Logic with Verilog Design”, 3rd
Edition, McGraw-Hill (Unit V)

REFERENCE BOOKS:

1. Charles H. Roth, Jr, “Fundamentals of Logic Design”, 4th Edition, Jaico Publishers.
2. ZviKohavi and NirajK.Jha, “Switching and Finite Automata Theory, 3rd Edition, Cambridge
University Press, 2010.
3. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, 2 ndEdition, Prentice Hall
PTR.
4. D.P. Leach, A.P. Malvino, “Digital Principles and Applications”, TMH, 7th Edition.

ONLINE LEARNING RESOURCES:

1. https://www.youtube.com/watch?v=BqP6sVYlrr0
2. https://archive.nptel.ac.in/courses/106/105/106105165/
3. https://onlinecourses.nptel.ac.in/noc22_ee55/preview

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II B.TECH I SEM – ECE-DIGITAL CIRCUITS DESIGN UNIT-II

UNIT - II

Combinational Logic Circuits Combinational circuits, Design with basic logic gates,
design procedure, adders, subtractors, 4-bit binary adder/ subtractor circuit, BCD adder,
carry look- a-head adder, binary multiplier, magnitude comparator, data selectors, priority
encoders, decoders, multiplexers, demultiplexers.
.
Introduction: Logic circuit may be classified into two categories

1. Combinational logic circuits

2. Sequential logic circuits

A combinational logic circuit contains logic gates only but does not contain storage
elements. A sequential logic circuit contains storage elements in addition to logic gates.
When logic gates are connected together to give a specified output for certain specified
combination of input variables, with no storage involved, the resulting network is known as
combinational logic circuit.
In combinational logic circuit the output level is at all times dependent on the combination
of input level. The block diagram is shown

Fig: Block diagram of Combinational circuit

The combinational logic circuit with memory elements(s) is called sequential logic circuit.
It consists of a combinational circuit to which memory elements are connected to form a
feedback path. The memory elements are devices, capable of storing binary information
within them. The block diagram is shown.

Fig: Block diagram of Sequential circuit

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By block diagram, it can be said that the output(s) of sequential logic circuit is (are)
dependent not only on external input(s) but also on the present state of the memory
element(s). The next state of the memory element(s) is also dependent on external input
and the present state.

DESIGNING COMBINATORIAL CIRCUITS (PROCEDURE):

The design of a combinational circuit starts from the verbal outline of the problem and
ends with a logic circuit diagram or a set of Boolean functions from which the Boolean
function can be easily obtained. The procedure involves the following steps:
• The problem is stated
• The number of available input variables and required output variables is determined.
• The input and output variable are assigned their letter symbol
• The truth table that defines the required relationship between the inputs and the outputs
is derived.
• The simplified Boolean function for each output is obtained
• The logic diagram is drawn.

Design with basic logic gates

Example: Design a combinational logic circuit with three inputs, the output is at logic 1
when more than one inputs are at logic 1.

Solution: Assume A, B, C are inputs and Y is output.

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Example of combinational circuit

Adder
The Basic operation in digital computer is binary addition. The circuit which
perform the addition of binary bits are called as Adder.

The logic circuit which performs the addition of two bit is called Half adder and three bit
is called Full adder.
Rules for two bit addition

0+0=0
0+1=1
1+0=1
1 + 1 = 102

HALF ADDER
A half adder is a logical circuit that performs an addition operation on two binary digits.
The half adder produces a sum and a carry value which are both binary digits.

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FULL ADDER
The three inputs of the full adders are augend, addend and the carry input fromthe
previous addition, the outputs are sum and carry.
Block diagram of Full adder

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The Full Adder can be implement using Two Half Adders and OR gates
The expression for sum is

The Expression for carry is

Logic Diagram

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Subtractor
Subtractor is the logic circuit which is used to subtract two binary number (digit)
and provides Difference and Borrow as a output. In digital electronics we have two
types of subtractor, Half Subtractor and Full Subtractor.

Rules for two bit addition

0-0=0
0 - 1 = 1 with borrow 1
1-0=1
1-1=0

HALF SUBTRACTOR:
Half Subtractor is used for subtracting one single bit binary digit from another single bit
binary digit. The truth table of Half Subtractor is shown below.

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FULL SUBTRACTOR:
A logic Circuit Which is used for Subtracting Three Single bit Binary digit
is known as Full Subtractor. The inputs are A,B, Bin and the outputs are D and Bout.

We can further simplify the function of the Difference (D)

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Simplified Logic diagram

Fig: Full subtractor using two Half Subtractors and one OR Gate

Parallel Adder – Subtractor

FOUR BIT PARALLEL BINARY ADDER

In practical situations it is required to add two data each containing more than one
bit. Two binary numbers each of n bits can be added by means of a full adder circuit.
Consider the example that two 4-bit binary numbers B 4B 3B 2B 1 and A 4A 3A 2A1 are to
be added with a carry input C 1. This can be done by cascading four full adder circuits. The
least significant bits A 1, B 1, and C 1 are added to the produce sum output S1 and carry
output C 2. Carry output C 2 is then added to the next significant bits A2 and B2 producing
sum output S 2 and carry output C 3. C 3 is then added to A3 and B3 and so on. Thus finally
producing the four-bit sum output S 4S 3S 2S 1 and final carry output Cout.

Fig. Block diagram of 4 bit binary parallel Adder

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FOUR BIT PARALLEL BINARY SUBTRACTOR

We can design a four bit parallel subtractor by connecting three full subtractors and onehalf
subtractor. In the figure A = A3 A2 A1 A0 is minuend B = B3 B2 B1 B0 is subtrahend giving
the difference D = D3 D2 D1 D0.

Fig. Block diagram of 4 bit binary parallel Subtractor

The subtraction operation can be performed using 1’s and 2’s complement addition, so we
can design Full subtractor using Full Adder.

Fig. Four bit binary subtractor using Full Adder

PARALLEL BINARY ADDER – SUBTRACTOR
The addition and subtraction operations can be perform using a common adder circuit,
where a EX-OR gate is connected in the second input along with the mode selection bit M.
if M=0 the circuit act as a adder, M=1 then substractor. If M=0 then output of the EX-OR
gate is B act as adder, if M=1 then B’ act as a subtractor.

Fig:4 bit Parallel binary Adder – Subtractor

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CARRY LOOK AHEAD ADDER

In the parallel adder the carry input of each stage is depends on the carry output of
the previous stage. This processes leads to time delay in addition. This delay is called
propagation delay. The process can be speeding up by eliminating the inter stage carry
delay called look ahead carry addition. In uses two functions carry generate and carry
propagate.

Fig. Full Adder Circuit

The output sum and carry can be expressed as

Gi is called carry generate and Pi is called carry propagate.

The Boolean function for the carry output of each stage can be

From the above functions it can be seen that C4 does not have to wait for C3 andC2. All the
carries are propagating at the same time.

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Fig: Logic diagram of a look-ahead carry generator

BCD ADDER

In digital system, the decimal number is represented in the form of binary coded
decimal (BCD).The ten digit (0-9) decimal numbers are represented by the binary digits.
The circuit which add the two BCD number is called BCD adder. The BCD cannot be
greater than 9. The representation of the BCD number as follows, consider the 526 itcan

be expressed as
There are three different cases in BCD Addition
i) Sum is less than or equal to 9 with carry 0

Consider the addition of two BCD numbers 6 and 3, The addition is performed as

normal binary addition

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ii) Sum is greater than 9 with carry 0

consider the number 6 and 8 in BCD

The sum is invalid BCD number, Add the sum with correction number 6

After addition of 6 carry is produced into the second decimal position.

iii) Sum equals 9 or less with carry 1

Consider the addition of 8 and 9 in BCD

The result 0001 0001 is valid BCD number but it is incorrect. Add 6 to get correct
number.

The procedure for BCD addition is

1. Add two BCD numbers using ordinary binary addition.
2. If four bit sum is less than or equal to zero, then correction is needed.
3. If the four bit sum is greater than 9 or if carry is generated then add 0110.

Implementation of BCD Adder

We require 4-bit binary adder for initial addition, Logic circuit to detect sum greater than 9,
andsecond 4 bit binary adder to add 0110.
The following truth table is used to design a circuit for the sum, which is greater than 9

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Inputs Output K map for carry (Y)

S S S S identification
Y
3 2 1 0
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0 Y = S3S2 + S3S1
1 0 0 0 0
1 0 0 1 0 If Y=1 add 0110 using
1 0 1 0 1 binary adder
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Block diagram of BCD adder

Fig. Block diagram of BCD adder

The binary adder add two BCD numbers, ifcarry is ‘0’ nothing to be added. If carry is
‘1’ add 0110 with the sum, consider the overall carry from the first stage of the addition.

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Magnitude Comparator
Definition:
A magnitude comparator is a combinational circuit that compares two numbers A & B to
determine whether:
A > B, orA = B, orA < B

1-BIT MAGNITUDE COMPARATOR:

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2-BIT MAGNITUDE COMPARATOR:

Fig: Block diagram of 2-bit comparator

Truth Table:

Boolean expression for outputs:

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Logic Diagram:

4-BIT MAGNITUDE COMPARATOR :

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Logic diagram

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Decoder:
Decoder is a combinational circuit. It has N inputs and 2N outputs.

2 TO 4 DECODER:
It has 2 inputs and 22 = 4 outputs.
Block Diagram

Truth Table

Logic Diagram

2 to 4 Decoder with Enable input

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Truth Table

Logic Diagram

3 TO 8 DECODER:

It has 3 inputs and 23 = 8 outputs.

Block diagram:

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Digital Circuit Design

Truth Table:

Logic Diagram

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Digital Circuit Design

Encoders

Encoders is a combinational circuit which takes 2N inputs and gives out N outputs, the
enable pin should be kept 1 for enabling the circuit.

4 TO 2 ENCODER:

It has 22 inputs and 2 outputs.

Block diagram:

Truth table:

Logic diagram:

PRIORITY ENCODERS

A Priority Encoder works opposite of the decoder circuit. If more than one input isactive,
the higher order input has priority.

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Digital Circuit Design

4 TO 2 PRIORITY ENCODERS

D0-D3 - inputsA1,A0 – outputs

Active (A)– Valid indicator. It indicates the output is valid or notOutput is invalid when no

inputs are active .i.e, A=0

Output is valid when at least one input is active .i,e, A=1

K-map simplification

Logic Diagram

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Digital Circuit Design

3 TO 8 PRIORITY ENCODER
Block diagram:

Implementation Table:

Mutliplexer (Mux)

Multiplexer is a combinational circuit that selects binary information from one of many
inputs and directs it into single output.

The selection of particular input is controlled by a set of selection line. Mutliplexer has 2n

inputs, n select line (control input) and one output.

It also called as Data selector

2 TO 1 MULTIPLEXER:

has 21 inputs, 1 select line and one output

Circuit diagram

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Digital Circuit Design

4 TO 1 MULTIPLEXER:

4 to 1 MUX has 22 = 4 inputs, 2 select line and one output

8 to1 MULTIPLEXER:

8 to1 MUX has 23 = 8 inputs, 3 select line and one output

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Digital Circuit Design

Example: Implement the following Boolean function using 4:1 MUX

F(x,y,z) = Σm(1, 2, 6, 7)

Solution:
Truth Table Multiplexer Implementation

Example 2: Implement the following Boolean function using 8:1 MUX

F(A,B,C,D) = Σm(1, 3, 4, 11,12-15)

Solution:

Multiplexer Implementation

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Digital Circuit Design

Demultiplexer (DEMUX)

Demultiplexer has 2n outputs , n select lines, one input.A demultiplexer is also called a

data distributor.

1-TO-2 DEMULTIPLEXER
has 22 outputs , 2 select lines, one input.
Block diagram:

Truth table:

Logic diagram:

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1-TO-4 DEMULTIPLEXER

It has one input,2 select lines,4 outputs

Block diagram:

Truth table : Boolean expression

Logic Diagram

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1-TO-8 DEMULTIPLEXER
It has one input3-select lines 8-outputs

Block diagram:

Truth table

Boolean expression for all outputs

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Digital Circuit Design

Logic Diagram

1-to-8 DEMUX using Two 1-to- 4 Demultiplexers

1- to-8 demultiplexer can be implemented by using two 1-to-4 demultiplexers with aproper
cascading.

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Digital Circuit Design

In the above figure, the highest significant bit A of the selection inputs are connected to the
enable inputs such that it is complemented before connecting to one DEMUX and to the
other it is directly connected. By this configuration, when A is set to zero, one of the output
lines from Y0 to Y3 is selected based on the combination of select lines B and C. Similarly,
when A is set to one, based on the select lines one of the output lines from Y4 to Y7 will be
selected.

Applications of Demultiplexer

 Synchronous data transmission systems

 Boolean function implementation (as we discussed full subtractor function above)
 Data acquisition systems
 Combinational circuit design
 Automatic test equipment systems
 Security monitoring systems (for selecting a particular surveillance camera at a
time), etc.

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