ASM Charts, Sequence detector
Serial Adder, ASMD Charts
Nagaraj Bhat
Introduction
State box
Decision box & Conditional box
ASM example
Mapping of ASM Blocks
Invalid ASM block having nonunique
next states
Looping
• Any closed loop must contain at least one
state box
Another Looping Example
• Any closed loop must contain at least one
state box
Linked State Machines
Rules to be followed
STG to ASM
Sequence Detector
• A sequence detector is a sequential state machine which takes an
input string of bits and generates an output 1 whenever the target
sequence has been detected. There are two ways in which
sequence detector circuit can be designed
Moore Machine
Mealy Machine
• Sequence detector is of two types
Overlapping
Non Overlapping
For non overlapping case of 101 sequence detector
Input : 0110101011001
Output :0000100010000
For overlapping case of 101 sequence detector
Input : 0110101011001
Output :0000101010000
FSM
Steps to be followed
• Understand the problem statement
• Determine the inputs and outputs
• Draw state diagram
• Perform state minimization (If possible)
• Perform state and output encoding in binary
form
• Write verilog or VHDL code
• Simulate FSM
Creating ASM charts
ASM CHART From State Diagram
Verilog code
module seqdetector (
input a,
input clk,
input reset,
output reg q );
parameter S0=2'b00,
S1=2'b01,
S2=2'b10;
reg [1:0] PS,NS;
Verilog code
always @ (PS,a)
case (PS)
S0 : if(a) NS=S1;
else NS=S0;
S1: if(a) NS=S1;
else NS=S2;
S2: if(a) NS=S1;
else NS=S0;
default: NS=S0;
endcase
Verilog code
always @ (posedge clk)
if(reset) PS<= S0;
else PS<= NS;
always @ (PS,a)
case (PS)
S0 : q=1'b0;
S1 : q=1'b0;
S2: if(a) q=1'b1;
else q=1'b0;
default: q=1'b0;
endcase
endmodule
Moore Sequence detector Problem
statement
State diagram of Moore FSM
Verilog code
Verilog code
Verilog code
Verilog code
Verilog code
Example : Home Work
Serial Adder
Operation of 4 bit Serial Adder
Operation of 8 Bit Serial Adder
Considering the states
State Diagram
Ci/PS Qa[0] Qb[0] Sum/ Ci+1/NS
Output
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Verilog Code for Serial Adder
module serial_adder ( A,B, reset, clock, sum);
input [7:0] A,B;
input reset,clock;
output [7:0] sum;
reg [3:0] count;
reg s;
reg PS,NS;
wire [7:0] qa,qb,sum;
wire run;
parameter G=0,H=1;
Verilog Code for Serial Adder cont…
shiftrne shift_A (A,reset,1'b1,1'b0,clock,qa);
shiftrne shift_B (B,reset,1'b1,1'b0,clock,qb);
shiftrne shift_sum (8'b0,reset,run,s,clock,sum);
Declarations for 3 Shift Registers
Verilog Code for Serial Adder cont…
• Using State Diagram
//adder fsm G: begin H: begin
//output and next state s = qa[0]^qb[0]; // output logic s = qa[0] ~^qb[0]; // xnor
combinational circuit
// next state logic if (~qa[0] & ~qb[0])//nor
always @(qa or qb or PS) gate
if (qa[0] & qb[0]) NS=G;
case (PS)
NS = H; else
else NS= H;
NS = G; end
end default : NS = G;
endcase
Verilog Code for Serial Adder cont…
//sequential block always @(posedge clock)
always @(posedge clock) if (reset)
if (reset) count = 8;
PS <= G; else if (run) count = count - 1;
else assign run= |count;
PS <= NS; // count=0000 , run=0
//control the shifting process endmodule
// Assignment of States
//Counter for 8 iterations
Verilog Code for Serial Adder cont…
• SHIFT REGISTER MODULE
// shift register
module shiftrne ( R,L,E,w,clock,q); always @(posedge clock)
parameter n=8; if (L)
input [n-1:0] R; q <= R;
input L,E,w,clock; else if (E) q<={w,q[7:1]}
output [n-1:0] q;
endmodule
reg [n-1:0] q;
ASMD Charts
How Small companies Operate?
How big Companies Operate?
ASMD based design partitioning
ASMD based Design
ASMD example: Traffic light Controller
Step-1 Design Specifications
Design Partitioning
Design Partitioning
Data Path Design
How to think Data Path?
Common Functionalities and
Components
Data Path
Draw block diagram clearly mark I/Os
Stitching of data path together
Figuring Control and Status s/g to TLC
ASMD of Control unit
How to design Control Unit?
TLC Control unit Design
Coding data path
CODE
Multiplication by Repeated Addition
Data Path
Data path & Control Path
Control Path
Data Path Code
Code
Counter
Control Path
Control Path
Test Bench
Example2: GCD Computation
Data Path
Control path and Data Path
Control Path
Code Data Path
Control Path
Code
Code
