TU Microprocessor Exam Preparation:

8085 Interfacing Solutions

Introduction to 8085 Memory and I/O Interfacing

The Intel 8085 is an 8-bit microprocessor widely used in embedded systems and
educational settings due to its relatively simple architecture and comprehensive
instruction set. A fundamental aspect of designing systems around the 8085 involves
interfacing it with various memory and input/output (I/O) devices. This process,
known as memory and I/O mapping, ensures that the microprocessor can correctly
access data from memory and communicate with peripheral devices.

8085 Addressing Capabilities

The 8085 microprocessor has a 16-bit address bus, enabling it to address up to 2^16 =
65,536 (64KB) unique memory locations. This address space is typically divided
between Read-Only Memory (ROM) and Random Access Memory (RAM). ROM is used to
store permanent programs and data, such as the boot-up routines or fixed lookup
tables, while RAM is used for temporary data storage and program execution. The 8085
uses a multiplexed address/data bus (AD0-AD7), where the lower 8 bits of the address
are time-multiplexed with the data bus. The higher 8 bits of the address (A8-A15) are
dedicated address lines.

Memory Interfacing

Memory interfacing involves connecting memory chips to the 8085 such that the
microprocessor can read from and write to specific memory locations. This requires
careful consideration of address decoding, which is the process of generating chip
select (CS) signals for memory devices based on the address lines from the
microprocessor. Decoders, such as the 74LS138 (a 3-to-8 line decoder), are commonly
used for this purpose. The 74LS138 takes three address lines as input and activates
one of its eight output lines, allowing for the selection of up to eight different memory
or I/O devices.
I/O Interfacing

I/O interfacing allows the 8085 to communicate with external peripheral devices like
keyboards, displays, sensors, and actuators. The 8085 supports two primary methods
for I/O interfacing:

1. Memory-Mapped I/O: In this scheme, I/O devices are treated as memory

locations. The 8085 uses its full 16-bit address bus to access I/O ports, and
memory read/write instructions (e.g., LDA , STA ) are used for I/O operations.
This approach simplifies the instruction set but reduces the available memory
address space.

2. I/O-Mapped I/O (Peripheral-Mapped I/O): This is the more common approach

for the 8085. It uses a separate 8-bit I/O address space (256 unique I/O ports) and
dedicated I/O instructions ( IN and OUT ). The IO/M (Input/Output/Memory)
signal from the 8085 distinguishes between memory and I/O operations. When
IO/M is high, it indicates an I/O operation, and the 8-bit address on AD0-AD7 is
used to select the I/O port.

Address Decoding Techniques

Effective address decoding is crucial for preventing address conflicts and ensuring that
each memory or I/O device responds only to its assigned address range. Common
decoding techniques include:

Full Decoding: Every address line is used in the decoding process, ensuring that
each memory or I/O location has a unique address. This provides the most
efficient use of the address space but requires more complex decoding logic.

Partial Decoding: Only a subset of the address lines is used for decoding. This
simplifies the decoding circuit but results in multiple physical memory locations
mapping to the same logical address (mirroring). While less efficient in terms of
address space utilization, it is often used for smaller systems where simplicity is
prioritized.

Block Decoding: This technique is often used for I/O devices where a block of
addresses is assigned to a group of I/O ports. A decoder, like the 74LS138, can be
used to select a block, and then lower address lines can select individual ports
within that block.
This document will provide detailed solutions to various 8085 interfacing problems,
covering both memory and I/O interfacing scenarios, and demonstrating the
application of different address decoding techniques, including the use of the 74LS138
decoder.

Solutions to Exam Questions

Q16. Design an interfacing circuit for 8085 using 3:8 decoder

(74LS138) for:

a) 4KB ROM and 2KB RAM starting at address C000H

Explanation:

To interface 4KB ROM and 2KB RAM with the 8085 microprocessor starting at address
C000H, we need to perform address decoding to generate chip select signals for both
memory devices. The 74LS138 (3-to-8 line decoder) will be used for this purpose.

First, let's determine the address ranges for the ROM and RAM:

4KB ROM:

4KB = 4 * 1024 bytes = 4096 bytes.

Since 2^12 = 4096, we need 12 address lines (A0-A11) to address 4KB of

memory.

Starting address: C000H (1100 0000 0000 0000 in binary)

Ending address: C000H + 4096 - 1 = CFFFH (1100 1111 1111 1111 in binary)

Address range for ROM: C000H - CFFFH

2KB RAM:

2KB = 2 * 1024 bytes = 2048 bytes.

Since 2^11 = 2048, we need 11 address lines (A0-A10) to address 2KB of

memory.

The RAM should start immediately after the ROM, so its starting address will
be D000H (1101 0000 0000 0000 in binary).

Ending address: D000H + 2048 - 1 = D7FFH (1101 0111 1111 1111 in binary)
 Address range for RAM: D000H - D7FFH

Now, let's analyze the address lines to determine the inputs for the 74LS138 decoder.
The 8085 has 16 address lines (A0-A15). We need to find the common higher-order
address bits that distinguish between the ROM and RAM blocks.

Address Line ROM (C000H - CFFFH) RAM (D000H - D7FFH)

A15 1 1

A14 1 1

A13 0 0

A12 0 1

A11 X X

... ... ...

A0 X X

From the table, we can see that A15, A14, and A13 are common for both, but A12
changes from 0 (for ROM) to 1 (for RAM). This suggests that A12 can be used as one of
the inputs to the 74LS138. We need two more higher-order address lines to feed into
the 74LS138. Let's consider A15, A14, and A13.

If we use A15, A14, and A13 as inputs to the 74LS138, the output for C000H (1100...)
would be based on 110 (binary for 6), and for D000H (1101...) would be based on 110
(binary for 6) as well, which is not unique. Therefore, we need to use address lines that
provide unique combinations for the desired address ranges.

Let's use A15, A14, and A13 as the inputs (C, B, A respectively) to the 74LS138. The
active low outputs of the 74LS138 will be used as chip select signals.

For the address range C000H - CFFFH (ROM), the higher address bits are 1100. If we use
A15, A14, A13 as inputs to 74LS138, this corresponds to input 110 (binary for 6). So,
output Y6 will be active low for this range.

For the address range D000H - D7FFH (RAM), the higher address bits are 1101. If we use
A15, A14, A13 as inputs to 74LS138, this corresponds to input 110 (binary for 6). This is
still not unique. This means we need to use A12 as one of the inputs to the decoder.
Let's reconsider. The 74LS138 has three select inputs (A, B, C) and eight active-low
outputs (Y0-Y7). We need to select three address lines that will uniquely identify the
ROM and RAM blocks.

Given the starting address C000H (1100 0000 0000 0000) and D000H (1101 0000 0000
0000):

ROM (C000H - CFFFH): A15=1, A14=1, A13=0, A12=0

RAM (D000H - D7FFH): A15=1, A14=1, A13=0, A12=1

We can use A14, A13, and A12 as the inputs to the 74LS138 (A14 as C, A13 as B, A12 as
A). A15 must be high for both. So, A15 will be used as an enable for the 74LS138.

74LS138 Inputs: * C = A14 * B = A13 * A = A12

Enable Inputs: * G1 = A15 (active high enable) * G2A = IO/M (active low enable, for
memory operations) * G2B = RD (active low enable, for read operations, connected to
ROM and RAM for read)

Let's check the outputs:

For ROM (C000H - CFFFH): A14=1, A13=0, A12=0. This corresponds to binary 100,
which is decimal 4. So, Y4 will be active low.

For RAM (D000H - D7FFH): A14=1, A13=0, A12=1. This corresponds to binary 101,
which is decimal 5. So, Y5 will be active low.

This setup provides unique chip select signals for ROM and RAM.

Circuit Design:

Connect 8085's A15 to G1 of 74LS138.

Connect 8085's A14 to C input of 74LS138.

Connect 8085's A13 to B input of 74LS138.

Connect 8085's A12 to A input of 74LS138.

Connect 8085's IO/M (active low) to G2A of 74LS138.

Connect 8085's RD (active low) to G2B of 74LS138.

Connect Y4 output of 74LS138 to the Chip Select (CS) of the 4KB ROM.

Connect Y5 output of 74LS138 to the Chip Select (CS) of the 2KB RAM.
 Connect 8085's A0-A11 to the address lines of the 4KB ROM.

Connect 8085's A0-A10 to the address lines of the 2KB RAM.

Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of both ROM
and RAM.

Connect 8085's WR (active low) to the Write Enable (WE) of the 2KB RAM.

Diagram:

[Diagram for Q16a will be inserted here. It will show the 8085, 74LS138, 4KB ROM, and
2KB RAM with all necessary connections.]

b) One PROM of 4K8, one EEPROM of 2K8 and one SRAM of 8K*8 starting at 3000H

Explanation:

To interface one 4K8 PROM, one 2K8 EEPROM, and one 8K*8 SRAM with the 8085
microprocessor, all starting at address 3000H, we need to carefully map their
addresses and use the 74LS138 decoder for chip selection. The total memory required
is 4KB + 2KB + 8KB = 14KB. Since the 8085 has a 64KB address space, this is well within
its capabilities.
Let's determine the address ranges for each memory device:

4K*8 PROM:

4KB = 4096 bytes. Requires A0-A11.

Starting address: 3000H (0011 0000 0000 0000 in binary)

Ending address: 3000H + 4096 - 1 = 3FFFH (0011 1111 1111 1111 in binary)

Address range for PROM: 3000H - 3FFFH

2K*8 EEPROM:

2KB = 2048 bytes. Requires A0-A10.

Starting address: 3FFFH + 1 = 4000H (0100 0000 0000 0000 in binary)

Ending address: 4000H + 2048 - 1 = 47FFH (0100 0111 1111 1111 in binary)

Address range for EEPROM: 4000H - 47FFH

8K*8 SRAM:

8KB = 8192 bytes. Requires A0-A12.

Starting address: 47FFH + 1 = 4800H (0100 1000 0000 0000 in binary)

Ending address: 4800H + 8192 - 1 = 67FFH (0110 0111 1111 1111 in binary)

Address range for SRAM: 4800H - 67FFH

Now, let's analyze the higher-order address lines to determine the inputs for the
74LS138 decoder. We need to find common and distinguishing bits.

Address Line PROM (3000H-3FFFH) EEPROM (4000H-47FFH) SRAM (4800H-67FFH)

A15 0 0 0

A14 0 1 1

A13 1 0 0

A12 1 0 1

From the table, A15 is always 0. This can be used as an enable for the 74LS138. The
lines A14, A13, and A12 show distinct patterns for each memory block. We can use
these as the select inputs for the 74LS138.
74LS138 Inputs: * C = A14 * B = A13 * A = A12

Enable Inputs: * G1 = Not used (or tied high if not needed for additional decoding) *
G2A = A15 (active low enable, since A15 is 0 for all ranges) * G2B = IO/M (active low
enable, for memory operations)

Let's check the outputs based on A14, A13, A12:

For PROM (3000H - 3FFFH): A14=0, A13=1, A12=1. This corresponds to binary
011, which is decimal 3. So, Y3 will be active low.

For EEPROM (4000H - 47FFH): A14=1, A13=0, A12=0. This corresponds to binary
100, which is decimal 4. So, Y4 will be active low.

For SRAM (4800H - 67FFH): A14=1, A13=0, A12=1. This corresponds to binary
101, which is decimal 5. So, Y5 will be active low.

This setup provides unique chip select signals for PROM, EEPROM, and SRAM.

Circuit Design:

Connect 8085's A15 to G2A of 74LS138 (since A15 is 0 for all ranges, it acts as an
active low enable).

Connect 8085's A14 to C input of 74LS138.

Connect 8085's A13 to B input of 74LS138.

Connect 8085's A12 to A input of 74LS138.

Connect 8085's IO/M (active low) to G2B of 74LS138.

Connect 8085's RD (active low) to the Read Enable (RE) of PROM, EEPROM, and
SRAM.

Connect 8085's WR (active low) to the Write Enable (WE) of EEPROM and SRAM.

Connect Y3 output of 74LS138 to the Chip Select (CS) of the 4K*8 PROM.

Connect Y4 output of 74LS138 to the Chip Select (CS) of the 2K*8 EEPROM.

Connect Y5 output of 74LS138 to the Chip Select (CS) of the 8K*8 SRAM.

Connect 8085's A0-A11 to the address lines of the 4K*8 PROM.

Connect 8085's A0-A10 to the address lines of the 2K*8 EEPROM.

Connect 8085's A0-A12 to the address lines of the 8K*8 SRAM.

 Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of PROM,
EEPROM, and SRAM.

Diagram:

[Diagram for Q16b will be inserted here. It will show the 8085, 74LS138, 4K8 PROM, 2K8
EEPROM, and 8K*8 SRAM with all necessary connections.]

c) Two 8KB EPROM blocks and one 4KB RAM block starting at 50A0H

Explanation:

To interface two 8KB EPROM blocks and one 4KB RAM block with the 8085
microprocessor, starting at address 50A0H, we need to carefully assign their address
ranges and use a suitable decoder. The total memory required is 8KB + 8KB + 4KB =
20KB.

Let's determine the address ranges for each memory device. Since the starting address
is 50A0H, which is not a power-of-2 boundary, we will align the blocks to the next
available power-of-2 boundary for simpler decoding. The smallest power-of-2
boundary greater than or equal to 50A0H is 5000H (if we consider 4KB blocks) or 4000H
(if we consider 8KB blocks). Given the sizes, it's better to align to 4000H or 5000H for
simplicity in decoding. However, the question states

starting at 50A0H. This means we will have to use partial decoding or a more complex
decoding scheme if we strictly adhere to 50A0H. For simplicity and typical exam
solutions, it's common to adjust the starting address to a convenient boundary if not
explicitly forbidden. However, if we must start at 50A0H, it implies that the higher
address bits will be fixed, and the lower bits will vary. Let's assume for simplicity that
the starting address implies the beginning of the first block and subsequent blocks
follow contiguously.

Given the starting address 50A0H, let's analyze the address space: 50A0H = 0101 0000
1010 0000 in binary.

This starting address is not aligned to an 8KB or 4KB boundary. If we strictly adhere to
50A0H, the decoding becomes more complex, often requiring additional logic gates
(AND, OR, NAND) in conjunction with the decoder. However, in typical 8085 interfacing
problems, if a non-aligned starting address is given, it often implies that the first byte
of the first memory block starts there, and the rest of the block fills up from that point.
For simplicity in decoding with a 74LS138, it's usually assumed that the blocks are
aligned to their natural boundaries (e.g., 8KB blocks start at addresses divisible by
8KB).

Let's assume the question implies that the block containing 50A0H is the starting
point, and we can align the blocks to the nearest convenient boundary for simpler
decoding with a 74LS138. A common practice in such scenarios is to use the given
address as a reference for the chip select logic, rather than forcing the entire block to
start exactly at that unaligned address. For instance, if 50A0H falls within an 8KB block,
that 8KB block would be selected when the address is within its range.

Let's consider a scenario where the blocks are aligned to their natural boundaries, and
the 50A0H is part of the first 8KB EPROM block. This simplifies the decoding
significantly. We will assume the first 8KB EPROM block starts at 4000H, the second
8KB EPROM block starts at 6000H, and the 4KB RAM block starts at 8000H. This is a
common interpretation for exam questions to allow for straightforward 74LS138
usage. If strict adherence to 50A0H is required, the solution would involve more
complex logic beyond a single 74LS138.

Revised Address Ranges (for simpler 74LS138 decoding, assuming alignment):

 First 8KB EPROM:

8KB = 8192 bytes. Requires A0-A12.

Let's assume it starts at 4000H (0100 0000 0000 0000 in binary).

Ending address: 4000H + 8192 - 1 = 5FFFH (0101 1111 1111 1111 in binary)

Address range: 4000H - 5FFFH

Second 8KB EPROM:

8KB = 8192 bytes. Requires A0-A12.

Starts immediately after the first EPROM: 6000H (0110 0000 0000 0000 in
binary).

Ending address: 6000H + 8192 - 1 = 7FFFH (0111 1111 1111 1111 in binary)

Address range: 6000H - 7FFFH

4KB RAM:

4KB = 4096 bytes. Requires A0-A11.

Starts immediately after the second EPROM: 8000H (1000 0000 0000 0000 in
binary).

Ending address: 8000H + 4096 - 1 = 8FFFH (1000 1111 1111 1111 in binary)

Address range: 8000H - 8FFFH

Now, let's analyze the higher-order address lines for the 74LS138 decoder:

Address 1st EPROM (4000H- 2nd EPROM (6000H- RAM (8000H-

Line 5FFFH) 7FFFH) 8FFFH)

A15 0 0 1

A14 1 1 0

A13 0 1 0

We can use A15, A14, and A13 as the inputs to the 74LS138 (A15 as C, A14 as B, A13 as
A). We will also need to ensure that the IO/M signal is low for memory operations.

74LS138 Inputs: * C = A15 * B = A14 * A = A13

Enable Inputs: * G1 = Not used (or tied high) * G2A = IO/M (active low enable, for
memory operations) * G2B = Not used (or tied low)

Let's check the outputs based on A15, A14, A13:

For 1st EPROM (4000H - 5FFFH): A15=0, A14=1, A13=0. This corresponds to
binary 010, which is decimal 2. So, Y2 will be active low.

For 2nd EPROM (6000H - 7FFFH): A15=0, A14=1, A13=1. This corresponds to
binary 011, which is decimal 3. So, Y3 will be active low.

For RAM (8000H - 8FFFH): A15=1, A14=0, A13=0. This corresponds to binary 100,
which is decimal 4. So, Y4 will be active low.

This setup provides unique chip select signals for the two EPROMs and the RAM.

Circuit Design:

Connect 8085's A15 to C input of 74LS138.

Connect 8085's A14 to B input of 74LS138.

Connect 8085's A13 to A input of 74LS138.

Connect 8085's IO/M (active low) to G2A of 74LS138.

Connect 8085's RD (active low) to the Read Enable (RE) of both EPROMs and the
RAM.

Connect 8085's WR (active low) to the Write Enable (WE) of the 4KB RAM.

Connect Y2 output of 74LS138 to the Chip Select (CS) of the first 8KB EPROM.

Connect Y3 output of 74LS138 to the Chip Select (CS) of the second 8KB EPROM.

Connect Y4 output of 74LS138 to the Chip Select (CS) of the 4KB RAM.

Connect 8085's A0-A12 to the address lines of both 8KB EPROMs.

Connect 8085's A0-A11 to the address lines of the 4KB RAM.

Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of both
EPROMs and the RAM.

Diagram:

[Diagram for Q16c will be inserted here. It will show the 8085, 74LS138, two 8KB
EPROMs, and one 4KB RAM with all necessary connections.]
Q17. Design address decoding interface for input/output ports:

a) Input port and output port at FAH and F8H using 74LS138 decoder

Explanation:

For I/O-mapped I/O in the 8085, the IO/M signal is high, indicating an I/O operation.
The 8-bit I/O address is placed on the AD0-AD7 lines. We need to decode the addresses
FAH (Input Port) and F8H (Output Port) using a 74LS138 decoder.

First, let's convert the I/O addresses to binary:

Input Port (FAH): 1111 1010 (binary)

Output Port (F8H): 1111 1000 (binary)

The 74LS138 is a 3-to-8 decoder. We need to select three address lines from AD0-AD7 to
feed into the decoder. Let's look at the common and distinguishing bits:
 Address Line Input Port (FAH) Output Port (F8H)

A7 1 1

A6 1 1

A5 1 1

A4 1 1

A3 1 1

A2 0 0

A1 1 0

A0 0 0

From the table, A7-A3 are all 1s. A2, A1, and A0 show variations. We can use A2, A1, and
A0 as the inputs to the 74LS138.

74LS138 Inputs: * C = A2 * B = A1 * A = A0

Enable Inputs: For I/O decoding, the IO/M signal (active high for I/O) and the higher
address lines (A7-A3) that are common and fixed can be used as enable signals for the
74LS138. We can use a NAND gate to combine A7, A6, A5, A4, A3 and the IO/M signal to
generate an overall enable for the 74LS138.

Let's assume we use a NAND gate to combine A7, A6, A5, A4, A3. The output of this
NAND gate will be low only when all these inputs are high. This output, along with the
IO/M signal, can enable the 74LS138.

Alternatively, we can use the common higher address bits (A7-A3) as part of the enable
logic for the 74LS138. Since all of them are '1' for both FAH and F8H, we can use a 5-
input AND gate (or a combination of smaller AND gates) to check if A7-A3 are all high.
The output of this AND gate, along with the IO/M signal (active high), RD (for input
port) and WR (for output port) will control the chip select.

A simpler approach for the 74LS138 enable is to use the IO/M signal (active high) as
G1, and then use a combination of the higher address lines (A7-A3) to enable G2A or
G2B. Since A7-A3 are all high (1) for both FAH and F8H, we can use a NAND gate with
inputs A7, A6, A5, A4, A3. The output of this NAND gate will be low when all these are
high, which can be connected to G2A (active low enable).

Let's refine the enable logic: * G1 = IO/M (active high) * G2A = Output of a NAND gate
with inputs A7, A6, A5, A4, A3 (active low) * G2B = Not used (or tied low)

Now, let's check the outputs based on A2, A1, A0:

For Input Port (FAH): A2=0, A1=1, A0=0. This corresponds to binary 010, which is
decimal 2. So, Y2 will be active low. This Y2 will be connected to the chip select of
the input port, and gated with RD signal.

For Output Port (F8H): A2=0, A1=0, A0=0. This corresponds to binary 000, which
is decimal 0. So, Y0 will be active low. This Y0 will be connected to the chip select
of the output port, and gated with WR signal.

Circuit Design:

Connect 8085's IO/M (active high) to G1 of 74LS138.

Connect A7, A6, A5, A4, A3 to a 5-input NAND gate. Connect the output of this
NAND gate to G2A of 74LS138.

Connect 8085's A2 to C input of 74LS138.

Connect 8085's A1 to B input of 74LS138.

Connect 8085's A0 to A input of 74LS138.

Connect Y2 output of 74LS138 to one input of a 2-input AND gate. Connect 8085's
RD (active low) to the other input of the AND gate (after inverting it to active
high). The output of this AND gate goes to the Chip Select (CS) of the Input Port.

Connect Y0 output of 74LS138 to one input of a 2-input AND gate. Connect 8085's
WR (active low) to the other input of the AND gate (after inverting it to active
high). The output of this AND gate goes to the Chip Select (CS) of the Output Port.

Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of both Input
and Output Ports.

Diagram:

[Diagram for Q17a will be inserted here. It will show the 8085, 74LS138, NAND gate,
AND gates, Input Port, and Output Port with all necessary connections.]
b) Input port at 81H and output port at 82H using block decoder

Explanation:

Block decoding is a simplified form of address decoding where a group of I/O ports is
selected by a single decoder output. In this case, we need to interface an input port at
81H and an output port at 82H. Since these addresses are close to each other, they can
be considered part of the same block.

First, let's convert the I/O addresses to binary:

Input Port (81H): 1000 0001 (binary)

Output Port (82H): 1000 0010 (binary)

We can use a simple decoder to select the block of addresses from 80H to 8FH. The
higher address bits A7-A4 are common (1000). We can use these to select the block.
The lower address bits A3-A0 can be used to select individual ports within the block.

Let's use a simple NAND gate as a block decoder. The inputs to the NAND gate will be
A7, A6, A5, and A4 (inverted). The output of the NAND gate will be low only when A7=1,
A6=0, A5=0, and A4=0, which corresponds to the 8xH address range.
Block Decoder Logic: * The block select signal will be active low when A7=1, A6=0,
A5=0, A4=0. This can be generated using a 4-input NAND gate with inputs A7,
A6(inverted), A5(inverted), A4(inverted).

Once the block is selected, we can use the lower address lines to select the specific
ports.

For Input Port (81H): The block is selected. We need to check for A0=1. The chip
select for the input port will be a combination of the block select signal, A0, and
the RD signal.

For Output Port (82H): The block is selected. We need to check for A1=1. The
chip select for the output port will be a combination of the block select signal,
A1, and the WR signal.

Circuit Design:

Connect 8085's A7, A6(inverted), A5(inverted), A4(inverted) to a 4-input NAND

gate. The output of this NAND gate is the block select signal (active low).

Connect the block select signal to one input of a 3-input AND gate. Connect A0 to
another input. Connect RD (inverted to active high) to the third input. The
output of this AND gate is the Chip Select (CS) for the Input Port at 81H.

Connect the block select signal to one input of a 3-input AND gate. Connect A1 to
another input. Connect WR (inverted to active high) to the third input. The
output of this AND gate is the Chip Select (CS) for the Output Port at 82H.

Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of both Input
and Output Ports.

Diagram:

[Diagram for Q17b will be inserted here. It will show the 8085, NAND gate, AND gates,
Input Port, and Output Port with all necessary connections.]
c) Input device with 8 switches and LED output device at 41H and 42H

Explanation:

To interface an 8-switch input device at I/O port 41H and an LED output device at I/O
port 42H with the 8085 microprocessor, we need to design an address decoding circuit.
These are I/O-mapped devices, so the IO/M signal will be high during their access.

First, let's convert the I/O addresses to binary:

Input Port (41H): 0100 0001 (binary)

Output Port (42H): 0100 0010 (binary)

We can observe the common higher-order bits and the distinguishing lower-order bits.
 Address Line Input Port (41H) Output Port (42H)

A7 0 0

A6 1 1

A5 0 0

A4 0 0

A3 0 0

A2 0 0

A1 0 1

A0 1 0

From the table, A7-A2 are common (010000). We can use these bits to generate a block
select signal. The bits A1 and A0 distinguish between 41H and 42H.

We can use a NAND gate to decode the higher address bits A7-A2. The output of this
NAND gate will be low when A7=0, A6=1, A5=0, A4=0, A3=0, A2=0. This corresponds to
the 4xH address range.

Block Decoder Logic: * A 6-input NAND gate can be used with inputs A7(inverted), A6,
A5(inverted), A4(inverted), A3(inverted), A2(inverted). The output of this NAND gate
will be active low when the address is in the 40H-43H range.

Once the block is selected, we can use A1 and A0 to select the specific port.

For Input Port (41H): The block is selected. We need to check for A1=0 and A0=1.
The chip select for the input port will be a combination of the block select signal,
A1(inverted), A0, and the RD signal.

For Output Port (42H): The block is selected. We need to check for A1=1 and
A0=0. The chip select for the output port will be a combination of the block select
signal, A1, A0(inverted), and the WR signal.

Circuit Design:

Connect 8085's IO/M (active high) to an enable input of the decoding logic.
 Use a 6-input NAND gate to decode A7(inverted), A6, A5(inverted), A4(inverted),
A3(inverted), A2(inverted). The output of this NAND gate will be the active low
block select signal for the 4xH range.

For the Input Port (8 switches at 41H):

Connect the block select signal to one input of a 3-input AND gate.

Connect 8085's A1 (inverted) to another input of the AND gate.

Connect 8085's A0 to the third input of the AND gate.

The output of this AND gate, combined with the RD signal (active low,
inverted to active high), will generate the Chip Select (CS) for the 8-switch
input device.

Connect the 8 switches to the data lines D0-D7 of the input port.

For the Output Port (LED at 42H):

Connect the block select signal to one input of a 3-input AND gate.

Connect 8085's A1 to another input of the AND gate.

Connect 8085's A0 (inverted) to the third input of the AND gate.

The output of this AND gate, combined with the WR signal (active low,
inverted to active high), will generate the Chip Select (CS) for the LED
output device.

Connect the LEDs to the data lines D0-D7 of the output port (with
appropriate current limiting resistors).

Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of both Input
and Output Ports.

Diagram:

[Diagram for Q17c will be inserted here. It will show the 8085, NAND gate, AND gates, 8-
switch Input Device, and LED Output Device with all necessary connections.]
Q18. Interface memory blocks with 8085:

a) Two 2732 (1K8) EPROM and one 6116 (2K8) RAM starting at 1000H

Explanation:

To interface two 2732 (1K8) EPROMs and one 6116 (2K8) RAM with the 8085
microprocessor, starting at address 1000H, we need to assign their address ranges and
design an appropriate decoding circuit. The 2732 is a 4KB EPROM, not 1KB. The
question states 1K8, which is 1KB. This is a common point of confusion with 2732. A
2732 EPROM is typically 4KB (4096 bytes). If it's 1K8, it means 1024 bytes. Let's assume
1K*8 as stated in the question.

2732 EPROM (1K*8):

1KB = 1024 bytes. Requires A0-A9.

Two such EPROMs are needed.

6116 RAM (2K*8):

2KB = 2048 bytes. Requires A0-A10.

Let's determine the address ranges, starting at 1000H:

First 2732 EPROM (1K*8):

Starting address: 1000H (0001 0000 0000 0000 in binary)

Ending address: 1000H + 1024 - 1 = 13FFH (0001 0011 1111 1111 in binary)

Address range: 1000H - 13FFH

Second 2732 EPROM (1K*8):

Starting address: 13FFH + 1 = 1400H (0001 0100 0000 0000 in binary)

Ending address: 1400H + 1024 - 1 = 17FFH (0001 0111 1111 1111 in binary)

Address range: 1400H - 17FFH

6116 RAM (2K*8):

Starting address: 17FFH + 1 = 1800H (0001 1000 0000 0000 in binary)

Ending address: 1800H + 2048 - 1 = 1FFFH (0001 1111 1111 1111 in binary)

Address range: 1800H - 1FFFH

Now, let's analyze the higher-order address lines to determine the decoding logic. We
can use a 74LS138 decoder for this.

Address 1st EPROM (1000H- 2nd EPROM (1400H- RAM (1800H-

Line 13FFH) 17FFH) 1FFFH)

A15 0 0 0

A14 0 0 0

A13 0 0 0

A12 1 1 1

A11 0 1 1

A10 0 0 1

From the table, A15-A12 are common (0001). This can be used as an enable for the
decoder. A11 and A10 show variations. We need three inputs for the 74LS138. We can
use A11, A10, and A9 for the 74LS138 inputs, and use A15-A12 as enable signals.
Let's use A11, A10, and A9 as inputs to the 74LS138 (A11 as C, A10 as B, A9 as A).

74LS138 Inputs: * C = A11 * B = A10 * A = A9

Enable Inputs: * G1 = A12 (active high, since A12 is 1 for all ranges) * G2A = IO/M (active
low, for memory operations) * G2B = Output of a NAND gate with inputs A15, A14, A13
(active low, since A15, A14, A13 are 0 for all ranges)

Let's check the outputs based on A11, A10, A9:

For 1st EPROM (1000H - 13FFH): A11=0, A10=0, A9=0. This corresponds to binary
000, which is decimal 0. So, Y0 will be active low.

For 2nd EPROM (1400H - 17FFH): A11=0, A10=1, A9=0. This corresponds to
binary 010, which is decimal 2. So, Y2 will be active low.

For RAM (1800H - 1FFFH): A11=1, A10=0, A9=0. This corresponds to binary 100,
which is decimal 4. So, Y4 will be active low.

This setup provides unique chip select signals for the two EPROMs and the RAM.

Circuit Design:

Connect 8085's A12 to G1 of 74LS138.

Connect 8085's A15, A14, A13 to a 3-input NAND gate. Connect the output of this
NAND gate to G2B of 74LS138.

Connect 8085's IO/M (active low) to G2A of 74LS138.

Connect 8085's A11 to C input of 74LS138.

Connect 8085's A10 to B input of 74LS138.

Connect 8085's A9 to A input of 74LS138.

Connect 8085's RD (active low) to the Read Enable (RE) of both EPROMs and the
RAM.

Connect 8085's WR (active low) to the Write Enable (WE) of the 6116 RAM.

Connect Y0 output of 74LS138 to the Chip Select (CS) of the first 2732 EPROM.

Connect Y2 output of 74LS138 to the Chip Select (CS) of the second 2732 EPROM.

Connect Y4 output of 74LS138 to the Chip Select (CS) of the 6116 RAM.

Connect 8085's A0-A9 to the address lines of both 2732 EPROMs.

Connect 8085's A0-A10 to the address lines of the 6116 RAM.

 Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of both
EPROMs and the RAM.

Diagram:

[Diagram for Q18a will be inserted here. It will show the 8085, 74LS138, two 2732
EPROMs, and one 6116 RAM with all necessary connections.]

b) Two 4K8 ROM and two 4K8 RAM with base address 2000H

Explanation:

To interface two 4K8 ROMs and two 4K8 RAMs with the 8085 microprocessor, starting
at base address 2000H, we need to assign their address ranges and design an
appropriate decoding circuit. Each 4K*8 memory chip requires 12 address lines (A0-
A11) to address its 4096 bytes.

Let's determine the address ranges, starting at 2000H:

First 4K*8 ROM:

Starting address: 2000H (0010 0000 0000 0000 in binary)

 Ending address: 2000H + 4096 - 1 = 2FFFH (0010 1111 1111 1111 in binary)

Address range: 2000H - 2FFFH

Second 4K*8 ROM:

Starting address: 2FFFH + 1 = 3000H (0011 0000 0000 0000 in binary)

Ending address: 3000H + 4096 - 1 = 3FFFH (0011 1111 1111 1111 in binary)

Address range: 3000H - 3FFFH

First 4K*8 RAM:

Starting address: 3FFFH + 1 = 4000H (0100 0000 0000 0000 in binary)

Ending address: 4000H + 4096 - 1 = 4FFFH (0100 1111 1111 1111 in binary)

Address range: 4000H - 4FFFH

Second 4K*8 RAM:

Starting address: 4FFFH + 1 = 5000H (0101 0000 0000 0000 in binary)

Ending address: 5000H + 4096 - 1 = 5FFFH (0101 1111 1111 1111 in binary)

Address range: 5000H - 5FFFH

Now, let's analyze the higher-order address lines to determine the decoding logic. We
can use a 74LS138 decoder for this.

Address 1st ROM (2000H- 2nd ROM (3000H- 1st RAM (4000H- 2nd RAM (5000H-
Line 2FFFH) 3FFFH) 4FFFH) 5FFFH)

A15 0 0 0 0

A14 0 0 1 1

A13 1 1 0 0

A12 0 1 0 1

From the table, A15 is always 0. We can use A14, A13, and A12 as the inputs to the
74LS138 (A14 as C, A13 as B, A12 as A).

74LS138 Inputs: * C = A14 * B = A13 * A = A12

Enable Inputs: * G1 = Not used (or tied high) * G2A = A15 (active low, since A15 is 0 for
all ranges) * G2B = IO/M (active low, for memory operations)

Let's check the outputs based on A14, A13, A12:

For 1st ROM (2000H - 2FFFH): A14=0, A13=1, A12=0. This corresponds to binary
010, which is decimal 2. So, Y2 will be active low.

For 2nd ROM (3000H - 3FFFH): A14=0, A13=1, A12=1. This corresponds to binary
011, which is decimal 3. So, Y3 will be active low.

For 1st RAM (4000H - 4FFFH): A14=1, A13=0, A12=0. This corresponds to binary
100, which is decimal 4. So, Y4 will be active low.

For 2nd RAM (5000H - 5FFFH): A14=1, A13=0, A12=1. This corresponds to binary
101, which is decimal 5. So, Y5 will be active low.

This setup provides unique chip select signals for all four memory blocks.

Circuit Design:

Connect 8085's A15 to G2A of 74LS138.

Connect 8085's IO/M (active low) to G2B of 74LS138.

Connect 8085's A14 to C input of 74LS138.

Connect 8085's A13 to B input of 74LS138.

Connect 8085's A12 to A input of 74LS138.

Connect 8085's RD (active low) to the Read Enable (RE) of all four memory chips.

Connect 8085's WR (active low) to the Write Enable (WE) of both RAM chips.

Connect Y2 output of 74LS138 to the Chip Select (CS) of the first 4K*8 ROM.

Connect Y3 output of 74LS138 to the Chip Select (CS) of the second 4K*8 ROM.

Connect Y4 output of 74LS138 to the Chip Select (CS) of the first 4K*8 RAM.

Connect Y5 output of 74LS138 to the Chip Select (CS) of the second 4K*8 RAM.

Connect 8085's A0-A11 to the address lines of all four memory chips.

Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of all four
memory chips.

Diagram:
[Diagram for Q18b will be inserted here. It will show the 8085, 74LS138, two 4K8 ROMs,
and two 4K8 RAMs with all necessary connections.]

c) Two RAM chips of 16KB each using suitable decoder

Explanation:

To interface two 16KB RAM chips with the 8085 microprocessor, we need to assign
their address ranges and design an appropriate decoding circuit. Each 16KB RAM chip
requires 14 address lines (A0-A13) to address its 16384 bytes.

Let's assume the RAM chips start at a convenient address, for example, 0000H for the
first chip and 4000H for the second chip. This is a common practice for such problems
to simplify decoding.

First 16KB RAM:

Starting address: 0000H (0000 0000 0000 0000 in binary)

Ending address: 0000H + 16384 - 1 = 3FFFH (0011 1111 1111 1111 in binary)

Address range: 0000H - 3FFFH

 Second 16KB RAM:

Starting address: 3FFFH + 1 = 4000H (0100 0000 0000 0000 in binary)

Ending address: 4000H + 16384 - 1 = 7FFFH (0111 1111 1111 1111 in binary)

Address range: 4000H - 7FFFH

Now, let's analyze the higher-order address lines to determine the decoding logic. We
can use a 74LS138 decoder for this.

Address Line 1st RAM (0000H-3FFFH) 2nd RAM (4000H-7FFFH)

A15 0 0

A14 0 1

We can use A14 as the input to a simple inverter or directly use it to enable the chip
select. Since we only have two blocks, a 74LS138 might be overkill, but the question
asks for a

suitable decoder, and the 74LS138 is a common choice for such problems, even if
simpler gates could suffice for just two chips. We can configure the 74LS138 to select
between the two 16KB RAM chips.

74LS138 Inputs: * A = A14 * B = 0 (tied to ground) * C = 0 (tied to ground)

Enable Inputs: * G1 = Not used (or tied high) * G2A = A15 (active low, since A15 is 0 for
both ranges) * G2B = IO/M (active low, for memory operations)

Let's check the outputs based on A14:

For 1st 16KB RAM (0000H - 3FFFH): A14=0. With B=0, C=0, this corresponds to
binary 000, which is decimal 0. So, Y0 will be active low.

For 2nd 16KB RAM (4000H - 7FFFH): A14=1. With B=0, C=0, this corresponds to
binary 001, which is decimal 1. So, Y1 will be active low.

This setup provides unique chip select signals for the two 16KB RAM chips.

Circuit Design:

Connect 8085's A15 to G2A of 74LS138.

Connect 8085's IO/M (active low) to G2B of 74LS138.

 Connect 8085's A14 to A input of 74LS138.

Tie B and C inputs of 74LS138 to ground.

Connect 8085's RD (active low) to the Read Enable (RE) of both 16KB RAM chips.

Connect 8085's WR (active low) to the Write Enable (WE) of both 16KB RAM chips.

Connect Y0 output of 74LS138 to the Chip Select (CS) of the first 16KB RAM.

Connect Y1 output of 74LS138 to the Chip Select (CS) of the second 16KB RAM.

Connect 8085's A0-A13 to the address lines of both 16KB RAM chips.

Connect 8085's AD0-AD7 (demultiplexed data bus) to the data lines of both 16KB
RAM chips.

Diagram:

[Diagram for Q18c will be inserted here. It will show the 8085, 74LS138, and two 16KB
RAMs with all necessary connections.]
Conclusion

Interfacing memory and I/O devices with the 8085 microprocessor is a fundamental
skill in embedded systems design. This document has demonstrated various
techniques for address decoding, primarily utilizing the 74LS138 3-to-8 line decoder, to
correctly map different types and sizes of memory (ROM, EPROM, EEPROM, RAM) and
I/O ports within the 8085's address space. The detailed explanations and circuit
designs illustrate how higher-order address lines, along with control signals like IO/M ,
RD , and WR , are used to generate unique chip select signals for each device,
preventing address conflicts and ensuring proper data flow. Understanding these
principles is crucial for designing robust and efficient microprocessor-based systems.

References

[1] Gaonkar, Ramesh S. Microprocessor Architecture, Programming, and Applications

with the 8085. Penram International Publishing, 2002. [2] Brey, Barry B. The Intel
Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium, Pentium Pro
Processor, Pentium II, Pentium III, Pentium 4, and Core2 with 64-bit Extensions :
Architecture, Programming, and Interfacing. Pearson Prentice Hall, 2009.