SRAM Dynamic Stability: Theory, Variability and Analysis: Wei Dong Peng Li Garng M. Huang
SRAM Dynamic Stability: Theory, Variability and Analysis: Wei Dong Peng Li Garng M. Huang
0.98
0.96
the separatrix of the former is along the well expected 45◦
0.94
0.92
line, the one of the latter is distorted by mismatch.
0.9
0.88
0.86
4. DYNAMIC NOISE MARGINS
0.84
Using the concept of stability boundary, new dynamic
0.82
0.8
noise margins (DNMs) are defined for read, write and hold.
0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Normalized Dynamic Noise Margin
Figure 2: Correlation between SNM and DNM. 4.1 Dynamic Noise Margin in Read
The read DNM is defined for a given wordline pulse width
3. STABILITY BOUNDARY: SEPARATRIX TR . To obtain the read DNM, the circuit setup correspond-
An SRAM cell can be described using the MNA equations ing to the read operation in Fig. 4 (a) is analyzed. Before
the read starts, the bit and bit-bar lines are modeled as two
d
f (x(t)) + q(x(t)) + u(t) = 0, (1) fully charged line capacitances. Beside the cell being read,
dt other unselected cells in the same column may draw leakage
where x(t) ∈ RN is the vector of nodal voltages and branch currents from either the bit or bit-bar lines depending on the
currents, u(t) ∈ RN is the input, f (·) and q(·) are nonlin- stored value. These leakage contributions can be properly
ear functions describing static and dynamic nonlinearities. modeled and included to capture the inter-cell interaction.
First, the separatrix of the cell in hold, i.e. when the two ac- overwrites the SRAM state, hence producing a state flip.
cess transistors are off, is analyzed (e.g. using the algorithm The cell in write mode is analyzed using the circuit setup in
described in Section 5). Then, starting from an initial zero Fig. 5 (a). One of the bit and bit-bar lines are discharged
or one state, the transient state trajectory of the cell with before the write starts. Hence, the initial voltage of one
the access transistors turned on (Fig. 4 (a)) is simulated. bit/bit-bar line capacitor is set to zero. Similar to the pre-
The time it takes for the trajectory to reach the separatrix vious case, transient analysis is performed to compute the
is denoted as Tacross . As shown in Fig. 4 (b), the read DNM time, Tacross, at which the state trajectory crosses the sep-
is defined as aratrix of the hold mode. For a given wordline pulse width,
TDNM,R = Tacross − TR . (4) TW , the write DNM is defined
TR VDD TR
0.4
∂f ∂x ∂f
· + = 0. (19) equilibrium point
∂x ∂pj ∂pj ti 0.2
∂f ∂q ∂f ∂q 0
Define: Gi = | ,
∂x ti
Ci = | ,
∂x ti
di = | ,
∂pj ti
ei = | ,
∂pj ti
0 0.2 0.4 0.6 0.8 1
X1
∂x
si = | ,
∂pj ti
and Δt = ti − ti−1 . (19) can be written as (a) A 6-T SRAM cell (b) separatrix
−1
Ci Ci−1 si−1 ei−1 − ei
si = + Gi + − di . (20) Figure 10: Separatrix of a symmetric cell.
Δti Δti Δti
Note that di and ei can be obtained by computing the sensi- Since the main cost of our tracing algorithm comes from
tivities of device model evaluations. The matrix inversion in the two transient runs, the separatrix tracing method is very
(20) can be facilitated by reusing the matrix factorization in efficient compared with the brute-force method. The separa-
the last Newton iteration of the transient simulation for each trix tracing time is less than 1 minute. But if we run 100x100
ti . Hence, by accumulating the transient response sensitivi- brute-force transient simulations to sample the state space
ties starting from time t0 according to (20), sensitivities at to obtain the separatrix at 1% accuracy, the total runtime
any other time points can be rather efficiently computed as is about 38 hours. Hence, the proposed method provides
part of the transient analysis. The sensitivities w.r.t. other more than 2000X speedup. To verify the accuracy of the
1 1 are −0.002ns, 0.002ns, 0.013ns and 0.025ns, respectively.
separatrix separatrix Again, we use brute-force transient simulations to verify our
0.8 0.8
results, as shown in Fig. 13. It can be seen that in the first
0.6 0.6 case, no state flip is produced, indicating a write failure,
X2
X2
X2
Figure 11: Separatrix under device variations. 0.4 T
W1
0.2
tracing algorithm, we randomly select 20 points close to the T
W4
separatrix in the state space. We run transient simulations 0
0 0.2 0.4 0.6 0.8 1
by taking these points as initial conditions. Each transient X1
state trajectory ends up at the correct stable equilibrium Figure 13: Verification of write DNMs.
points without crossing the separatrix.
7.2.3 Hold DNM
7.2 Dynamic noise margin analysis To understand the cell stability in hold, a noise current
Several DNM analyses for read, write and hold are con- with an amplitude of 135μA is injected into one of the stor-
ducted, where the initial SRAM state is at x1 = 1.0V and age nodes. The duration is varied as: TH1 = 1.685ns,
x2 = 0V in Fig. 10(a). TH2 = 1.683ns, TH3 = 1.654ns, TH4 = 1.460ns. To charac-
terize the hold DNM, again the separatrix in hold (without
7.2.1 Read DNM noise injection) is traced. Then, with the noise injection,
We consider an asymmetric 6-T SRAM cell for read DNM a transient simulation is performed to find the separatrix
analysis. We first trace the separatrix in hold. In the read crossing time Tacross to be 1.684ns. The hold DNM may
mode, with the access transistors being turned on, start- be defined as the difference between Tacross and each TH .
ing from a stable equilibrium, a transient run is used to Given this, for TH1 , the hold DNM is negative, suggesting
compute the time at which the state trajectory crosses the a state flip, which is confirmed by the transient simulation
separatrix, or Tacross. It is found to be 8.71ns. Then, con- shown in Fig. 14. For each of the other three cases, the
sider four worldline turn-on times TR1 = 8.72ns, TR2 = hold DNM is positive and hence no state flip happens, as
8.70ns, TR3 = 8.20ns, TR4 = 5.00ns. According to our read confirmed in the same figure.
DNM definition, the read DNMs for these four cases are
−0.01ns, 0.01ns, 0.51ns and 3.71ns, respectively. Next, we 1
use the transient simulations to verify our read DNM results.
The simulation trajectories under the four worldline turn-on 0.8
Separatrix
TH1
times are shown in Fig. 12. As expected, in the first case a
0.6
state flip is produced, indicated by a negative read DNM. In
X2
each of the other three cases, there is no read instability (the 0.4
state trajectory moves back to the initial stable equilibrium TH3
after the read operation ends). 0.2 TH4
TH2
1
0
0 0.2 0.4 0.6 0.8 1
X1
0.8 Separatrix
TR1 Figure 14: Verification of hold DNMs.
0.6
0.4
TR2 The read and write DNM variations under independent
0.2 T
R3
Gaussian random transistor threshold voltage variations are
TR4 considered. The nominal threshold voltages for NMOS and
0
0 0.2 0.4 0.6 0.8 1 PMOS transistors are 0.3V and -0.28V, respectively. The
X1 initial SRAM state is also at x1 = 1.0V and x2 = 0V
Figure 12: Verification of read DNMs. (Fig. 10(a)).
In the first example, we consider the VT variations of tran-
7.2.2 Write DNM sistors M 1 and M 5 in Fig. 10(a). Ttarget + TR in (9) is set
For the same cell, we further analyze write DNMs when to be 0.3ns and accordingly the acceptance region boundary
the wordline pulse width is set to be TW 1 = 0.038ns, TW 2 = is:
0.042ns, TW 3 = 0.053ns, TW 4 = 0.065ns, respectively. For
the write, the time for the trajectory to reach the separatrix, ∂Ωaccept = {(Vth1 , Vth5 ) | Tacross (Vth1 , Vth5 ) = 0.3ns},
Tacross , is found to be 0.040ns. Therefore, the write DNMs (21)
−0.2
where Vth1 and Vth5 represent the threshold voltages of tran-
sistors M1 and M5. The traced boundary is shown in Fig. 15.
−0.25
Failure Region
Vth4(V)
0.4 −0.3
Accept.
Accept.
0.35 Region
Region −0.35
Tacross(Vth3,Vth4)=0.2ns
Failure
Vth5(V)
0.2
0.2 0.25 0.3 0.35 0.4
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