PIC16F877 I2C Communication Protocol

• I2C (i-square-c) is an acronym for “Inter-Integrated-Circuit” which was originally created by Philips
Semiconductors (now NXP) back in 1982
• The I2C is a multi-master, multi-slave, synchronous, bidirectional, half-duplex serial communication bus.
It’s widely used for attaching lower-speed peripheral ICs to processors and microcontrollers in short-
distance, intra-board communication.
• The I2C-bus is used in various control architectures such as System Management Bus (SMBus), Power
Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display Data Channel
(DDC) and Advanced Telecom Computing Architecture (ATCA).

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 I2C (Inter-Integrated-Circuit) Bus

Here are some of the most important features of I2C Bus:

• Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
• Each device connected to the bus is software addressable by a unique address and simple master/slave
relationships exist at all times; masters can operate as master-transmitters or as master-receivers.
• It is a true multi-master bus including collision detection and arbitration to prevent data corruption if two
or more masters simultaneously initiate data transfer.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode,
up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed
mode.
• Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode
• The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance.
More capacitance may be allowed under some conditions.

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 I2C Protocol

- It always starts with a start condition (s).

- Followed by the desired slave device address (7-Bits or 10-Bits),
- then a R/W bit to determine whether the master (who initiated the S condition for communication)
wants to read or write to this slave having that address.
- Then if the slave exists and works OK, it’ll acknowledge back to the master by sending an Acknowledge
bit ACK otherwise, it’s considered a Negative Acknowledge NACK.
- Afterward, the byte of Data is sent, followed by acknowledging from the slave. And finally, the master
can terminate the communication by sending the Stop Condition (P) sequence.

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 I2C SFR PIC16F877

• SSPCON1, SSPCON2, and SSPSTAT are the control and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and writable. The lower six bits of the SSPSTAT are read-
only. The upper two bits of the SSPSTAT are read/write.
• SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data
bytes are written to or read from. SSPADD register holds the slave device address when the SSP is
configured in I2C Slave mode. When the SSP is configured in Master mode, the lower seven bits of
SSPADD act as the Baud Rate Generator reload value.
• In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission,

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the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.
 I2C Speed calculation

With the PIC to running at its highest instruction clock rate of 8MHz what value needs to be in the
SSPADD to get an I2C bit clock of 100KHz?
SSPADD = (_XTAL_FREQ/(4*c))-1; _XTAL_FREQ 8000000
SSPADD =19 if clock=100Khz

HOW EVER MAX SPEED IS JUST 400KPS

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 I2C Master writing mode

• START condition : Just like in the reading process, writing begins with a START condition initiated by the
master. This signal is generated by pulling the data line (SDA) low, while the clock line (SCL) is held high,
signaling the start of a transmission.
• Slave Address and Write Bit : The master then transmits the address of the recipient slave, followed by
a control bit set to 0 to indicate a write operation.
• Acknowledgment (ACK/NACK) : The slave, after receiving and recognizing its address, sends an
acknowledgment bit (ACK) by pulling the SDA line low for one clock cycle. A non-acknowledgment
(NACK) would be indicated by an SDA line held high.
• Sending Data by the Master : After receiving the ACK from the slave, the master starts sending the
data, byte by byte.
• Acknowledgment by the Slave : At the end of each byte transmitted, the slave acknowledges reception
by sending an acknowledgment bit (ACK), thus confirming successful reception of the byte. If there is a
problem, a NACK can be sent.
• STOP/RESTART condition : The operation ends with a STOP condition, generated by the master by
passing the SDA line from low to high while SCL is high, thus indicating the end of transmission and
release of the bus. If the master wishes to continue with another write or read operation, it can
generate a RESTART condition.

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 void i2c_Start(void) void i2c_init(const unsigned long c)
{ { void i2c_Stop(void)
i2c_Wait(); SSPCON = 0b00101000; {
SEN=1; i2c_Wait();
SSPCON2 = 0;
} PEN=1;
SSPADD = (_XTAL_FREQ/(4*c))-1;
}
// i2c_Write - Sends one byte of data SSPSTAT = 0;
void i2c_Write(unsigned char data) TRISC3 = 1;
{ TRISC4 = 1;
i2c_Wait(); }
SSPBUF = data;
} void i2c_Wait(void){
while ( ( SSP1CON2 & 0x1F ) || ( SSPSTAT & 0x04 ) );
}

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 I2C Master reading mode

• START condition : Reading begins with a START condition initiated by the master. We achieve this by lowering the data
line (SDA) low while keeping the clock line (SCL) high. This distinct signal tells all devices on the bus that the master is
about to begin a new transmission.
• Slave Address and Read Bit : The master then sends the address of the targeted slave on the bus. This address is
followed by a control bit, set to 1 to indicate a read operation. Each bit is transmitted sequentially, with a change on
the rising edge of each clock pulse.
• Acknowledgment (ACK/NACK) : After receiving its address, the slave responds with an acknowledgment (ACK) bit if
ready to communicate, pulling the SDA line low for one clock cycle. A non-acknowledgment (NACK) would be signaled
by leaving the SDA line high.
• Receipt of Data : The slave then begins to send the data to the master, byte by byte.
• Acquittal by the Master : After receiving each byte, the master sends an acknowledgment (ACK) bit, pulling the SDA
line low, to signal the slave to continue sending data. If the master does not wish to receive more data, it sends a non-
acknowledgement (NACK) after the last byte received.
• STOP condition : The communication ends with a STOP condition. The master generates this signal by switching the
SDA line from low to high while the SCL line is high. This change indicates the end of the reading session and frees the
bus for other communications

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signed char i2c_Read(unsigned char ack) i2c_Wait(); void I2C_Slave_Init(short address)
if ( ack ) ACKDT=0;// Ack {
// Read data from slave else ACKDT=1;// NAck SSPSTAT = 0x80;
// ack should be 1 if there is going ACKEN=1;// send acknowledge sequence SSPADD = address;
be more data read SSPCON = 0x36;
// ack should be 0 if this is the return( i2cReadData ); SSPCON2 = 0x01;
st byte of data read }
unsigned char i2cReadData;
TRISC3 = 1; //Setting as input as given in datashee
TRISC4 = 1; //Setting as input as given in datashee
i2c_Wait(); GIE = 1;
RCEN=1; PEIE = 1;
i2c_Wait(); SSPIF = 0;
i2cReadData = SSPBUF; SSPIE = 1;
}

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I2C writing and receiving

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I2C writing and receiving

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Flowchart for slave

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 I2C writing and receiving

Lập trình truyền từ master sang slave số 12.XY nếu nhấn nút ở B7 và nhận lại giá trị truyền
từ slave 5.XY nếu nhấn nút ở B6. XY là số sau dấu chấm

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I2C writing and receiving (Master)

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I2C writing and receiving (Slave)

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 I2C External EEPROM 24C64 With PIC
The 24C64 provides 65,536 bits (8kB) of serial electrically erasable and programmable read-only memory (EEPROM)
organized as 8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2-wire
(I2C) bus. The device is optimized for use in many industrial and commercial applications where low power and low
voltage operation are essential.

Device Address:

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed
with any number of other open-drain or open-collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hard-wired or left not
connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may
be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When
the pins are not hardwired, the default A2, A1, and A0 are zero.

WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to
VCC, all write operations to the upper quadrant (8/16K bits) of memory are inhibited. If left unconnected, WP is internally

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pulled down to GND
 External EEPROM Write

The 64K EEPROM is capable of 32- byte page writes. A page write is initiated the same way as a byte write, but the
microcontroller does not send a stop condition after the first data word is clocked in. The microcontroller can transmit up
to 31 more data words. The data word address lower 5 bits are internally incremented following the receipt of each data

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word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 32
data words are transmitted to the EEPROM, the data word address will “roll-over” and previous data will be overwritten.
External EEPROM Read

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I2C External EEPROM 24C64 With PIC byte write

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I2C External EEPROM 24C64 With PIC page write

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I2C External EEPROM 24C64 With PIC Using CCSC

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 I2C With PIC Using CCSC

#use i2c (master, SDA= PIN_XXX, SCL=PIN_YYY)

PIN_XXX: chân làn chức năng SDA, PIN_YYY: chân làn chức năng SCL
I2c_start(): Khởi động start bit trong I2C mode
I2c _write(device address): Địa chỉ của con slave
I2C_write( dữ liệu truyền): Dữ liệu truyền là số 8 bit
I2C_stop(): kết thúc quá trình truyền
Ví dụ: một module mẫu của truyền I2C
I2c_start();
I2c_write(0xa0)
I2c_write(10);
I2C_stop();
Các lệnh liên quan đến I2C slave:
#use i2c (slave, SDA= PIN_XXX, SCL=PIN_YYY, address=AAA, Force_hw)
PIN_XXX: chân làn chức năng SDA
PIN_YYY: chân làn chức năng SCL
Address: địa chi của slave
Force_hw: dùng I2C phần cứng
I2C_read(): đọc giá trị từ slave
Data=i2c_read();// data có giá trị 8 bit
I2C_poll: trị trả về là true hay false
#INT_SSP: interrupt that read the I2C signal

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I2C communication between two PIC16F877

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 I2C With PIC Using CCSC
Chương trình master: Chương trình slave
#include <16F877.h> #use I2C(slave, sda=PIN_C4, scl=PIN_C3 address= 0xa0,
#use delay(clock = 20000000) NOFORCE_SW)
#include <stdlib.h> #use rs232(baud=56000,parity=N,xmit=PIN_C6,
#include <string.h> rcv=PIN_C7)
#use I2C(master, sda=PIN_C4, scl=PIN_C3,NOFORCE_SW) Int tam[3];
#use rs232(baud=56000,parity=N,xmit=PIN_C6, rcv=PIN_C7) Int i=0;
Void main() #INT_SSP
{ Void nhani2c()
While(1) {
{ If(i2c_poll()==true)
If (input(PIN_B7)==0) {
{ tam[i++]=i2c_read();
I2c_start(); if(i==2) i=0;
I2c_write(0xa0); }
I2C_write(5); }
I2C_stop(); Void main()
} {
} Enable_interrupts(INT_SSP);
} Enable_interrupts(global);
While(1)
{
Printf(“gia tri nhận được= %u”,tam[1]);
Delay_ms(100);
}
}

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 I2C IO Expander PCF8574

I2C IO Expander PCF8574

The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire bidirectional I2C-
bus (serial clock (SCL), serial data (SDA)) @ 100kHz. The system master can read from the input port or
write to the output port through a single register.

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I2C IO Expander PCF8574

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Internal EEPROM

Steps For Reading From EEPROM

1. Write the address to EEADR. Make sure that the
address is not larger than the memory size of the
device.
2. Clear the EEPGD bit to point to EEPROM data memory.
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA register.

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 Steps For Writing To EEPROM and Reading from EEPROM

Steps For Writing To EEPROM

1. If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that
the address is not larger than the memory size
of the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program
operations. Steps For Reading From EEPROM
6. Disable interrupts (if enabled). 1. Write the address to EEADR. Make sure that the
7. Execute the special five instruction sequence: address is not larger than the memory size of the
• 1,2) Write 55h to EECON2 in two steps device.
(first to W, then to EECON2) 2. Clear the EEPGD bit to point to EEPROM data memory.
• 3,4) Write AAh to EECON2 in two steps 3. Set the RD bit to start the read operation.
(first to W, then to EECON2) 4. Read the data from the EEDATA register.
• 5) Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware.) If step 1 is not
implemented, then firmware should check for EEIF
to be set, or WR to clear, to indicate the end of the
program cycle.
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Internal EEPROM

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Internal EEPROM Using CCSC

write_eeprom (address, value)

address: 8 bit địa chỉ
value: giá trị 8 bit
VD: ghi giá trị 1 vào địa chỉ 10
#define LAST_VOLUME 10 // Location in EEPROM
int volume=1;
write_eeprom(LAST_VOLUME,volume);

+ value = read_eeprom (address) //Address: địa chỉ

cần đọc
VD: đọc giá trị từ địa chỉ 10
#define LAST_VOLUME 10
volume = read_EEPROM (LAST_VOLUME);

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