Design and Implementation of Optimized

Parameter Based Operational Amplifier for High

Speed Analog Signal Processing
2020 IEEE International Symposium on Sustainable Energy, Signal Processing and Cyber Security (iSSSC) | 978-1-7281-8880-5/20/$31.00 ©2020 IEEE | DOI: 10.1109/iSSSC50941.2020.9358826

Abinash Patnaik Abhijit Panigrahy Rajesh Kumar Patjoshi Shasanka Sekhar Rout
Dept of Electronics and Dept. of Electronics and Dept. of Electronics and Electronics and
Comm. Engg. Comm. Engg. Comm. Engg. Communication Engineering
National Institute of Science National Institute of Science National Institute of Science Dept.
and Technology and Technology and Technology GIET University
Berhampur, India. Berhampur, India. Berhampur, India. Gunupur, India.
avinashpattnaik1998@gmail.com abhijit316abhijit@gmail.com rajeshpatjoshi1@gmail.com ssrout1988@gmail.com

Abstract—The most domineering device in the field of As demonstrated in Fig. 1, the device comprises of two
electronics is the Operational Amplifier owing to its widespread stages. The initial one is differential amplifier, whereas the
appliances via analog computation and signal processing. The latter one holds common source. There are two inputs in the
major objective of this paper is to design and implement a two- differential stage, which are named as Vin+ and Vin-. Vin+
stage complementary metal-oxide-semiconductor operational
represents as non-inverting terminal and Vin- as inverting
amplifier through precise specifications and also investigate the
different outcomes concerning several parameters as well as one. The second stage is the gain boosting stage [7], which is
process variations. The two-stage complementary metal-oxide- required even after the amplification of the signals finished in
semiconductor Operational Amplifier operates under ±1.8V the first stage [8]. Hence, output of the initial stage continues
supply voltage and the simulation is performed through towards the second stage, which is a common source for
Cadence Virtuoso having 180nm technology. The important further boosting of the gain [9]. Compensation circuits are
consideration throughout design of this Operational Amplifier also utilized in the negative feedback condition to uphold the
circuit is its feasibility concerning the environment and electronic device stability and attain lower gain at higher
appliance. Moreover, the feasibility of this circuit vastly depends frequency.
upon the process variation, which brings about a significant
impact over analog circuits in terms of quantifiable and
foreseeable deviation of the output. Therefore, to determine the
process variation as well as feasibility of the circuit, different
simulations such as Monte-Carlo and Corner analysis have been
performed for validation and specified gain of 60dB, phase
margin of 58.7 degree and power dissipation of 302.55 micro-
watt have also been achieved.

Keywords—Operational Amplifier, Process variation, Corner

analysis, Monte-Carlo, Cadence Virtuoso, VLSI.

I. INTRODUCTION
Operational Amplifier (Op-amp) is the elementary Fig. 1. Block diagram of Two-Stage Op-amp
configuration of analog very-large-scale-integration (VLSI)
circuits. Analog circuits like comparators, differentiators,
digital to analog converters (DACs) and integrators utilize II. PROBLEM FORMULATION
Op-amp, which makes it more application-specific [1, 2]. Digital circuit design usually implies more automation
There are two types of Op-amp, where the first one is than Analog circuit design [10, 11]. Analog sizing is
inverting Op-amp and the second one is non-inverting Op- intrinsically information-concentrated and wants precise
amp. Scaling of a device leads to reduction of power modeling of different types of parametric effects existing in a
consumption, area etc., which is always needed and remains device. Moreover, a classic analog design problem holds
the key objective. The inflection done here is the reason more constraints, which sometimes also includes complex
behind the improved competence and the frequency of tradeoffs [12]. Still, if one wants to alter or improve the
operation [3, 4]. The major difficulty stays in the design and performance of a circuit, then changes in the analog circuit
implementation of two-stage complementary metal oxide level are much more crucial than its digital counterpart as it
semiconductor (CMOS) Op-amp sustaining many parameters allows alteration in the transistor level, which is the principal
into deliberation which are restraints. Here, the gain of the building block of a circuit. The aforementioned reasons
circuit primarily depends upon the width to length ratio, i.e. motivate towards designing of the Operational Amplifier
(W/L) ratio. [5, 6]. Nonetheless, for the performance employing analog design techniques, which again act as
improvement and stability matching purpose, surge in gain is crucial component in many analog circuits such as integrator,
required. differentiator, comparator, voltage follower, filters, current to

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voltage converter etc. In this paper, we have employed Furthermore, the maximum value of ICMR (ICMRMax) is
180nm technology to design the Operational Amplifier and specified through the following equation.
different investigations have been performed to acquire the ICMRMax  VD1 + Vtn1 = VDD – VSG3 + Vtn1 (4)
workability knowledge of the Operational Amplifier, i.e. the where, VD1 is the drain voltage of transistor 1, Vtn1 is the
process variation of the circuit. The specifications have been
chosen depending upon different constraints. The voltage threshold voltage of NMOS transistor 1 and VSG3 is the gate
supply has been selected as 1.8V as the node is built voltage of transistor 3.
underneath 180nm technology. The Input Common-Mode Subsequently, VSG3 can be formulated as follows.
Range (ICMR) has been chosen between 0.8V to 1.6V, so 2 ID
VSG3 = + |Vtp3| (5)
that all the MOS transistors will be remain in the saturation W 
region, while the threshold voltage for nmos and pmos are μ pCox   3
 L
.45V and -.5V. The load capacitance has also been chosen as
2PF such that the poles will be remained before the 0dB mark. where, μ p is mobility of P-type MOS (PMOS) transistor and
This ensures the stability of the circuit. The gain, slew rate Vtp 3 is the threshold voltage of PMOS transistor 3.
and gain-bandwidth product (GBW) have been chosen for the
ideal case. Here, the input voltage and output voltage swing W 
Therefore,   3, 4 is represented as below, where 3 and 4
are needed to be stay within the ICMR range. The design  L
process is initiated with investigating upon exceptional Op- signify the transistor number.
amp topologies that are widely used. The investigation is W  2 × 10 μ A
  3, 4 = =8.33
ended up with four common topologies whose characteristics
 L μ pCox (VDD − ICMRMax − Vtp 3 + Vtn1)
are well outlined in table 1.
W 
TABLE I. DESIGN SPECIFICATION
Consistently, choosing the approximate value of   3, 4 as
 L
Sl No. Design Parameter Values 7, calculated value of minimum ICMR (ICMRMin) is
1 Voltage Supply (VDD) 1.8V computed as follows.
2 Gain (G) 60dB ICMRMin = VGS1 + VDS, Sat (6)
3 Slew Rate 20 V where, VGS1 is the gate voltage of transistor 1.
μs
Additionally, the value of drain saturation voltage (VDS, Sat) is
4 Load Capacitance ( C L ) 2pF found to be,
5 Input Common Mode Range 0.8V to 1.6V VDS, Sat = ICMRMin െ VGS1 (7)
(ICMR)  
6 Gain Band Width Product (GBW) 30MHz  
2 I D
VDS, Sat = ICMRMin െ  + Vtn1  = 0.2V
 W  
 μ pCox  L  1 
III. CIRCUIT ANALYSIS AND CALCULATION    
The Op-amp has been designed along with the During design process, requirement of the drain voltage
specifications prescribed in the above table. needs to be small.
Calculation of CC holding the minimum value. CC is Therefore, VDS,sat is chosen to be 0.1 V as compared with
prescribed as follows. 0.2V.
CC 0.22CL = 0.22 × 2pF = 0.44pF (1) W 
Based on the above preference value,   5, 8 is calculated
Choosing the approximate value of CC as 0.8pF and slew rate  L
specification as 20V/μs, current associated with transistor as, where 5 and 8 signify the transistor number.
number 5 (I5) can be calculated as below.
W  2 ID5
I5 =SR × CC =20 V/μs × 0.8pF = 16μA (2)   5, 8 = = 13.33
Similarly, considering I5 as 20 μA and GBW as 30MHz, input  L μ nCoxV 2 D5, Sat
stage transconductance gm1 can be computed as follows. where, I D 5 is the drain current of transistor 5 and VD5 is the
gm1 = GBW × 2 × CC = 30MHz × 2 × 0.8pF drain voltage of transistor 5.
= 150.79μA/V (3)
W 
Based on the above calculation value, the approximate value Considering the approximate value of   5, 8 as 12 along
 L
of gm1 is observed to be 160μA/V.
with the virtue of symmetry properties, the following
W  expression can be gained.
Therefore,   1, 2 is calculated as below, where 1 and 2
L W 
signify the transistor number.  6
 L  = gm 6
666

W  (8)
2 2
  1, 2 = gm1 / μnCox2ID = gm1 / μnCoxI5 = 4.266 W  gm 4
L   4
L
444444

where, μn, Cox and ID is mobility of N-type MOS (NMOS)

transistor, oxide capacitor and drain current respectively. W  W 
Where,   4 and   6 are the W/L ratio of 4 and 6
W   
L L 
The approximate value of   1, 2 is chosen as 6. numbered transistors.
L

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 Fig. 2. Schematic of Two-Stage Op-amp

However, transconductance of transistor 4 ( gm4 ) is defined W 

 7
=  
as I7 L
(10)
W  I5  
W
gm4 = 2 ID μ pCox   4 = 109μA/V  5
L L
Correspondingly, the value of transconductance of transistor W  W 
where,   5 and   7 are the W/L ratio of 5 and 7
6 ( gm6 ) is approximately ten times more than gm1 .  L  L 
W  numbered transistors.
Therefore,   6 is calculated as
L W 
Therefore,   7 = 95
W  gm 6  W   L
  6 = gm 4 ×   4 = 150 W 
L  L From above calculation, the approximate value of   7 is
W   L
Approximate value of   6 is considered as, selected to be 75.
L
W  Additionally, the channel length ( L ) of transistor M1- M4
  6 = 180
L has been considered as 0.5 um. Similarly, for M5 and M8, L
Subsequently, calculation of current associated with has been retained as 1um for increasing the output impedance
transistor 6 ( I6 ) and current associated with transistor 7( I7 ) of Op-amp. Moreover, for M6, L has been considered as 0.5
um to decrease the loading effects at the output of Op-amp.
is based upon following equation.
For M7, L has been kept as 1 um to make the output
W  impedance of Op-amp as very large [13, 14]. The W/L ratio
 6
=  
I6 L of all the mos devices are presented in the below Table 2.
(9)
I4 W  Fig. 2. shows the schematic of two stage CMOS Op-amp.
  4
The schematic is implemented according to the calculated
L
parameters conferring to design constraints and specification.
From the equation 9, values of I6 and I7 are calculated as
The Operational Amplifier comprises five NMOS plus three
follows. PMOS, whose W/L values have been mentioned in Table 2.
I6 = I7 = 150μA Fig.3 shows the layout of the Operational Amplifier which has
Because of current mirror, the relation between I5 and I7 been generated from the schematic of the circuit, which has
becomes equal to, been followed by Layout VS Schematic(LVS).

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 TABLE II. TRANSISTOR DIMENSIONS
Transistor Number
(W L ) Ratio
(W L)1, 2 6

(W L ) 3, 4 14

(W L ) 5 ,8 12

(W L ) 6 180

Fig. 4. DC analysis of Two-Stage Op-amp (Static)

(W L ) 7 75

IV. RESULTS AND ANALYSIS

The design and optimization of two stages CMOS Op-
amp circuit have been validated through cadence tool using
180nm node, where 1.8V has been taken as the supply
voltage. Different analyses such as DC, AC, Transient and
Power have been carried out to achieve the different
constraints of the circuit. However, due to presence of the
process variation, analyses like Monte-Carlo and Corner have
been taken into consideration.

A. DC Analysis
Fig. 5. DC analysis of Two-Stage Op-amp (Corner)
Fig. 4 depicts the DC analysis of the two stages CMOS
Op-amp circuit, which has been performed by changing one
input whilst keeping the other input as constant. DC analysis
is generally being performed to identify the behavior of the
circuit when it confronts with DC voltage or current. It shows
the performance of the circuit during initial condition when
circuit is turned on without any input signal. The Op-amp
circuit simulation provides a series of values, while sweeping
the DC values over a prearranged range. The DC source
voltage is instigated with start and stop values and vary the
DC range from its initial value to final value. Fig. 5
demonstrates the corner analysis of the circuit while Fig. 6
shows the Monte-Carlo analysis of the circuit. It is observed Fig. 6. DC analysis of Two-Stage Op-amp (Monte-Carlo)
from the figure that the corner analysis provides the voltage
variation up to 23.853mV, while the voltage variation in B. AC Analysis
Monte-Carlo analysis is 96.4257mV. During the simulation
process the corner analysis considers the different parameter Fig. 7. shows the AC analysis of the two stage Op-amp. It
values such as MOS, capacitor and temperature. Similarly, is the small signal analysis which is accomplished in the
for the Monte-Carlo simulation analysis, twenty points have frequency domain and utilized to achieve the frequency
been taken into consideration. However, the number of points response of the circuit. Different parameters of the circuit
can be varied depending upon the application. such as lower cutoff frequency, gain, bandwidth and phase
margin etc. are also can be defined with the help of AC
analysis.
It is observed from the figure that the Op-amp achieves
nearly 60dB gain and 60-degree phase margin. It also
observed that the cutoff frequency is equal to 30.5MHz which
is nearly same as given specifications. The AC magnitude is
considered here as 1dB for the ease calculation. The analysis
has been considered for both ICMRMax and ICMRMin and the
gain varies from 57dB to 62dB, which is a desirable range for
the circuit for functioning correctly. Fig. 8 illustrates the
corner analysis and Fig. 9 shows the Monte-Carlo analysis of
the two stage operational amplifier. The Monte-Carlo
simulation is accomplished with twenty points. These points
are varied depending upon the application and the required
Fig. 3. Layout of Two-Stage Op-amp accuracy of the desired circuit.

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 Fig. 13 shows the corner analysis of the circuit where the
voltage variation is approximately equal to 20uW and Fig.14.
shows the Monte-Carlo analysis of the two-stage Op-amp
where the voltage variation is around 38uW for 20 points.
Additionally, Table 3 shows the comparison result of
proposed and previous two-stage OP-amp. From the table, it
has been observed that the suggested Op-amp delivers better
performance as compared to others.

Fig. 7. AC analysis of Two-Stage Op-amp (Static)

Fig. 10. Transient analysis of Two-Stage Op-amp (Static)

Fig. 8. AC analysis of Two-Stage Op-amp (Corner)

Fig. 11. Transient analysis of Two-Stage Op-amp (Corner)

Fig. 9. AC analysis of Two-Stage Op-amp (Monte-Carlo)

C. Transient Analysis

Fig. 10 shows the transient analysis of the two stage

operational amplifier. Moreover, transient analysis ultimately
provides time domain waveforms consisting of voltage and
current. Transient analysis basically determines the behavior
of the circuit though confronting the non-ideal signals. Form Fig. 12. Power analysis of Two-Stage Op-amp (Static)
the figure, it can be observed that the amplifier is connected
with sinusoidal input of 1.6V amplitude with 1MHz
frequency for input and the corresponding sinusoidal output
waveform of 1.06V is achieved through simulation. Fig. 11
shows the corner analysis where the output voltage variation
is measured as 211.233mV. In this case, the corner has been
considered for both the input signal and output signal.

D. Power Analysis

Fig. 12 shows the power analysis of the two-stage

operational amplifier. Here the corresponding power is
302.55uW, while the supply voltage is considered as 1.8V. Fig. 13. Power analysis of Two-Stage Op-amp (Corner)

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 considered due to process variation, which elaborates the
applicability of the circuit.
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