9.1 Introduction thm or information on how tp if memory system is fo, Armor system can be consid 1 canis 466 Up mag ert sor Memories : These consist ofthe small set of (0) gues which arntmalo a processor andro used a tempor Each location can store a computer word. Word ‘e.computer. We can see the memory as stiown in mory and Secong, me Storage Device system is to increase tne Caen sey es whee " ‘memory such that t proce @ ) © owing terms are most commonly used for iden us memory devices and tecinlgges 7 0 comparative behavour ge Location : Ther are te possible sage locations, Internal Storage : We detng ntemal Storage as storage which is needed 0 also called Primary storage. femal storage as storage which is "0 CPU. kisalsocaled secondary PU also have its Onn loa memary inthe fom of Bit (Binary Dig): Abinay digits gical oo fran active state of a component in an e Nibble : A group of four bits i caled nib Byte : Aroup of 8 bits is calea byte. A bytes the smalest unit which ‘can represent a data tem or a character. ting a passive (219) atDirect Access Mo ‘own ROW heads, so, (@) Computer word (oF Wor ) fixed number of| 1B = 1024 Byes 1B = 1008 KB 168 = 1024 Me 178. 1004 a8 1 P= 1028 7B canbe word or Block, Fri Stilo wor ng Py inch ager unt thar aa (Destructive Read out ; ead, they are wiped, called Destructive Read o ‘Access Time : Access te is defined a8 me required 1 pay retrieve a record. ” operations) Hence, Memory-Cycl time consists of the access any additional time required befor : (c) Access Rate : Access Rate is defined as number of Reay y operations carried out per second. nm 1g Rlfers tothe way the memory can be ay me can be accessed (Retrieved). Various ast wo Memories: These ao hse emotes wher oman ae Power is tumed off. Semiconductor Memory is ‘The solution to the problem is using of UPS.” © OS Ue + In this Pe of momar hg | | ee ation aftwo successive memory operations. | ‘one FUW head and each location of memory is accessed serial, ity of Storage Locations “The capacity of ea manufacturers. They memory locations. (a) Fixed Word Length Storage : Inthis design a fixed number of characters are stored in each ol the memeny location. These characters are treated asa single word This such machines that store a fixed number of characters in each adress locaton ae saidto be word-addressible Fig. 99. shows two lectins each of wich stores, length word of eight characters. is fixed and is provided by the computer ‘accessed from 1 to N. Access sia 7 ‘magnetic tape. This Access method is useful ing techniques in desging adresses io tese processed as shown in figure 9.2La — | g sii Walle WORD >< WORDS es ae es hit ly acvatage: rues Westongh machin ; fine heen anght werd is eight characters 1ong, then Wo eghy ry resltememtbenay moran eae atecopramba’ 210 3 wor Suppose a tee ot pon the Word rr en See anand wal ©) Vrale Woréeng at each memory location can be character desig approach, the work MUKTA will occupy eight as shown in FIGURE 9.4 ming Yr rst eo eins oe Onesie: Casas es mich tne Ferries cahoperenine etter | ae ery earn woe Pecan ceoraemr nee naw sec soe tenes TS then supplying the number of addr ‘Thus the data item RAJESH stor to 0016 mye retvieved beginning with Fi by identifying the address of R viz 0' (2) —_——__ . Characteristics of Meme sone goes down the herarhy, te toxin xr (y_Inreasing access tine, Increasing capaci Decreasing cost per bit (Decreasing Kequency tae the memory by i Gp “rnus smaller, more expensive, faster memo slower memories. 18 ae supplemented by larger, cheaper, “There are several devices which can at as a memory ony evie ponent. For a act as a memory Component, i must have folowing chaactersoe ° 3. Access Time should be Less. (Access time is defined as time requied to locate and retrieve a record) (223)4. Packing dénsity should be more Pas dg pores er mr eooue cones aren my 7. Information stored should not decay with passage of time, ‘Magnetic cores, Magnetic surfaces sua irom 1960 0 1975, he mom, 195 0F Cores Of magna) 5 of af eed must have less ost 5 memory, magnetistateinthe absence ofthe curert, 1 2 3 ‘ 5 6 z. Storage medium, access speed is igh sos | a0c05¢ oF end il ependc, 8. direct access of data a —— aaa +s of Main or Primary Memories “These are fast & expensive and are generally used in ALU and other pa cpu, a pars of (225)(0) Metal. oxide Semi-conductor (MOS) Technology patty bt ss exer & 2 UBEU SEMA ny section % 9.7.2.1 Comparison between Bit “ron = <0 WS ve pea oh oe ae — mlrosecond. mount of dataitcan hold microchips and also inthe "Motherboard. These racessor. — 2, Thay ae comparatv ty Soy, ee 9.7.2.2 Advantages & Disadvantages of the semi-conductor memory ‘Advantages : (@) Cheaper due to mass production & non-manual process, (©) Take much less space than core memories due o timely integeateg, (0) faner tan cov monn bea. of absence ot oes ive. be 3 ts contents a S000 as the powers an use he UPS (Unnieruptod over ag 272.3 Difference Between Magnetic Core & Semi-Conductors Memo 1. Nonvolate 2 Belen ery 8 Lotus take a simple example of why RAI bythe computer, When the CPU es ae ‘aplication Program, such rocessng to memo, facitales 4 Distustve readout catlon program to workas: ony as possible. The process 5. High power consumption ‘when the user enters a command rom the keyooerd. The CPU ilepois 8 ‘pommand and instruct the harddisk Toa the command or program ito ii ny ne Bak 7. elavoly large access tre 6 tame dren train memory. Once the data is loaded into memory, the Ci Truch quickly as shown in fig. 9.8. The reason behing his that main memory i ‘uch faster than secondary memory. tz)TIGURE 98 [ Random Access Memory 9.9 Types of RAM AM is of two types as shown ing. 29 (i) Static RAM (SRAM) (Dynamic RAM (ORAM) i _Dinee —oe“ = easton i¢ RAM (SRAM) es of Static RAM are three types of SRAM, ‘burst SRAM (BSRAM) ; Bust SRadAis 5 (Fig allows itto be more easily synchron juces access-walting time, Spee fer than ASPAM, but tis 3 5 Se eae ple, i ape srehate onthe nene orn and eeson 0 is offen used. ‘operate atbus speeds higher than 66MHz, gy Dynamic RAM (DRAM) 2 nAM, unliko SRAM, must Be continual no ori is done by lacing the mnmon carte ek main be dat, T pnd es per sezied DRA denpevind seve fp ad smal Al RAIS is aay of one capac and on prams RAM stores infrmaten A Dynaay ina vor erie, Tae reas ory wo mil-econds, Ama arr DRAM consumes les poner a 1 TMi pce on computers moter less, Spy one wansslor por mena clang hence fs package ders gh 99.2 Types of DRAM [DRAM technology has evolved ove the lst decade, ving diferent Kinds of OAM. Some of he most popular DRAM tecinaljes are bled given in table 9.1.|Z Synetronous DRAM 8 || 1. Fast Mode DRAM ozs ee (oRaM) Need tos continous. se owe as compared to SRAM. glo ROM. “ro memory fom wich we cane ne. rare red on ROM 8 ale wa roar & microprogram. ernie ere on used th ca rw ile ne and mcovave oen,OPU aaa Wo nd eaten9.10.1 Types of ROM (2) MROM (Masked ROM) Tr contained a pre-programed treks rastod ONS re chip producto? Sins the ch. transistors inside t © aoe eno is ao on as onetime ana sare COM 8 a PROM cP ae abe hake per own ROMs so trou ey an ete ew PON (¢) EPROM (Erasable and Prog canbe erasedby exposing ttouta vole quar ‘An EPAOM eraser isnot selective: it wil erase the sive than PROMS, their ability tobe (o) ePROM Ta EEPROM 8 pepe ines sh aengardwoper vicina Savoceng be oe ch hence pos eae indo Theboper erng ct EEPPOM ges ae hong ea a and the write operat i time. Both of these disadvantages are disappear ‘growth in technology, sepean wih ba ‘about 4 to 10 ms (Mili seconds). n EEPROM, erased and programmed. EEPAOMSs can be or 9.10.2 Advantages of ROM © Non-volati in nature © Easier to interface than RAMS lex state and donot requieretreshing is are always known and can be verfiog geht Memory ory is @ Very high-speed memory, wi Ga teeta) a com aay ME Ee Between he ig much slower han the CPU. Teteore, movin sa tr vey ie consuming cperctent 9 deta between RAM and the r ‘fo sowvothis problem, a vry high-speed memory calla “cache memo" is placed fenwoon processor and main memory. The frequen used insuctons are stored seNtcho. So. the processor does not have to accass them again and again fom ‘andom access memory (RAM) because, they are made avalable ti fom the ‘one memory. This improves the overal etilency of computer. (299)ee 9.11.1 Levels of Cat cache memory 19808 most PC CPUs have, nt cache is often called Loy many CPUs have as much a8 256 KB in (i) Level-2 Cache : In addition tothe each mem ec Py Level Cache: Incr Tuemebverbear-esdenteaang eo rey Pos Dong Sl Oday have Sp ye nay tog hs " ‘motherboard cache memory. 9.12 Flash Memory Fash memory i non-volalle memory thal canbe e480 ard reprog, ‘hears tate dea siordin hese memories Not erased even whee ge Imoing deve inh ‘switched of. As flash memories do nt ave arms ete, So, hey are faster than the mechani special ype o! EEPROM, 1e between EEPROM an whereas flash memory chipalows data to \wtten or erased in biocks and same makes lash ‘erasable and programmable. The whole device is erased in one operation. Flash memory gets its name because the chip is organized eo that a section of memory cols ‘are erased in single action or flash. { a GuRE@s 9.12.1 Use of Flash Memory Flash memory is used in Pen Drive LAN entenes cart (e Rash ear cis) for ot book computer Digital iat Embeded coolers «ase Dal ass (OA) ch mereres oer sorage capactiosuplo 4G8. Fash memo Alo cated PC cards. PC cards a fray pes tat ery va nga tex) Se gl 932 ages of Flash Memory yan © small Sze Fast © Economical + Geny low eneray consumstion Storage 3 oprmary soa98, Which he Cantal Precssing Un GPU) ues or eng data and instructions, secondary stra ia oe | ekucton 981 uted to store daa a procers when they ae net Being processed. Secondary so aces 100 sks floppies, CD-FOMS and magnate tapes, Those aonees nana ; etc tapes. These dewces have @ ike Pad more permanent) storage capacy and they ate ess renee eo 1 pray rage eves bt hey are yin compel | | advantages of Secondary Storage etroveniages oF S600 age ae ‘Non-Volatlity: It does not lose its contents even when ts ponerse of capacity : Secondary storage can store larg volumes of data jequvatent ‘2 00m full of dala on paper) in sets of disks. ee ‘Gost: Its ess expensive to store data ona tape ods Reusabilty: The data remains inthe secondary storage as lng a Brerwritten or deleted by the user. Te eet Portability : Moder day storage devices ike CO-RONs ° ste so smal that, they can be easly ported fom one computer eanoher Reliability: Data in secondary storages sae becau r romain oe 58 secondary storage is )) Convenience : With the help ofa computer, authored peopl can locate and access data quickly, roe Methods of Accessing Data imariy. there are two methods of accessing data tom the sacondary storage ‘Sequential : Sequential access means the computer system much search the storage device from the beginning unt it nds the required piece of data. Example is magnetic tape, 0 (205) tta nee atin ge ee renannel, then there fe gage in te assem, er 9-channal tape thre a ean the assent, ered onthe tapi the form ot ‘Magnetic tape is very popular storage medium for large data. Mt orca tape moves wien Continuous length storage medium similar the tape usedin voice or soun tis made of past bbon. iis of 1/2" with and 2400 feet in length Magy Coated with magneizable material on one side, Data are stored in ma hich ae permanent. The data slored on tape can be read again and; ‘magnetic tape just as in case of sound tape recorder. As the new data i Previous data stored on tape are Magnetic tape is cvided into num (vertical called frames as shown rico) Aled Yacks ard chy 0 data should be read from the tape ie the ty _ ‘moving at @ constant speed for rea eet BIB eck 1 Blocking and Deblocking FIGURE 837 FIGURE 9:6 (gmat Tope Unt) ‘adit heads i. for each track there is locks as shown in ma ee fig 9.17. WeTS = 00rd in block i, uber of ca Hot ha ris then 4 eco ar lg 20 IG Bets. he Heck sie age. STONY where contents of block are cont memory. The cord is SE" Bogram work space, This process However, ifthe system stores unblocked and interblock gp in figure 9.19 tape atthe begining and at the '9of a magnetic tape file is called header maton about the fle such as Inter block gap is of 0 inches. The block 9.14.2 Tape Utilization He Bro which le cant be overrten tape length used for data 100 Tape stiizaton in 5 =

10.231 Optical Mark Readers vers ae capable of recognising a prespeci ‘ase ee 2 SE ray tents MIG have apes May inobp y pene or pen. FOF a ta anewer 0 Questions On a 1 tl cn of Tut S88 a eel ind spent ane vrs atematves, These ansiver sheets are i con che ging we se of a optical ar read ri elt ie cx gfe Ye tes. nt any pt deta gel ant we recorded for OM inp teat of selection nature ca ye used by an OMR device re ua 2 Re eal wa, Soe searod ed detesing nerfs feat md wih st Teas penal gg ee ha lta rapa For example 4 Corin Sample quien ofan objctve toa and san Taal an opel ark rader to grade the ests given Doles oe cag Question (24 4 character Readers join at cof 200 2eryoso charactors ma aPetren characte tandard size, 0 oe ead On oh ype ae can om ee "ye erenary ink ed at te, orf eam standrg) ang oonee Secs “age of Mand Serer Character 2 Sanday at carpe ma been scanned, ten ming OCR devices pearson igang gm ip considered iaracter read, P28, Which acters con esac th any ofthe fonts, tis rigs “Med hae ae ce acter does or Code Readers 3 Bar gers a SONC0 Ut oe 008 rmed BY a laser-beam scamer yeh barcode date pai Pe Spoxed acoes hepatomas war SHAG ante T padely known bar code is "ecorded ase Pu. The st We, Product Code (UPC) int data penou Uis.A. These bars are 08 The fist five of 'e manufacturer joduet and the Ink Character Reco, FeouRe 1a 4 Magnetie- " character recognition (MICR) devices we e develop to assis the and on gusty in processing the tremendove "A special type of cheque is used in Para ee be wit Ry MICR devices (235)09°* “can 028) anda speci that ot io epiayod On he scren is eter and m, ve win cat Peso patch "6 rei than tat on Men tite Wer ht comer capably of interactive graphs of display screen that has a it Janel co hone ics then stored in 5 MicroP! input sound wh ee em npenit rman Ft on oF ra muted prose” sound0 famry outs, and retail stores, ‘of game and the numbers o pay are m ynerates and pints the lteytexet sensitive pad is used as a point |, touch computers, my 1 objec along the pad, you nthe display screen, Many ‘such as microwave ovens, use touch ce that can read tet, graphs, drawing and photo and convenient form tobe understood by the computer A 1 principle of digitzing an image in the form of bit matrix called (257)mera (MACHIDE-Vision Seq) rp map can vo 2000 810, SELYCS titmap’ The bitmen rant packagesprograms, °° og ceasiy be manipulated PY apes and sizes. The tw "ey jon System allows a computer Tage scanners cr ¥8 nag rr ee 2 See are scanner: Afb scanner ho a | caret, TS an gn j) Flatbed Scanne® © nich consists of @ Box a (9 Fpotocony machine. WE ard aid that covers ‘ 1 camera 8 FoCUBed on the Favig agus Pl Or tobe scanned is En oie tte : co pate The ight al carera cele &age og and interpreted by the computa," OE om, so tat +S thattcan od image ofthe objects mache 1 re enteral ag ean i Ae me 1-held scanne i F @ match is foun (mans ea es rade oe os a ‘scan 2 t0 5 inches Ba) Sprontia YSLEM takes the n of the document al device, which acceps data rom Sere verso he et camerare Used enn lonisreasan, oa 'm,which is sutabe for use by the ouside wot an be broad! ified i 10.28 Voice Systems ( regen ono nay casei oe owing oes ort copy Output: OUUt whCh srt pociced on +. Syecopy output. They are temporary in nature For exany se {8 known as sereorminal SEEN. OF SOKEN Out ya ie repay ee ene on Syl a ot utp Oupu which ord-copy Output Produced ona paper, dor oulut Tey ae pemanentin nature Forsnang ee ea mars and poters on paper are haan ou PS MOMERADY Voice recognizers are used in some graphics works Zovept vice commands. The voice-system input can be rons or fo enter data. These systems operate by ined diconary of words and phrases. B ted thus allowing their use only to wages More efficient device. ‘ isthe main oul acathod ipa Monitor yy Unit (VOU), commonly called as monty iput device of a computer. onsets of “Tube (CRT), which dspays characters forms images trom tiny dots, caled 1 and Handicapped people, lancieapped peopl os, tat aro arranged i rectangular. Tha eres of the image (Steen esOuten) depends spon the number of pixels. There are to Kinds of vel ube (CAT), (i) Flat-Panel Display 1d speakers can be identified (a (250)10.4.1Cathode-ray Tube “The operation ofthe CRT is itustrated in fa 10.15 screen, The elecons ly the pons where the beam makes carta. By focussing the electron beam ora a Fenty ert spit o otc apis he pose coer ey the ue ofa dooce sto, the beam can be mad o Generate a pay CRT screen, an The OFT screen shor. The smal te the beter e mage cry, or resolon, re elements, caleg be uminateon eet FE on tea, in levision, cis ean PCRS dats me Potable creat, isles ar devices hat conver etal @ Stone tcmet ac isplays use optical etfects to wert from some other source into a CN a eee o as Types of Monitors - Video Standards ‘je are ditferat kinds of monitors depending upon th numberof stl or re rons). Depending upon the rescluton, manors ean be dashed a, (25)10.5 Printer nse is tomestiren (@) Impact Printers ‘The printers th © the characters without striking ageing, |Non-Impact Printers. These printer 10.6 Impact Printers 10.6.1 DOT Matrix Pri One of the mast Printers in Market, maids becaus 88 of Printing eaturesanaeroromcal pcs eDe Matin Sia Printed is in form of pattem of DOTs and head consis (8x7, 7x8, 9x7 oF 9x9) which comes out o form a char Dot - Matrix Printer av oP a some (408 cranes ing speed ares fom 200 to 26 10 ayy it EPSON, Pag Nee Supping Ps, characters per TVSE, GODREJ i & send . * citer anguage characters canbe pine, pysadvantages + Slow Speed ‘+ Poor Quality (288)La are generally use ‘sent here and there ‘Advantages = ‘@ More reliable than MPS @ Better quality ‘¢_ The fonts of character can easily be changed. Disadvantages = ‘¢ Slower than DMP'S © Noisy ¢ More expensive than DMP'S 10.6.3 Line Printers Line Printers ate printers which ee Pies ve pape out Tey ee very anne eae tb a0 tes per ne. Two most carmen yee 9 a ange a) wel it ren the paper. You cn rng. These printers Nave very slow gr The we SIN ns on ‘ 35 Lette- QU same as Latter Oye) covond Quality of iting Is Very goog cfr word-processing in off68s which require aff orn very nice quay representation, fom en print one line at a time. These are inpag i, the category ao : DRUM PRINTER and CHAIN PRINTER ei, 10.6.3.1 Drum Printer sts of in Market, 48, Character Set, 64 re equa to size of papers. fora paper wi im, The surface of DRUM into nur sees ar ‘wil suppor. Different characters sets ares = : “on Se zauent empath ote tara Thus ‘J‘is embossed on paper. (286) of DRUM Prints one i 6 to 2000 lines per mite, a Prin 0 aractes oat ote atte shows ain Printer - go Line Printers, because of use of ters. They can be thought of cated rar ot repeated, hee or four times, 2 chain of, 88. Tape we A standard Speed ang, Speed nr alate tg be ve SFY Pes, he misting cases way iting, character os, undone spo act a cha, 96 characters. chasse nay 19,64 m son to the chain the printer has a sto a manner that an irked ribbon and paper nM al numberof hammer pares. rents at a 0d an achat mre ig to arora Panne, whee ha plow it Boca ta print pasion, edn tonto he be placed between the S-equlo he tal runtes ote have 132 uns the drum of drum printer, the chain cach pict cage, Ah lows the use of dterent fonts and deen va tho same printer orp (guages) tobe used (287)—————EESS—— so Moet SS He aes Advantoges: © Character fonts can easily be changed. 5 Tepanetcy pg mI nay eta aan aes ‘ be used wth he same pring, Donot have thea and graphics Noisy in operation. 10.7 Non-Impact Printers 10.7.1 Laser Printers ‘These are non-impact page printers. They US laser IONS to produgs ‘Reeded to form the characters to be printed on a page & hence thes printers. FIGURE 1021 My ny shape ol characters, tern 288 Dy, the = [ey “SOGES to tun he tser 's Ceara a, Potdatad ae OMEN 2 postive 148 the dre C2 Basing from tote pare Tbe acre ate dierent? um suriace (aod 127 cparicls are permanen 6 *Tpressre con Paper by using either heat ot Gram 1165 Back 6 he cane + c288 nk & epee the ru pats dleans of ered 0 pape, Wy fixed 0th 1 ea otis aly ve mary fons and dierent character se suppor + ages pene sed 0 PALE Up cope ota docu ant 2 Tein ingle prnig, printers iow as compare to laser printer creme FouRe 1022 (269)10.7.3 Thermal Printers 10.7.4 LCD & LED Printers Similar to a laser enter bat une aud cso oN dy, # laser to produce an mage on the tum ‘Me, 10.8 Plotter Piotr are, used orn igh qualily apis and ravings. Pt, nay tn aving graphical images such as cha, rainy, ‘engineering and scientific a one. Soe poten espe 10.8.1 Flat Bed Plotters ‘The fat-bed plotters more expansive It uses at drawing stag Paper is attached, On some model, the surface is horizontal, nie ted in a neatly vertical located on two slides ofthe to hich Poe mee 0 cosane the these automated drating tables can range upto roughiy '™) with ploting accuracies approaching + 0.001 in, (x 0.026) Paper Flatbed FIGURE 1025 (FLAT BED PLOTTER) [FIGURE 1024 (ORUM PLOTTER) ster Output Microfitm ip jput Microfilm (COM) isa fechrique to produce cpt on a micron Ge ne rousandsminiatuized document gs ti sheet which can store several huncedages,Teinoman eons [any (20)——— 10.10 Off Line and On Li fon the microfilm is read with the viewing (Output Microfim is particulary wien Pe manipulate large amount of dat usa Binge a Gocument handing cost ine Data Entry ces are used 10 niet dala not eet tg ves ms type of fine data erty f° 8 erga werd used, dla was entre cane mach Di ines came hee When the data input then tis called ofne da ‘obsolete now. When punch Bt was off ine erty. Key to disk & puneh-cards. ing these machi entry Wen data is rectly entered to the computer, iti called ‘obvious example of onine data entry Oreline en keys of the keyboard & the data sted or processed. This sort of or ata entry is ne-longer used no. Exercise tas ICR? Whatnduty is the primary user of MICR? Viatihe tlerercebemeen ovine arti dala ny dew Explain various pointing devices. = ior? Wt is advartages and disadvantages s types. video standards, sins devices wih the hep of oyboard mouse eta je unit (ALU) ee alain, rors te arithmetic operations tke agg gg unit {is ns like Comparison, selecion ec Bria feng Sn ng genory on 4 stores instructions, data and sis 0 intermediate resus control unit 4 ic iz controls the operations of sis unit all pats of computer oust ts of devices withthe ws unit cones ee Ts ie For rama, met, Diesen, 1 processing Uni) i the heart ofthe Tomi unit, cont Unt, rege and decoders Moh COE of og es ard removes by ste maces ees ctr shown in gue 11.4 ase Aigo h We Qe the information io wa ter avi eof CPU ist ex eit A chaise, how tes suo wl eae et CPU? se purpose Tperlre. answor this question. In this chapter, We wil 1 GPU, the instruction eye, nstucion nas and aisenp rea , ats and atessng mode, (2m)bus is defined as the numberof ies tat. 2 jaa bus. This means that 8 bis ofinfor ones Bt cy mation canbe tansnited a Two way of Data Transfer occur (Unidirectional Bus : ata in one direction caled Unidrecioal | pearangement of the three types of bsesin a pal dongs sn ‘Adoress Bus. Transfer is controlled by conto signals, ete tay 5)FAGURE 112 chips and UO devices are connected via cs requied egg i ec re at ey Ha rn) oral on thecal Ds. Tremere at 7 om the adcressed locaton on the ro ten data the data is read from the memory into one of the ata bus, by ata Bs, a ome CPU 0 he designed 0 device, "PEN et 11.3 Instruction Set colton of al the instructions a CPy lemens Aninsruton menting ay ton. nd An instruction set instruction cons required by the Ci 11.3.1 Elements of an ii instruction has the ‘An operation code be pertomeds (i) ‘Areterence othe operands on whch data processing i ‘example, an address of an operand. 1915 to Peromes i) A a lermed as opcode which specifies the Petal, iy tthe operands which may store the resus of performed by the instruction. ata proces (hs) Areterene fr tho net instruction, tobe fetched and executed, (em aor 5 qcnto8 98 SOUED CL ny stg 110 8 te ese folds are corresponds to agen otter conse ede, ee Ce ion enon a homey, aon set SOME! ve ‘of instruction set for a machine are: c oF ox may and ts oes epee © ar e osand te es be pon yt nod ete instutn oma? ny «Math, numberof address, length of varios o ad et a a Whats th ruber fee wich canbe ek tre and how are they used ? rence yan ncn wy What ae the meee ot peg ancpewd ais? imr 11.5 Types of Instructions tegorised @s The instructions can be cal ic ictions : These instruct structions are ‘a machine. Examples of the ort r Data Movernent instruct These are required to bri ‘communicate tions are : Stat Inpul/ Output a) w » category. Some of these are + interrupt or sy" saree tum rm inter, Hat intrusion or come ph Superga hy of operating systems. ved ig iy 11.6 BASIC Structure of CPU 1 CPU undergoes Sequence of a ealed the instruction eyele nr wemort 1 tents ofthe memo ids the 1 word et eo comiplaced inthis reir tanened one ete At wed ace Be Herland A orator tnd lO ei aerate be seat ht et battered em tobe sowing wereroy TiS registers so known st Daa Regier (ony wea courte’ (°C) ar ofeonroluntendisuseds hidbeadies a ig om memory aftr the Curent insucon eaten through a counting sequence an, tr, ada | ute computers. This was having minimal number of registers and a small insres”, ‘ris register goes inhuion Trfomented afer an instruction ifthe by cus te cng ‘stored instructions in a sequential manne, aed Ly (2%) 12)4. Instruction Register Itholds the our yo st sare seperate Z rte operation parts senttothe conto} Lhe we and ually command Signals aro spe task specified bythe instruction. roan S Memory Aadress Register (MAR) = tuanis drecty connected 0th aaa racaion fom whe data is rived ort rametar and MBF reilly an Important rag pemeen CPU and the memory missile srctre of CPUCAN BO Oxf MAK it ny purpose increasing the, 2 1 chee vam execution. Exta Registers arg © "28 £ be used for vatious tune fan an end ran ai ig any , In modem day systems, cqnel _ ulin use wher some rege may po eee partoperons “tse odes Registers used fo contain the condition co the programmers. These flags are ss ag, peraon. Some of he common conden gay Oy Zero lag: To indicate whether tho content fast anne am me ber indicate whether the content of last. . tne, Pt Interrupt Enable! disable flag : For enabling ord disabling te Ce fadaro3s oft MaMON/Tecaion where the sy the cperaton 'istobe Ae ——$$___| “pose four address instructions have become ob trinese instructions is very slow. * Now because execution 2. saddress instructions : ‘To reduce the length of an instruction, a register called Program Count iz used to compute the address ofthe nex instruction, Here atwe adhe ieatrction consists of the following arts operaton coe (an)Operation code (]) Two aciosses for two oporande (Address of the memory location where the Feute he ert yg form ofa three address instruction is address2 | address of result SS _] cress instructions both operand address are speciid, The resu ig one of the spectied address. The general form of a two aadrss ns, ction only one operand address in the ‘other operandis: ‘umuletor tel, rom where these can be by another instruction, The general form of single address jons are also called stack instructions. The general form of zero address instructions is HIsiTUCYON depends upo view, most computers ter organization of into the one ofthe three ADD x is the address of he operand. Meaning of his instruction is AC AC ADD Rt, R2, RS the operation Ft < R2-+ RS. Where Rt, R2, RB are general purpose “The two address instructions may be written on {wo or throe addres feds in their ay Specily a processor rogistor oao-address instruction) ck PONY (SP) wg, accumulator nor ack org ‘would have eens ross Hold. Thus ri ‘dcress fed. Th ener nS | (3) Stack organization viento mac frstucion whch 62 ust X iho cross Xto th 0p SACK. Operation py inners ay wapushtne wore donot need 2 instucten. ADD stack, adds thom and push operands rom the ops to 10 “Tere ino need ing the stack to operands ae imphod to be ‘pop, SUB, MUL and DIV fo" the fo wo and tee access instructions by wit "Program Fa(R+S)*(U+V) : Solution : () Trree-Address Instructions [ea ACK ACHMIS] wer] AC ace MU ace Ac + MV) ace ACMIT] MIFI-AC js address of a temporary locaton "eauited or stonng ig instructions wz as folows (TOS sland rear 6 28 J orto ot Tose R aa ® en 5 Toss oF ose (RAS) sf; a Tee eevee i qose(U+V) oe Tose (Fe wer MIF TOS us addressing Modes 1 paddressing mode oF an instruction refers toa ru ‘esse for that instruction is cleus banat which be ech sess anna novia! memon endrnal sree oe paial sory ares environment Tis rgiln ess ft repel pea memory address. raped to physea ation wih tho use of adoresing modes has cern ay the address fed Sd. of he instruction, a larger terms tt Pets orate tage tm rset tetan (285) er (Rrra HeACR AC +26 4 ACE AC- 564 sadress 374 Yor nd PGURE 116, (27) te) SS ,(Wil) Relative Address Mode (ill) Indexed Addressing Mode (i) MisisabocatedPC(Proam Coe AIEEE Me yas y PU as corte em cro the conan My Oren nt inn 0 EH NON he ag ge effective address of the operand. "tray, Etetie ass = contents of PESCoMen faa yy For example: ADD"+100 AD0S+100 rere“ represents contents of PC and this instruction j moe contents of Cote val given nth stun (10) nage hy } 4, ofthe operand, “The indexed address can be any general purpose r (CPU design may set aside a separate set of register the mode the effective address is computed by a address given to the contents of indexed regi Used for address modification in calculations, Etetve Adress = Adress field Contents + Contents ting Toe For Example ADD 100,X here incates the adress ofthe indexed register. Compute gy contents of the indexed riser to 100 to calculate efectve adress ‘Autoincrement Mode In this mode, address is automatically incremented by 1 (one), imple: In insertion (PUSH) operation in stack, the addss ot ug Pointer Register is automatically incremented by 1. (a ee | A = 50H " 57H next ae jodecrement Mode a = the stack, the contents of Of base reir add to. the address part ofthe ‘location o Programs in mem. When rogram ‘one segment of memory to another, as required and data are moved from the address values of instructions must reflect. ce ee systems, positon 9 instruction cycles Asimple instruction cyl wil consist ot he oonng stops: fetching the instruction from the memo ry. This is also termed as feteh-cyte, decode the instruction 0 {i find out the effective address ofthe operand (iw) execute the instructions. This is also termed as execute cyl, Nomally decoding is also performed in this eycle, {269} eaecceeeeneere E inem n ace a n —‘Upon the completion of step (i), the contro! goes ‘and execute the next instruction. This process con instruction is encountered Shy ‘An instruction cycle may consist ofthese Sub-eyces. These threg ‘Wels, % 11.9.1 Fetch Cycle During tis cyte the instruction which is tobe executed nent is memory to the CPU. Steps are Phin (The next instruction address arson tom FC wag, no 86 1) ManpaetiesgniontessteineMe rah metaytegy, spc cote dt wr ace Dregne DR & i uh represen «mane (W)_The PCs incremented by one memory word length Pom pc+1 Tis operaton canbe cared oun paral! 0 he atove operat, (6) The instruction oo obtained is tansfored to he Istucion Rage, ROR 11.9.2 Indirect Cycle ‘Once the instruction i fetched he next step is o determine whether tro, ics memory reference 0 register reference or itis an input oulputinstucion, However, the memory reference i ution can Use Several adessing mig, Depending on the type of adcressing the etfecive address (EA) of pean inpy ‘Memory are calculated. In certain cases, the calculation of etfctive asso | (2 roforence (or example in ty iy €ase of indret aden) in on aloft Which conversa he ing, the ae et adeesses to dct adsosss ot, mie oe San nec oe, os 07 aster te ates fect cycle are Instucton othe MAR, T is tanster can be DR ony a 0 Nioved using OR ont 25 OR and iat tis prt of ne ean came yale MAR DR (Across) jn a memory read operation a once again "7 Fea operation as done in etch cycle is perormed and ane desired ad6259 Of he Operands btn nthe OR. or memory buter register (MER) @ DR wansfrtne ad0F85 Paso obtined in Das neato partons, @ 1 (Adress) — DR (Adress) te Cycle pect we aor etch and net 6 requed) an nsucon ready tobe executed se cx2cute cI the NSN GE acualyexened An execute ele depends cn ne opcode. A diferent opcode wil require diferent sequence of tps for he frocute cyte. There, et us seuss one example of execute cycle of some simple instruction fr the Purpose of dentiyng some of he steps needed dung tris eycla. SUPPOSE, We have an instton: Add A which adds the content of memory location A to AC ston he resltin AC. This instruction wil be executed inthe following steps ()_Transfr the adress pon (is adress in symbol fom is A) ofthe instruction to the MAR. MAR < IR (Address) ae(©) Read he memory locaton A and big the oprandin the op DR (M) (Ae OR with AC using ALU an bring he eu back AC = AC+DR Exercise Explain various addressing modes. 2 Explain the arithmetic statement X=(A+B)(C+D) Using various address instructions 3. Write down the procedure to evaluate the arithmetic system X=(A+B°O)/(0-E7F) (@) Using a general register type computer (0) Using an accumulator type another (©) Using a stack organisation computer . 4 Whatis addressing mode ? Diferentate between relative and indexeg 2h mode. 5. What do you mean by Zero address instructions ? ©. Discuss the function of a CPU. What are the main sections of a Cpyp functions of each section, 7 What Discus he mB0Se of providing registers in a CPU ? Describe various registers which are usually provid Explain instruction format, What are the varo Discuss them with suitable examples, ‘What are fetch cycles and execute cycles ? to 0 on plain varius types of buses, ws 58 ‘elements of an instruction, 1 gt vl te gspay mPOTaN le oto of ainstucton st 7 xan yon finns 0 ee setae CP ” bo ua , zz12.1 Introduction Ine previous chapter we ISCUSSEH various LO devices. The VO dey 10W a8 coy connected the CPU. The spe0d of UO devices is vary oa cs Tare ty CPUs be utise. inthis chapter, we wil iscuSs various data wanstr senor ©, incompatibi i maxi om an 12.2 Functions performed by the computer system toy W/O devices dle There ae thee functions of computer system to handle UO devieg 4. Assigning a unique address of each /O devices, Main furtion i transter data. Data maybe vansfered tam HO dy main memory or fom main memory to InpuvOUput devices, go kro how much data iso be, transfered and also trom which og be stored oF retrieved, 8 ot i mst ty aontisy ‘Another important factor is, when there are many data items ob there should be no deadlock so all should synchronization. rans, ster data in tne ie, Therefore, we wil dscuss various methods which are used to peiom he og three functions (ae) output interface pt js an oletOnic machine wtih communica Uohingw is rTurcaes with uses troughin cos ike Keyboard, MOUSE and pi eve inter. These external device ae called ; © Cpuisanelectronic device whereas UO devices are electromechanical device (0) ren operate at Very lw speed, w ‘Gru ie 8 vOrY It 88 COMared 16 U0 deve, 1 trese Problems, COMPUC ssl include spacial harduarocompenents 70 SON interface Units (For example, YO gor) between the CPU an VO device none jee and synchronize all input and output ransters e aeons of & come ‘system, that is, the memories, VO devices etc. ‘re, interconnected 1 1M a computer sjsem. The arithmetic loge nt and 8 nite geal gar ith he cantel process unt cat sory POpUAT and 18s expensive techngue, inches necconnectng a out 'U by Using a single bus. This bus consists of oe rane eta tom oro ech congue Each ws ‘Output device as a deco contr whch cont the operation ot he wp Ora itera unt beeen nut esa a shown 4 figure 21 ae Cass FIGURE 121 (251for VO Interface 8 123.1 ¢ ca ks as a media ~* Components of VO Interface orf? works: for between 0 ‘devices and the CPU. There is 0 gy 009200 ifs base sv azn Pa ‘The Components of WO interface (or external interface) are (9) Address Decoder : The address decoder decodes the adcrgy, ‘Output device. As we know that each levice has a unique adn, ey CPU (or processor) sends data toa device oF receive 8 is a significant mismatch between the speed of CPU and peripherals, ® data Blaces the adress ofthat device on the Input! Output synenronizain mechanism may be needeg 08 bus, thn rat ofthe Peieras may be very torent rom hat use bythe CPU, Serocesby he aes cote nh race ata ah ata iat address lines. “moat 2 pedipnerals are clectromectaical and electromagnetic devices and their (©) Data Register : The data resister which contain the ta to bg ie nner of operation 1 een rom the operation ofthe CPU and memory, Brosessor or that receved frm processor. is connecieg i atoy e Sp are electronic devices. Theretore, a conversion of signal values may (6) Status Register : The status register is used to Pet) ying ten wie - ome devo eyo be ead byte proceso oyna hy &y veroau sa 9 ee atom te proses. Micon eee imeflace sts tine sts ester and we reformat mt netion of UO Interface Dt tthe flags equal 01, the CPU reads the de om dann on fu oe “agin equal to 0, datain the data register is no an po yo merce Pe FMS the following functions (@) Control circuits : Contr! q pecoding ofthe address sent on the bus AA block diagram of process: and it connec ng the daa onthe busin cas te device adress on he bus matches through extemal interface is shown in fig, 12.9 1 HO en nae its own address. “ranslatng contol signals into appropiate commands erthe device controler 14. ttregular data i received, channeing this data tothe device so that it can be ‘output or stored, depending on the nature ofthe individual device VO neta 1g Word transfer requests atthe rate required by he device. | ing a normal termination of word transfer interrupt when word has Device Conlon | been transferred, and Vo Deve 10 an ‘abnormal termination of word transfer interrupt due to error condition. FlGURE 122 (207)1 ; 24 Device Controller ‘sk unit, oF moving the paper Functions of Device Control i) Starting, stopping and a (W) Selecting the address where appropriate (vi) Contrting the device step. ) Maintaining device status information toning to transfer The device cor Pe 12.5 Modes of Transfer Binary information received from an external dev later processing. The CPU merely executes the lO ee Fecetang the cont! signals and information rom the inet 1 Individual device. Receiving the status signals trom the device and taki ae Comveing he omat of dla reeves the ee g ) Generating error checking ode (party bit) during wite ge Py, ‘Checking for error in the data received from the device, ‘nia Aboring he command exciton on encautrny ey i) Retrying the command on encountering an enon” VO information to or tom the interac, =e > Communicates with the internal pectic conto signals required for proper operation of the den "ae ard grea i he is uovally stored inmenery Instruction and may scopy (224) 26 Ba ats the device eal 1 0 gists a inves di 0M tne relatively small amount of 8 inet ao 0 Digi, feo OF units. Usually one bye of aa i ranstoed at tine med contlted method, mre a 8 ready fx dete so eps the OPU busy needlessly, oe 8 ASO eto, he Heiter generates a CPU stays ina program loop unt inal performing. fen the deviea and the memory is complata. DMA tage Doe wat spo paint program Controlled Data ‘Transfer Scheme ed contvoed dala transfer scheme, a sofware program. residing 9 ta ransler to or from the CPU. The Accumulator 5. This isa time-consuming process be avoided by using an interrupt mines thatthe device is ready for the computer. Upon detecting the the CPU momentarily stops the task itis processing 'n service program to process the IO transfer, and then returns to the rectly transferred from the UO device to memory without going ‘The CPU is forced to hold on by an VO device untl the data sed when a ty data tobe transfered rom main storage devices tke floppy. disk oF pe sequence of]evnts wich take place to ranstar &word om a device tothe remory ate Tan I instruction is encounters instructions may be ofthe fom ‘command. program being executed. The ‘operation code, device address, device 2, Te CPU sends on UO bus the device asress andthe command to be executed, namely read o wit, 3, Tho davice address on the VO b js recognized by the address decoder of the desired VO device intertace =desirable as it wastes CPU time. Using interrupt thod, CPU waiting time can be reduced as shown SS] | ‘VO Instruction \ Device addres and VO | | command to interface unit Le | _—_ Device address and U0 I command to interface unit | | < | | Interface unit assembles | | wordin DR | | ‘Transfer datato | memory | =a | cure 123 - Siealto CPU | 4 The motace unt conmands he once dvs conte aan 1 | word nthe interface data riser (OR) anda he sae ie Gicnivinazal interface busy fo. As long on ths busy fip-op is st, the in Instruction of program | tetera ay cereus Aa 20)Mep ieee is reset 0 0 5 The device conor file DR. AS Soon a the dali a OR a uaareaiGnae ready tip-top of 32 interface is sotto 1 Labbe deel 8 The CPU may continually inerogate te data red) fp 0 in a 1 | Qets out fhe oop as soon asthe data read fi>-op in eo Hner | appens the contents of DR are transfered tothe specie CPU rages, Tanieihboond through the VO bus | Figure 12.3 shows the program controlled data transfer method, —__ fl | TestoresPC & GPRSand | ; | Se ial ea 12.7 Interrupt Controlled Information Transfer | a 'n program controled transter method synchronization of VO device and CPUig ee ‘achieved by making CPU wait til the information is assembled by the device, As Ee FIGURE 124 (1) VO devices are normally much slower compared to CPU, program controlled transter {90}12.8 Direct Mem is scheme shal when data are ready. thy " devcg My led the device, the Ci (on a stack and gets a spe ‘address), trom where the subrout The processor now begins the exec fon the stack and then pertorms di ata Of the main program after poping cut th Was being executed before interruption. ory Access (Speed Mism: Memory and V0) ? ath beta no oom se 1 Se jg ‘State eet poyan cole baa en Dut Tate PU ten Wage ot Now CPU veya econ ea ide in these operations, at, ‘lower than CPU, pear Girectly make use intervention of CPU. This type f° which is done without hep of CPU, between UO devices and meme at Direct Memory Access or DMA, ae DMA means memory can be directly acces: This is tum adds to the speed of execution 0 by HO doves kan Pg DMA INTERFACE UNIT SHOULD HAVE FOLLOWING COMPONENTS 1. Memory Address Register (MAR) The memory address register contains an addr ‘cation in memory to which data is to be transfer be received, 1085 10 pect the dea red oF rom where dai l Seedy | n star pois th boro ors ob srt rece io after emer by ow ater ech or tars uted 1" 20 oder decodes the adress of the lO daviee. the DMA interface is shown as figure 12.3, Status Register we le Word count Register Control Register a FIGURE 125, sence ce of stops which take place to transfer words from spe sequen sopsitard ee aV0rouests sed, CPUnacets andrei 0 an, ess eee CPU sends everything to DMA (Device address, Corr 8 Am aero amet a unsfer to DMA, CPU is free and can ‘work some a (© Betis at ede.orin other sually breaks the working of CPU for one cycle oF MA act 0 0! (DMA decodes, ly when Jo called cycle-steaing. Cycle steaing occus only pu cycle Address, stars Ng Butore register, nd Resetting Data Regine PY seing, Mn (©) 8 soon as MBR is soy as Daiais tans, Adioss Data Via Data Bus. Ta mah ic me MA wi not erin (9 Atesthe word is tantored te woe COURT in DANA ig er Sei Secrwari rama counts is zero aren + Me Se ae MEMORY Mi A R y] B R roa RY == 4A D cade Caren cru fon CPUSuenders Memon te TEAR) MR Tre best Working i achieved it Memory is vided nwo pons one sept —_ Oa ar oN ont winner et __| wart Memory as shown inure 12.6. Wong ie na ep et whenever needed DMA can diery access memery aa wat ra Se port memory ie. Memory has same tof MAR and MBA osha with both CPU ‘and DMA. Then if CPU is working with memory Needing it, then there is use by CPU then DMA CPU completes its Cur arent means sparent to user. Here trans nd DMA is cept of Data transfer is transpare wil nem Butt OMA needs memory whichis aad yale roof wats happening hn hovel wat he case OUA sons asgaincy, | Wo eae of \ yee and leaves not ceo DMA or Care (304) _——_19 Interrupt Structures Inte Unt, 2 mechan fo carn ate CPU mica ay ’ ae ‘from, , ‘Sxecuting program to another ose le oe Tal ot tema request Steps of itt pen ae, Ina computer, mean = eon the occurence of ws tothe: ‘Re CPU in the form of a signal The cPU [Completes the in rowsives ‘he instruction was exeuting when ery ‘aninte UPL, an inter he vest, “| ‘my ‘The CPU stores the current status of CPU now begins s = Deans the execution of Iter sence suo ‘AS soon as the servi oa ws ‘Service programis executed, the. Beees 1 Comal arstong While transfer vse a beck othe ma pagan ts mt bath oP intial state when the program was inter ri Neat intorrupted. The Cpy eter 8 ny sy The: Content of the Program Counter (PC) or/and (b) The content of all processor registers or/and (©) The content of PSW. There are three types. ‘ypes of interrupts r 1. External Interrupts 2 Internat interrupts 3. Software Interrupts 1. External interrupts External Inter = Interrupts arse form Inpuvoutput (VO) devices, Gicuit monitoring the power supply or from any ot om ating sig, the teal sae a (a), yo devices connected to CPU ing device may intern il 1A erp to wT a rape, come from Hel errouneous US? Ce mon or dala Fr example, did by 200, tack overt 08 497d protection overt, ae qqco peovennExeraland internals ae te 08 ‘mona Interrupts ied by some exceptional |1. i gynotronous in nature rogram 1 10 again winout change uel wit coc exact in the place each time. being executed. oftware Interrupts ptaral and intemal parr ofthe CPU. A sof yt execution ofan st. that behaves the programmer prora For oxale, theeror routines, exerted by pesision inal programing anguages to wit erorrouines. External Interrupts Stes wich ve eee cm | Independent of the program lor some services Ike PU to indicate he ‘A power supply monitoring crt may interrUPt #° ister own in following from signals that occur in the other hand, is being initiated is a special ealinstruction interrupt rather than a subroutine call. It can be used BY procedure at any desired point in the rogram. There 18 8 (907112) Multipte Interrupts Ina mi crocompu transter, ia a ‘ystom several YO devices ca 1¢. While intertacr na ta ae Yet4eha 10 coves sinter, ei Me Faoyin i, "ing “| 2 8 The Hi The mi "eroprocessor has onl only one inten VO devices are connected tot ‘The microprocessor has seve (ne 0 which device has ramto_ specific ccutes esr, ieopecossr modal KOH i nsf fe mropronessor automatic that has been assigned to tho inloru ice which has interrupted. Such a sct levels. It ex treme is also called 0 an — nected sh level. oven : sera mips wort anthem re eet of intr Wve rected is mre than the numb cosas ‘evel When a device interrupt PP 1 VO veral interrupt leve te c nae {0 each inten sil re ne on oe lore Uo, Sh ae ‘ne 008 can immediately knows which interrupt level is high ‘The microp Ming, | tO agate PrOCesSOr 100 ee Siay roo icroprocessor uses poling ‘technique to kn ocessof- are connected to a can een atie Ho, nist sular interrupt level has | interrupted the microPr = ia, | mata 4 interrupt schemes: ate deseriy si Several UO Devices connected to a single Interrupt il, ie 7 When several VO device. “Connected to a single : output ook ° Interrupt ove, t/ aaa cat OF crew. nea 7 hey, ire ‘computer by itself but itis @ specialized type ys on time, a8C2Rain which gon Be HE et '22ch device one by one yy th a pais as shown in figure scr hoes seam = Ne of checking is caled mil Possibly that more than one device may iterupt he saan Tig time. To! SU oi ine Tess ston tapi tammrerneg em micropocessr. The micoprcestor pols deve ng the Ploty has been assigned othem. Ratendsthem nn eM microprc a ‘The microprocessor continues on poy basis asking eagh 2M, (ne whether they interrupted the microprocessor. ey The device poling scheme im consuing an there sy: hy, ae i) Hardware poling (One device connected to each level of interrupt devices: is equal to less than the inlrrupt levels, one device nk |) FIGURE 1283 ve Muttplexer Channel Selector Channet Block-MUX Channel Byte Mutts exer Channel: 's shared amor ame MUX channel ges igo among sev gives m weer Orne chao of In ices ime leomeation is ap 100 mar ee Bass saa, miso eta devios-t for re no ‘opeater pet ad proces i, So MUX-Channel workers in two mod 0 mode, ye-nterleave mode and Burst Mode, Steer hte: aso etLOD hater aparece RNC Sha a anced Does a erneret te won be et ay 5 doce comptes ts vari opr nt anstr operation ase 19) Lob } + seekand latency at® in is carted out just ike selector eas MUX channetand tine a8 $16 anvel. Via Cannel itis possible $= operation. Ate sa Read operation och times wor andis called Block MUX Cl 0 devices simutaneousty. yorchannel, ve ano of iit Peripheral Processor ‘contel Data Cooprator's ere computer fe the concept of Peripher Tre ral Processing Unit (Pl for 180 svi 800.i. Wo ‘Operations. E; OF Ak words wit Jon, a gen compre a for Reading and wrt Per word. Because the 289 3@ the main mer “ PPU words fen . are to be assembiec ida, a ee sdidisasser ° “Shenoy trance oes ha rputer may have 1 es oni ooh 10 PPUs and 12; Coben oe m channels here doe is fins section. vm : Here it simply refers to a conn = lots ot have the a 1 Some nda PPU. econ path baton Figu 2.10 gives a block diagram ee gram of the PPUS and channels, TWOdace Dor Channel Chane FIGURE 12.10 ‘Any of the PPUs 's can access any of registers forthe following pur ¥ of the 12 channels, Each PPUs fas ite om (@) To store the current PPU instucton (0) To store the instruction address (©) Data words (Operands et. exyam conrl anton red by raking OPU Ww normally much I aesirod as it waste Cl reduced or alleviation pd PU ac ‘ice 0810 0000852 csynevonisation seven PU wating can D> to and processor can be done. cesimatesthe timo requis ad command issued early in te eto readinformation roma spectied program several steps a (313) (9 Treproganmer devia. A stat————— smmers aro required todo careful iming estimation which sd prograr eractical and onthe other hand if two independent Pos romery when one program cannot proceed due to lack of bo stated by the processor whan the input fo suspended ‘original program available in memory the processor may De vr suspending the second program. This Is ng the processors resources is known as Multi Programming 1d below. This PROGRAM PROGRAM? r START Es = PROCESSOR INPUTREADY_— SUSPEND NI [Ea RESTARTS, | to effectively overlap processor and /O operation, itis the programs is waiting for VO. The other must keep the processor busy. I both program needs, 3 idle again, As the speed, mismatch is necessary to be able to work to keep the processor always rograms being For muitiprogramming t necessary that when one of have enough computation input data same between VO and the processor's very ‘simultaneously on many programs abs busy. With a large no. suspended due to lack of input is very small taneously on many programs a no. of special For a computer to a work si hardware and software features are required. (315)